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UNIT-7 ARM Architecture

ARM is a family of RISC-based instruction set architectures designed for efficiency, requiring fewer transistors than CISC processors, making them ideal for portable devices. It features a simple architecture with low power consumption, a load-store design, and 32 general-purpose registers across seven operating modes. The instruction set includes data processing, data transfer, and control flow, with a 3-stage pipeline for execution.

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5 views3 pages

UNIT-7 ARM Architecture

ARM is a family of RISC-based instruction set architectures designed for efficiency, requiring fewer transistors than CISC processors, making them ideal for portable devices. It features a simple architecture with low power consumption, a load-store design, and 32 general-purpose registers across seven operating modes. The instruction set includes data processing, data transfer, and control flow, with a 3-stage pipeline for execution.

Uploaded by

NK
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

UNIT-7 ARM Architecture

ARM is a family of instruction set architectures for computer processors based on


a reduced instruction set computing (RISC) architecture

A RISC-based computer design approach means ARM processors require


significantly fewer transistors than typical CISC x86 processors in most personal
computers. This approach reduces costs, heat and power use. Such reductions are
desirable traits for light, portable, battery-powered devices—including smart
phones, laptops, tablet and notepad computers, and other embedded systems. A
simpler design facilitates more efficient multi-core CPUs and higher core counts at
lower cost, providing improved energy efficiency

Introduction:

◼ ARM is a RISC processor.


◼ It is used for small size and high performance applications.
◼ Simple architecture – low power consumption.

General Information:

◼ Load – store architecture


◼ 32 bit data bus
◼ 3 addressing modes
◼ Simple architecture + Simple instruction set + Code density
◼ Small size
◼ Low power consumption

Registers

◼ 32 general purpose registers


◼ 7 modes of operation
◼ Different set of visible registers and different CPSR control level in each
mode.

Instruction Sets (Three instruction types)

◼ Data processing
◼ Data transfer
◼ Control flow
3 – Stage Pipeline (ARM7 – 80MHz)
◼ Fetch
◼ Decode
◼ Execute

A[31:0] control

address register

P
C incrementer

PC
register
bank

instruction
decode
A multiply &
L register
U control
A B
b
u b b
s u u
s barrel s
shifter

ALU

data out register data in register

D[31:0]
Processor modes
The ARM has seven basic operating modes

• Each mode has access to own stack and different subset of registers
• Some operations can only be carried out in a privileged mode

ARM has 16-bit thumb instruction set

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