Analog IC design training

Module - 1: Passives, Frequency & transient response, Amplifiers &

Feedback

Saravanan K

December 9, 2018

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Overview

1 Basics
Devices in Analog IC design
Frequency response

2 Amplifiers and feedback

Feedback
Amplifiers in feedback

3 Appendix
Rotating phasor, Complex plane
Laplace transform & s-domain
Closed-loop peaking Vs Phase margin
Working with the dB20 scale
Second order filter response
2/67
 Basics of Passives

Devices, Expectations, Non-idealities, Poles, Zeros, Step & Frequency response

3/67
Devices in Analog IC design

Ideal sources
Voltage source
Current source
Resistor
Capacitor1
MOSFET
NMOS
PMOS

1
Inductor is avoided unless it becomes impossible to eliminate its need. It is deferred to an advanced course
4/67
Sources

Voltage source Current source

Maintains the output voltage irrespective of Maintains the output current irrespective of
load(Zero source resistance), frequency, load(Infinite source resistance), frequency,
temperature or any other conditions temperature or any other conditions
Real voltage sources display non-zero intrinsic Real current sources display finite intrinsic
(source) impedance → Causes voltage to drop impedance → Causes current to drop at light
at high loadsa . Slope of the characteristic is loads. Slope of the characteristic is the source
the source resistance conductance

V I
Ideal Ideal
V1 I1
Real Real

I V 5/67
Sources

Voltage source

When voltage sources of different values are

connected in parallel, what will be the
effective output voltage?

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Sources

Voltage source Current source

When voltage sources of different values are When current sources of different values are
connected in parallel, what will be the connected in series, what will be the effective
effective output voltage? branch current?
The voltage source that displays the least The current source that displays the highest
source impedance has the say on the voltage impedance has the say on the current at the
at the terminal terminal
Source resistance as in Thevenin equivalent Source resistance as in Norton equivalent
”Low impedance node” implies that the ”High impedance node” implies that the
voltage at the terminal is fixed(Stiff voltage current at the terminal is fixed(Stiff current
source) and it can source/sink output current source) and it can accommodate a wide
a lot before giving up on the voltage voltage swing across it lot before giving up on
the current
6/67
Exercise -1
Vo

1 0.1 1k

+ 2V + 1V
− −

Find the voltage Vo . Find the current through the load resistor and the current drawn from both
sources
Vo

0.1 0.2 0.3 1k

+ + +
1V 1V 1V
− − −

Find Vo and the current sourced from all three supplies

2mA 100k

1mA 10M

Find the loop current value

7/67
Resistor
Ohm’s law : V = R · I
Resistance (R) does not vary with frequency, temperature, voltage across it, process, or any other
conditions
Practical resistors show temperature, voltage and process dependence
Usually negative temperature coefficient, but positive ones are available too2
Resistors realized in a MOS substrate would invariably display voltage dependence due to the
junction diodes at either ends
On die resistors display ±20% variability3
On chip resistors are characterized by R2 (R square) which is the resistance of a square cross
section. Total resistance is obtained as R = R2 wl
High dense resistors posses high R2 yield area advantage, Low dense resistors are best to
implement low valued resistors as they are generally more accurate, display low temperature
coefficient and matching
2
Power dissipated in a resistor4 : V (t) · I (t) = V R(t) = I 2 (t) · R
2
Often both these varieties are used in series to obtain an equivalent resistor with zero temperature coefficient
3
Unlilke external resistors which can be obtained with much better accuracies
4
V(t) and I(t) can be replaced by RMS quantities in this expression
8/67
Capacitor
Voltage acrossR capacitor is the integral of the current through it
Vc = C1 ic dt
ic = C dV
dt
c

To change the capacitor voltage, large I · t is required5 . If the current (charge or discharge)
is small, is required to flow for a long time to cause a change in voltage. If appreciable
change is required in small time, huge amount of current is necessary
Capacitors dont dissipate power. Current and voltage are always in quadrature. Their dot product
is zero. Capacitors rather store energy. E = 12 CVc2
Capacitance between parallel plates of area A and distance d is given by6 C = 0 dr A .
Capacitors are plagued by7
Series resistance, causing finite Q factor
Leakage, modeled as parallel resistance
Voltage dependence
Process and temperature induced variations
5
The actual relationship is integral of I over t, it is explained here for constant I
6
r ≈ 4.2 for SiO2 and 0 = 8.54pF /m
7
External capacitors show inductive behavior after a frequency called as Self-resonance frequency(SRF). This is rarely a problem in ones realized on the die
until the design goes to millimeter wave frequencies 9/67
Capacitor

Capacitors are used for

AC coupling: Couple the signal to an amplifier with the convenience of fixing independent
DC levels (over which the signal rides) at both ends without affecting the signal
Supply bypassing8 : Analog/Digital modules working off a constant voltage supply display
surge current requirements. A capacitor connected locally between supply and ground
functions as a neat low impedance source providing surge current requirements while it
charges itself at a slow rate from the main power source. High frequency currents are
localized reducing emissions
Filtering: In combination with R or L, capacitors can be used to selectively allow or attenuate
signals over a certain frequencies
Stability: Capacitors are essential to construct compensation networks within the die

8
Also known as decoupling
10/67
Capacitor
1
Impedance of a capacitor: Xc = j2πfC
Inversely proportional to both frequency and capacitance and has phase of −90◦
Magnitude and phase plot of impedance of 1.6nF is shown here. Note the -20dB/decade slope910

100

Gain (dB)
50

−80
Phase (°)
−90

−100

102 103 104 105 106 107 108

Frequency (Hz)

9
At 100MHz the impedance magnitude is 0dB(1) which becomes 20dB(10) at 10MHz
10
Refer Appendix, slide 64 for introduction to dB20 scale
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Capacitor types
Capacitor type Description Advantages Disadvantages
Poly-to-poly Between two poly layers in Medium density, Medium Q-factor,
a dual poly process Cheap option Asymmetric ca-
pacitance, high
frequency limit
Metal-oxide-metal Fringe capacitance between High-Q, high fre- Low density
(MoM) comb structures formed by quency operation,
metal layers Symmetry, Easy
availability
Metal-insulator- Between metal layer and in- High-Q, high fre- Low density, Expen-
metal (MiM) terface layer between nor- quency operation sive, Voltage limita-
mal metal layers tion
MOSCAP Between gate and channel High density, no spe- High voltage de-
of MOS transistor cial layer require- pendence11 , Low Q,
ment - Cheapest op- asymmetric, high
tion frequency limit
11
In fact it is so high that it gets used as a varactor
12/67
Poles and frequency response12
R
Vi Vo

R C C

Impedance of R and C connected in parallel is shown 100

Gain (dB)
80
A pole is formed by a combination of resistive and capacitive component. Pole
60
is the location where the characteristic moves from one curve to the othera R ||C
40
curve with a -20dB/decade relative slope difference R

C
20
The plot is for R = 1k and C = 1.6nF . The pole frequency is 100kHz. 0
A pole is characterized by 20dB/decade slope reduction after the pole −20

Phase (°)
frequency in magnitude response and 45◦ lag at the pole frequency and 90◦ −40
lag overallb −60 R ||C

R
−80
The frequency response of the transfer function ( VVo
) (of the second circuit) C

i
remains the same as the impedance characteristic (of first one) shown in the 103 104 105 106 107
plot except the fact that gain plot starts at 0dB instead of 60dB (Why?) Frequency (Hz)

a
Hence poles are called as break-points → The point in frequency where the curve breaks from one path to the other
b
Two poles yield -40dB/decade shift and −180◦ phase with −90◦ phase contribution at the frequency of the poles

12
For brief introduction to complex exponentials and arithmetic refer Appendix, slide: 59
13/67
Zeros

I
Vo
100
R

Gain (dB)
80
C
60
RCseries

1 40 Ronly
Current in to series RC network displays a zero at 2πRC
with Conly
pole at origin (Why?) 20
A zero is formed by a combination of resistive and capacitive 0
component. Zero is the location where the characteristic −20

Phase (°)
moves from one curve to the other curve with a −40
+20dB/decade relative slope difference −60 RCseries

The plot is for R = 1k and C = 1.6nF . The zero frequency −80

Ronly

Conly
is 100kHz.
A zero is characterized by 20dB/decade slope improvement 103 104 105 106 107
after the zero frequency in magnitude response and 45◦ lead Frequency (Hz)
at the zero frequency and 90◦ lead overalla
a
Two zeros yield +40dB/decade shift and +180◦ phase with +90◦ phase contribution at the frequency of the zeros

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Poles and zeros
Number of poles need to be larger or equal to the number of zeros in the transfer
function for realizability13
Poles are characteristic of the system. They are independent of the location of inputs and
outputs whereas zeros depend on the input and output location in the network
Zeros would be present when there exist more than one forward path at any point in a
network14
The lowest pole defines the bandwidth of the system15 . A low valued pole indicates a
system with slow transient response (corresponding to low bandwidth) and a high
frequency pole indicates a system with quick time response
A real first order system can have a pole only on the real axis. On the other hand higher
order real systems can have poles in complex planes but they have to occur in conjugate
pairs(Why?)
13
In impedance transfer functions, the zeros can be one more than poles
14
The two paths need to have different frequency characteristics to form a zero
15
The current discussion is only about first order systems implying there is only one pole, but this statement is true for all systems
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Frequency response - Geometrical interpretation
To evaluate the response mathematically, we substitute s = jω which is the
imaginary axis and vary ω from 0 to ∞
In the Laplace(s) domain, frequency response can be evaluated geometrically
Start from origin and travel along the positive imaginary axis
At each point connect vectors from the poles and zeros to the
observation point on the Imaginary axis.
Magnitude response is given as
Product of Length of vectors from zeros to the Observation point
Product of Length of vectors from poles to the Observation point
Phase response is given as Sum of angles created by the vectors drawn 0
to zerosa - Sum of angles created by the vectors drawn to poles −10

Gain (dB)
This also indicates why at a pole the response does not really make the −20
response pole(become infinity). To cause this the pole/zero should exist on the −30
imaginary axis so that the observation point moves through them −40
Can identify the nature and trace frequency response from the PZ map quickly 0
sRC −20

Phase (°)
The plot is for first order high pass transfer function 1+sRC −40
Try to obtain the frequency response for various PZ map patterns. Try to −60
figure out the pole-zero configurations for bandpass, bandstop, low pass, high −80
pass and all pass filters. You can use two or more poles and zeros.
103 104 105 106 107
a
Angle is with respect to positive real axis measured counter clockwise Frequency (Hz)
16/67
Transfer function
To completely define a transfer function, Gain (at any one frequency where it
is finite and non-zero) is required along with the values of poles and zerosa
The gainb could be the DC gain(s = 0) in a low pass filter, high frequency R
gain(s = ∞) in high pass filter, pass-band gain in band-pass filter, low or high C2
frequency gain in band-reject filter or gain at any frequency in all-pass filter
C1
For example, in the first order RC low pass filter, the DC gain is 1, there is one
ω1
pole at ω1 so the transfer function becomes H(s) = s+ω
1
Z
In the first order high pass filter, the gain at high frequencies is ’1’ which 120 R
s
contains a zero at origin and a pole at ω1 . The transfer function, H(s) = s+ω1
1

100 sC1
1
sC2

The gain term could also be obtained from slope at some part of frequency. To
understand this, try to obtain the gain term of the network shown here. The 80

Mag (dB)
DC gain is ∞ and high frequency gain is 0, so you have to estimate it from the 60
low frequency approximation ( sC1 ) or high frequency approximation ( sC1 )
1 2
40
Understand and appreciate how the individual element impedances combine to
form the overall impedance. Also understand the pole and zero frequencies in 20
the graph shown (R = 1kΩ, C1 = 1.6nF , C2 = 16pF )
0
a
This corresponds to defining the transfer function in the ZPK way, K stands for gain 104 105 106 107 108
b Frequency (Hz)
The gain here is just a constant correction term included after the numerator and denominator is determined due to zeros and poles

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Step response
First order systems can display only monotonic responses(no overshoots)16 , decay or rise
in exponential form with the time-constant given as τ = ω11
At t = τ , the transition would have completed 63% (1 − e1 ) of its journey17
−t
Step response of first order RC low pass filter is given as Vo (t) = (1 − e τ ) · u(t)
1 Vo (t)

0.8 e
− t

τ
Vo (t)(V )

0.6
0.4
0.2
0
−1 0 1 2 3 4 5 6 7 8 9 10 11
Time µs
16
Monotonic response due to poles, but zeros can cause initial kick in the positive or negative direction
17
At 3τ , 95% and at 5τ , 99.3% would be complete. 5 time constants is generally considered good enough to declare as steady state 18/67
Step response
To obtain the step response
Find the value of the output for step input at t = 0 and at t = ∞
At t = 0, the step transition occurs which is high frequency and all capacitors can be treated
as shorts
At t = ∞, there is no transition and it corresponds to DC18 where capacitors are treated as
open circuits
Applying the above circuit conditions start from V (t = 0), connect to V (t = ∞) along the
exponential curve with the time constant τ and you have the complete step response
The preferred step response is a step (Quick without overshoots) however due to the system not
passing a section of frequencies the response can either be slow(low pass)19 to follow step or rise
immediately but fall to zero(high pass) or yield decaying sinusoidal response(band pass)20
Note that step response could be obtained directly from the circuit without finding poles/zeros or
plotting frequency response
18
t = ∞ implies s = 0 due to the inverse relationship between the two domains
19
In feedback control theory almost all systems are low pass in nature where the target is to have neat step response subject to rejecting frequencies beyond
certain frequencies
20
What can you say about step response of a band-stop filter?
19/67
Summary - Poles, zeros, frequency and step response
The ability to sketch frequency response, step response from circuit diagram or both from
pole-zero map is essential21 to control theory and analog design
Frequency response and step response are tied to each other22 . Try to obtain one from
the other and appreciate the domain differences
Only poles determine the way a system recovers from a disturbance. Zeros(if they exist)
only provide initial kick in the response
From circuit diagram, poles and zeros could be obtained analytically. Transfer function
can be written completely after obtaining the gain term. Frequency response can be
plotted. Step response can be obtained directly from circuit diagram or from ZPK
information
Note that the complete analysis is shown to be possible without solving difference
equations or going through Laplace transforms23
21
Without going through the mathematics. The objective is to identify the underlying phenomenon and develop understanding rather improving arithmetic
acumen
22
A frequency response is tied to impulse response whose integration yields the step response
23
For brief introduction to laplace transform and domain refer Appendix, slide: 61
20/67
Exercise - 2
Pole zero map of closed loop system are shown. DC gain is 1 (in cases where it is non-zero). ”P” implies a pole
and ”Z” implies a zero in the map. Sketch the frequency response and step response.
Im
PZ
Re
1
Im
PZ
Re
2
Im
Z P
Re
3
Im
P Z
Re
4
5 Same as [3] with the zero at the same magnitude but on the right side (Positive zero). What difference does
it yield in step response?
21/67
Exercise - 2
For the circuits shown, find the pole zero locations, sketch the frequency response and step response. Try to do it
analytically rather than going through the complete math. If you had to go through the math, try to understand
the result (the poles, zeros and the overall response)

C2 C

Vi Vo Vi Vo Vi Vo
R1 R R1
R2 C C1 R2

C2

C1
Vi Vo
R1
R2 Vi Vo Vi Vo
R1 R1
C1
R2 C2 R2 C2
C1

22/67
Recommended self reading

Butterworth polynomial and pole pattern

Poles, zeros and their effect on frequency and step response
Solve first order circuits in the laplace domain

23/67
Worked out problems
Pole zero map of closed loop system are shown. ”P” implies a pole and ”Z” implies a zero in the map.
Im
P
Z
P Re
1 Bandpass
Im
P
Z (2)
P Re
2 Highpass
Im Z
P P

Z
Re
3 Notch
ImPZ

PZ
Re
4 Improved Notch
5 N poles placed at uniform intervals on the semicircle on the left half plane of radius 5 → Butterworth low
pass filter of order N with ωc = 5rad/s. What happens if on the same map you add N zeros at the origin?
24/67
Right-half plane zeros

The poles should always lie only on the left-half plane for stability
reasons
The zeros could lie anywhere without causing instabilitya
(1+ zs )(1− zs ) Im
Transfer functionb : 1
(1+ ps )
2

Phase : tan−1 ( zω1 ) − tan−1 ( zω2 ) − tan−1 ( ωp ) = θz1 − θz2 − θp

r r
2 2
1+ ω2 1+ ω2
z z
1 2
Magnitude: 2 θz 1 θp θz 2
1+ ω2
p
z1 p z2 Re
A right half plane zero behaves like a left half plane zero in the
magnitude response and a left-half plane pole in the phase response
a
While they dont cause instability just by their presence in the right-half plane, they cause stability issues which will be detailed soon
b
Dont bother about realizability of this transfer function. It is just used here to illustrate the effect of positive zero

25/67
 Right-half plane zeros
Evaluate the transfer function for the circuit shown
Observe that this TF exhibits right-half plane(positive) zeroa C2
−1

Sketch the frequency and step response Vi Vo

Note that the phase reaches −180◦ unlike other first order R
circuitsb C1

This additional phase lag causes issues in feedback circuits

Note that the step response starts from negative values. The
system starts its journey to a positive value by going negative
and recovering later
When enclosed in a feedback circuit the positive zeros reduce
damping → Create stability problem
Systems with only negative zeros are called Minimum-phase
systems. Any system can be represented as a sum of an all-pass
TF and a minimum-phase TF
a
Passive elements cannot combine to yield positive zero, it needs an inverting element(amplifier)
b
This circuit is still first order as effectively it displays one degree of freedom (Vo defines the voltage across both capacitors - only one state
26/67
variable)
 Right-half plane zeros
Evaluate the transfer function for the circuit shown
Observe that this TF exhibits right-half plane(positive) zeroa C2
−1

Sketch the frequency and step response Vi Vo

Note that the phase reaches −180◦ unlike other first order R
circuitsb C1

This additional phase lag causes issues in feedback circuits

Note that the step response starts from negative values. The
system starts its journey to a positive value by going negative
0
and recovering later −5

Gain (dB)
When enclosed in a feedback circuit the positive zeros reduce −10
−15
damping → Create stability problem
−20
Systems with only negative zeros are called Minimum-phase 0
−50

Phase (°)
systems. Any system can be represented as a sum of an all-pass
−100
TF and a minimum-phase TF −150

a
Passive elements cannot combine to yield positive zero, it needs an inverting element(amplifier) 102 103 104 105 106 107 108
Frequency (Hz)
b
This circuit is still first order as effectively it displays one degree of freedom (Vo defines the voltage across both capacitors - only one state
26/67
variable)
Second order systems

A first order low pass24 system has only one parameter (τ ) that defines the response
completely. It does not exhibit overshoot and the response can be deemed slow
A second order system brings in flexibility in the step response as it can be made to be
slower(like a first order system) or made to respond faster with a little overshoot or it can
be made to show excessive ringing
A second order system also approximates filter characteristics better compared to a first
order one
For stability reasons higher order filters are realized using cascades of second order systems
It is essential to understand the step response and frequency response of second order low
pass filters as it will be applied to analyze complex systems

24
Low pass system is considered here as it is the one of interest in feedback systems. The same concepts apply to other varieties as well
27/67
Second order systems

General form of second order low pass transfer function is2526

A0
H(s) = 2ζs s2
1+ ω + 2
n ωn
where the DC gain is A0 , damping factor is ζ and ωn is the undamped natural frequency
s2
If the numerator is A0 · ωn2
, it is a high pass filter27 (How?)
Poles are the roots of the denominator and as shown all filters can have the same poles
but with different zeros can yield a variety of filter responses
When ζ = 0, the poles are at s = ±jωn (On the imaginary axis). When there is no
damping, the system sustains oscillations at a frequency of ωn
25
I prefer writing transfer functions as (1 + ps ) form as it shows DC gain directly. Also the result of magnitude and phase computations remain the same
1
when either ω or f is used
26 A0
Another form of writing the transfer function: H(s) = , where Q is the quality factor. The former is used in control theory whereas the latter
1+ s + s2
Qωn ω 2
n
1
is used in oscillators. The relationship is Q = 2ζ

27
Find the numerator for bandpass/bandstop filters
28/67
Second order systems
Im

When ζ >> 1, the poles are real and separateda . System condition is overdamped.
jωn

The response is similar to a first pole system of that of the red poleb
At ζ = 1, the polesc meet each other which is when the system is called critically θ
Re
damped, now the system displays optimal rise time without overshootd
As ζ < 1, the poles break away in to the complex plane and as ζ further reduces, the −jωn
poles move in a circular path ending at ωn on the jω axis at ζ = 0
ζ = cos(θ) where θ is angle of the complex poles wrt the negative real axis as shown
In the second plot red lines indicate the locus of constant ωn but varying ζ whereas
the blue lines indicate the locus of constant ζ but varying ωn ζ2 ζ1
Im

a
At their initial locations indicated in the first plot
b ω2 ω1
Why? It is like blue pole is not felt
Re
c
In this exercise the poles move only due to change in ζ with a fixed ωn
d
Poles are at the breakaway point on the real axis

ζ2 ζ1

29/67
Second order systems

With the knowledge of the relationship between pole locations and frequency response
obtained earlier,
When the poles split in to complex plane, magnitude peaking becomes possible
Step response overshoot shows up immediately as ζ < 1, but magnitude peaking starts later
(Why?)
When the poles are complex and close to the imaginary axis, the damping factor is low which
shows up as overshoot in step response and magnitude peaking in frequency response
Usually we have a target damping factor in the design process28 . Variations in ωn only
change the time scale in the step response. Only ζ changes the profile of the step response
Self reading: Time response of second order system
The frequency and step response of various filters (for the same ζ) are shown in
Appendix. Refer slide: 66

28
ζ = √1 which is the butterworth response is often preferred
2
30/67
Second order systems
1
The step response in s-domain: C (s) = 2
s(1+ 2ζs
ω
+ s2)
n ωn
p
The poles are at29 −ζωn ± jωn 1 − ζ 2
−ζωn t
1 − ζ 2 t − tan−1 ( √ ζ
e
p
Step response or under-damped case, c(t) = 1 − √ cos(ωn ))
1−ζ 2 1−ζ 2

1.4 ζ = 0. 3

1.2 u(t)

1
Vo (t)(V )

0.8
0.6
0.4
0.2
0
−2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
Time µs
29
When the damping factor is high (ζ > 2), the poles can be approximated as p1 = −ω
2ζ
n and p = −2ζω
2 n
31/67
 Amplifiers and feedback

Amplifiers as a block, Negative feedback, Stability

32/67
Feedback
The forward gain is A and the feedback gain is β
A
The closed loop gain, C = 1+Aβ
The only interest in feedback analysis is to keep the closed loop poles (Roots of
1 + Aβ = 0) on the left half plane with sufficient damping. We are not highly interested
in the closed loop zeros3031
Self-reading: Block diagram arithmetic, Moving summing points, take away points and
transfer function computations
Vi Verr Vo
+ A
−

Vfb
β

30
Open loop zeros(Open loop indicates the loop gain which is Aβ) are important because they change the closed loop pole locations
31
Closed-loop zeros only change the initial value in step response which dont change the way the response reaches the steady state but can change the settling
time significantly. It may become important from this perspective, but on the whole we are concerned only about the pole locations largely
33/67
Block diagram computations
Block diagram computations
Ignores loading effect of the succeeding blocks32
Assumes unilateral blocks. i.e Signals flow only in one direction
Assumes that no signal overflow occurs causing any change in transfer function
In reality these conditions are not true and in addition, the summers will in general be non-linear. Yet block
diagram computations make it easy to work with and provide important insights. They are extensively used to
analyze feedback systems
The transfer function from various inputs to the output in the diagram shown can be written33 readily
Vo A1 A2 A3
V
= V Vo = V V
o
= 1+A A A β
i i,noise 4 1 2 3

= 1+A AA3 A β , V
Vo
V2 V3
o
= 1+A A1 A β
1 2 3 1 2 3
Feedback shapes the response depending on the forward gain. Note that the poles are the same in all cases
Vi,noise V1 V2 V3
Vi Vo
A1 A2 A3
−

V4

32
This has to be accounted for in the transfer function manually
33
Applying superposition try computing these by writing simple arithmetic expressions
34/67
Preferred closed-loop pole locations

Im For absolute stability, all closed-loop poles should lie only on the
left half plane
Systems which may comply to the above condition may still be
unusable in reality due to the excessive settling times and severe
overshoots
The objective of feedback system design is to achieve acceptable
step response. This is characterized by the closed-loop pole
locations which observe a certain ζ
The red lines indicate the locus of poles with constant damping
Re factor. The poles that are closer to the real axis have smaller
damping and preferable
The poles to the right of the blue lines display excessive delaya
even though they may be stable
The shaded area is the preferred one for the location of closed loop
poles
a
In some cases longer delay may be intentional(low pass filter with low cutoff frequency)

35/67
Relative stability
Barkhausen criteria
For a circuit to oscillate, the loop-gain magnitude, |Aβ| = 1 and
Loop-gain phase3435 ∠Aβ = 180◦
The Barkhausen criteria only shows under what conditions a circuit would oscillate but does not indicate what to
look for to design a stable system
To help with this, relative stability metrics are defined in the frequency domain36 : Phase margin and Gain margin
indicate how far away the system is before the onset of instability
The frequency at which the loop-gain magnitude reaches 0dB or 1 is known as the gain cross over frequency (or
more popularly as Unity gain bandwidth (UGB)37 ) and the frequency at which the phase reaches −180◦ is known
as the Phase cross over frequency
The difference between −180◦ and the loop-gain phase at UGB is called as the Phase margin → The amount of
phase lag the loop could tolerate before becoming unstable
The inverse of the magnitude of gain at phase crossover frequency in dB scale is the Gain margin→ The amount of
(phase-less)gain increase(in dB) the system can tolerate before becoming unstable
34
This is assuming that the intended connection is negative feedback which by itself yields 180◦ phase shift to the loop requiring only additional 180◦ to
oscillate. If it was a positive feedback loop to begin with this number will be 360◦
35
The oscillations can occur at these phase values + any integer multiple of 360◦ , but that detail is ignored here as we are not trying to build oscillators but
stable control loops
36
The relationship between the stability metrics in the two domains ζ and Φm is discussed in Appendix, slide: 62
37
This is strictly valid only when β = 1, but this term is used casually
36/67
Phase and Gain margin
The Bode loop-gain magnitude and phase plot is
shown
The poles are at 10kHz, 5MHz and at 500MHz.
There are no zeros 60
40

Gain (dB)
3 pole system is considered here to show gain margina
20
The phase margin is given asb
0
Φm = 180 − tan−1 ( ff ) − tan−1 ( ff ) − tan−1 ( ff ) where
1 2 3 −20 GM
fu is the UGB, f1 , f2 , f3 are the poles of Aβ
−40
If the frequency f1 in the expression −tan−1 ( ff )
is 10x
1
larger compared to f under consideration, it is 0
approximated as 0. Similarly it is approximatedc as
−50

Phase (°)
−90◦ if f1 is 10x smaller than f . These approximations
can be quite handy in analyzing responses −100
The gain margin is given as GM = −20log10 (|Aβ|)
−150 Φm
evaluated at fpc which is the phase crossover frequency
−200
a
What is the gain margin of a two pole system?
102 103 104 105 106 107 108
b
Frequencies are shown in Hz as the plot axis is in Hz. The expression remains same if the variable is ω as well Frequency (Hz)
c
If f1 is too high, the pole is too far to add significant phase and if the pole frequency is much smaller, the pole is considered to have
contributed all of 90◦
37/67
Stability metrics: Solved example
The DC gain of an open loop amplifier connected in unity gain
feedback(β = 1) is 1000. The amplifier has only two poles and no
zeros. The first pole is at 1kHz, the phase margin of 45◦ . Find the
location of the second pole

38/67
Stability metrics: Solved example
The DC gain of an open loop amplifier connected in unity gain
feedback(β = 1) is 1000. The amplifier has only two poles and no
zeros. The first pole is at 1kHz, the phase margin of 45◦ . Find the
location of the second pole
Since the poles are well apart, at the second pole the phase 60
contribution from the first pole is −90◦ . 40

Gain (dB)
Φm = 90 − tan−1 ( ffu ) = 45◦ 20
2
0
−→ fu = f2
−20
DC gain =1000 = 60dB. After the first pole, the magnitude −40
response starts to fall at 20dB/decade. It takes 3 decades from the 0
first pole to reach 0dB which happens at fu −50

Phase (°)
The second pole f2 = fu = 1MHz
−100
The characteristic is shown. The phase characteristic matches −150 Φm
exactly with our expectations, but the gain one is off considerably
The second pole contributes 3dB at f2 which is not 102 103 104 105 106 107
accounted for in the calculations resulting in an error of 3dB a Frequency (Hz)
The approximations on phase matches with the results very
well
a
Which is perfectly acceptable for hand calculations
38/67
On DC gain, Pole separation and Stability
With reference to the previous example, find what happens to the phase margin38 under the
following conditions
With the poles remaining at the same location, what would happen to the phase margin if the DC
gain is increased to 80dB or decreased to 40dB?
With the same 60dB DC gain, f2 = 1MHz, f1 decreases or increases?
With the same 60dB DC gain, f1 = 1kHz, f2 decreases or increases?
At a fixed DC gain, Phase margin is a function of the pole ratio (Or pole separation in the log plot)
Larger the pole ratio ( ff21 ), better is the phase margin
If for the same pole ratio which presented a healthy phase margin, the DC gain is increased, phase
margin degrades
Phase margin decreases with increase in the DC gain
To return to the healthy phase margin, the pole ratio need to be increased proportionately
A 60dB gain required 60dB separation between the poles for 45◦ PM, a 80dB gain requires 80dB
separation
Large DC gains are preferred as they keep the steady state error low, but they call for huge
separation between the first two poles39 which compounds the stability problem
38
This is a second order system where gain margin is undefined
39
If there is a 3rd pole, it needs to be far away from UGB too
39/67
 On DC gain, Pole separation and Stability

50
Gain (dB)

−50
0
−50
Phase (°)

−100
−150 Φm

102 103 104 105 106 107

Frequency (Hz)

The reference amplifier

characteristic is in black. The DC
gain is made lower(red) and
higher(blue). The phase
characteristic does not change.
Observe the phase margin

40/67
 On DC gain, Pole separation and Stability

50 50
Gain (dB)

Gain (dB)
0 0
−50
−50
0
0
−50
Phase (°)

−50

Phase (°)
−100
−100
−150 Φm
−150 Φm

102 103 104 105 106 107

Frequency (Hz) 102 103 104 105 106 107
Frequency (Hz)

The reference amplifier

The reference amplifier
characteristic is in black. The DC
characteristic is in black. The
gain is made lower(red) and
first pole is made lower(red) and
higher(blue). The phase
higher(blue). Observe the phase
characteristic does not change.
margin
Observe the phase margin

40/67
 On DC gain, Pole separation and Stability

50 50 50
Gain (dB)

Gain (dB)

Gain (dB)
0 0 0
−50
−50 −50
0
0 0
−50
Phase (°)

−50 −50

Phase (°)

Phase (°)
−100
−100 −100
−150 Φm
−150 Φm −150 Φm

102 103 104 105 106 107

Frequency (Hz) 102 103 104 105 106 107 102 103 104 105 106 107
Frequency (Hz) Frequency (Hz)

The reference amplifier

The reference amplifier The reference amplifier
characteristic is in black. The DC
characteristic is in black. The characteristic is in black. The
gain is made lower(red) and
first pole is made lower(red) and second pole is made lower(red)
higher(blue). The phase
higher(blue). Observe the phase and higher(blue). Observe the
characteristic does not change.
margin phase margin
Observe the phase margin

40/67
On DC gain, Pole separation and Stability
Stability criteria requires a single pole roll off. A slope of -20dB/decade around UGB.
If you were presented with a not-so-stable system, what are the options to improve stability?40
Reduce DC gain → Increases error in the feedback system
Move the second pole to high frequencies → Either reduce the R or C component associated with this pole.
C is not what you added intentionally41 , so dont have control to reduce it. Decreasing the R component
again decreases DC gain42
Move the first pole to lower frequencies → Decreases bandwidth which may not be preferable. Calls for
increase in capacitive component43 Including intentional capacitance to the circuit. Increases die area
After trying to move the second pole out, reducing the DC gain to sufficient-for-application levels, one
needs to look at
Reducing the first pole by introducing capacitance there
Introduce a zero to cancel the second pole
Pole-splitting which simultaneously pushes the first pole in and second pole out44
40
You can have all desirable properties in the overall amplifier: High DC gain, high bandwidth, low power, low area, etc but if it is not stable it is useless. You
would be willing to throw away all of these to achieve stability which is why the process of design-for-stability is called as Compensation. Often you have to
compensate DC gain, bandwidth, power and area among other things to buy stability
41
Often you have to serve a certain minimum load capacitance which may compound the problem
42
In amplifier stage, the gain is given by gm R
43
Why cant we increase the resistive component here?
44
More on this later 41/67
Exercise - 3

Two two-pole systems H1 and H2 exhibit complex pole pairs of 900 ± j436 and
1125 ± j992 respectively. Find which one has higher damping and bandwidth
Find the ratio required between UGB and second pole to achieve phase margin of 60◦ for a
system that has more than 40dB DC gain. The system has only two poles and no zeros45
1000
An amplifier transfer function is given as s(1+ ps ) . What is the condition on p1 to achieve
1
a minimum phase margin of 60◦
An open loop amplifier having 3 poles at 10kHz, 1MHz and 10MHz with a DC gain of
1000 is connected in unity gain feedback. You are free to introduce a single left half plane
zero. What is the ideal zero location to achieve maximum phase margin?

45
Hint: For a phase margin of 60◦ with DC gain more than 20dB the two poles will be well separated(Why?), so the first pole contributes a phase of −90◦
42/67
Amplifier as a block

V+ +
Vo
A
V− −

Amplifier in discussion here takes two inputs. The output46 , Vo = A(V+ − V− )

Ideal amplifier is expected to show
Infinite gain (A = ∞)
Infinite bandwidth and slew rate
Output does not depend on anything other than the two inputs −→ PSRR = ∞, CMRR = ∞
Zero noise, zero offset, No non-linearity (THD = 0)
Zero bias current, Infinite input impedance(Differential and common-mode)
Full rail input common mode range, full rail output swing47

46
The inputs are called as non-inverting and inverting. It wouldnt be right to call them as positive and negative
47
Ideally the supply itself doesn’t exist and these limits extend to ∞
43/67
Non-inverting amplifier

The Opamp non-inverting amplifier is shown.

All negative feedback circuits try to achieve one feat
Keep the input difference voltage as close as possible to zero.
The ability to do this depends on the value of loop-gain at Vin +
DC Vo
To analyze the circuit, appreciate two things −

The input difference is 0 (Vin = Vfb ) Rf

The opamp input terminals carry no current. No current Vfb
enters the input terminals of the opamp
The first rule tells that Vin appears across R1 , so the current R1
through it is VRin
1
According to the second rule, all of the current in R1 must pass
through Rf . So the voltage across Rf is Vin R
R
f
.
1
Vo is the sum of the voltages across the two
[Link] = Vin + Vin R
R
f
→ VVo = 1 + R
R
f
1 in 1

44/67
Non-inverting amplifier

The circuit equations can be written and fit in to a block Vin +

Vo
diagram model −
Rf
The amplifier gain is A
Vfb
The feedback factor which corresponds to the amount of
output that is fed-back is β, which is equal to Rf R+R
1 R1
1
A R1 +Rf
The closed loop gain is C = 1+Aβ = R1 +Rf
A
+R1
Vi Verr Vo
The gain tends to the one derived earlier as A → ∞ +
−
A

The expression also indicates the error in the output when Vfb
β
gain is not ∞

45/67
Negative feedback
Vi Verr Vo
+ A
−

Vfb
β

Real amplifiers come with their own poles and finite gain
A(s) 1
C (s) = 1+A(s)β(s) = 1 +β(s)
A(s)
R1 R2
This expression is similar to the impedance of two resistors in parallel (R1 ||R2 = R1 +R2 )
1
The closed loop gain approximates either β(s) or A(s) whichever is smaller
1
Graphically CL(s) can be constructed by plotting A(s) and β(s) and tracing the lower of the two
curves
1
When |A(s)| > |β(s)| (Within the UGB) , CL(s) u β1 and otherwise, (Outside UGB),
CL(s) = A(s)48
48
This is a really useful approximation. It must be treated that way. The approximation works well everywhere except near the closed-loop bandwidth where it
errs a little
46/67
Inverting amplifier
The Opamp inverting amplifier is shown.
As the difference between the input terminals is zero and the
non-inverting terminal is groundeda , V − = 0
Vin
Vin appears across R1 , so the current through it is R1
As no current passes in to the opamp input terminals, all of this
current has to flow through Rf
Rf
The voltage developed across Rf = V
R1 in
Rf
Vo is the voltage drop across Rf as it has its other terminal at Vin
−
groundb , Vo = − RR
f
Vin −→ VVo = − RR
f
R1
Vo
1 in 1
Note that this configuration is obtained through minimal changes +

from non-inverting amplifier

The classic feedback block diagram in its simplest form cannot
represent inverting amplifierc
a
This is called Virtual short. V + is a real short whereas V − takes ground potential with no current to ground due to negative feedback
b
The negative sign appears as the current runs from ground to Vo rather than the other way
c
More on this later

47/67
Exercise -4
A0
A unity gain non-inverting amplifier with amplifier transfer function A(s) = 1+ ps
. Verify that the
1
bandwidth of the closed loop is (1 + A0 · p1 ). The bandwidth gets extended by the same factor the gain
reduces. This is known as the constant gain-bandwidth product property. Show that if the closed loop
gain is raised to N, the bandwidth decreases from the unity gain case accordingly
The amplifier transfer function is ωsu . This transfer function corresponds to integrator. Integrators make
the DC gain infinity and therefore steady state error zero. The feedback resistor R is connected between Vo
and V −. A capacitor(C ) is connected from inverting input to ground. Evaluate the conditions for stability
Evaluate the transfer function for the circuits shown. In the first circuit, the amplifier is ideal. In the
second circuit the amplifier has DC gain of 1000, first pole at 1kHz, second pole at 1MHz without any
zeros. The closed loop gain is 2(Both resistors are equal). Find the required R and C values to achieve a
minimum of 55◦ phase margin
Vin +
Vo
−
R1 C
Vfb

R1 Rf
Vin
− R1
Vo
Vref
+

48/67
 Gain-bandwidth product

A0
An amplifier with transfer function, A(s) = 1+ ps is closed in a unity
gain loop
The closed loop bandwidth is ωu = (1 + A0 )p 60 A0

50
If the closed loop gain is increased to 2 (With β = 0.5), the 2

4
40
bandwidth decreases proportionally and becomes ω1 = ω2u 10

Mag (dB)
30
A0 ×p 20
In general for a closed loop gain of N, the bandwidth is N
10
a
This is the popular ”Constant gain-bandwidth property” where 0
A0 × p is the gain-bandwidth product −10
−20
The amplifier magnitude response for different closed loop gains
are shownb 101 102 103 104 105 106 107
Frequency (Hz)
a
This is not applicable for all negative feedback systems. Strictly speaking this holds only for linear voltage-feedback amplifiers with single
pole, but they form the majority of systems we would encounter
b
When β is zero, the closed loop gain becomes open loop gain, A0

49/67
Steady-state error
A closed loop system is expected to(at a basic level)
Display acceptable response to a transient disturbance (Overshoot, delay and settling time)49
Display negligible difference between the target and final value
At steady state, the error between the intended and the actual output value is the steady-state error.
Vi (s)
Verr (s) = 1+A(s)β(s)
Vi (s)
ess = lim s · Verr (s) = lim s ·
s→0 s→0 1 + A(s)β(s)
The step response will never reach ’1’, but it will settle at a value away from ’1’ by ess
If the amplifier is 1+A0s , the steady state error is 1+A1
0
, which can be made small only by increasing A0
ωp

Increasing A0 has huge stability implications → Cant be done without a price

Vi Verr Vo
+ A
−

Vfb
β

49
Filtering is a subset which applies to electrical systems: this requirement too gets covered here
50/67
Steady state error

Vi (s)
ess = lim s ·
s→0 1 + A(s)β(s)
1 1
For step and ramp input, Vi (s) equals s and s2 respectively
The unity gain amplifier shown in the previous slide suffers non-zero steady state error to a step
input and growing steady state error to a ramp input
To make the steady-state error to a step-input zero, a pole at origin is required

Vi (t) Laplace transform Function

1
u(t) s
Step
1
t · u(t) s2
Ramp
t2 1
2
· u(t) s3
Parabola

51/67
Type and order of amplifiers

The amplifier example shown in the previous slide corresponds to a proportional control loop(No
poles at origin - Type-0 system). The gain (A0 ) determines ess
If the amplifier had a pole at DC50 , the steady state error for a step-input ess = 0. Verr (t) → 0
The total number of poles in the amplifier51 transfer function is noted as the Order of the system
The total number of poles at the origin(s=0) indicate the type of the system. Systems with no
poles at origin are Type-0 system. A type-N system will have N-poles at origin52
A Type-1 system will display ess = 0, constant and growing for step, ramp and parabola inputs
respectively
A Type-2 system will display ess = 0, 0, constant for step, ramp and parabola inputs respectively

50
A pole at DC implies integration. The system does not need an input to sustain a finite output. On the other hand if there is an error, however small it is,
the output will move causing the loop to respond and make the error zero
51
It applies to the overall loop-gain, we call this for amplifiers with the assumption that a forward amplifier is connected in unity gain feedback
52
The TF will be of the form N...
s (...)
52/67
Increasing the type of loop-gain

ωu
A simple type-1 amplifier can be written asab A(s) = s

Gain (dB)
50
1
The unity gain closed-loop TF : 1+ ωs
. Here ωu represents the
u 0
closed-loop bandwidth or the gain-bandwidth product
−50
Steady-state error to a step input is zero and independent ofc ωu
−80

Phase (°)
The frequency response of the amplifier is shown. The closed-loop
system would be unconditionally stable and display zero steady −90
state error to step input −100

a R
102 103 104 105 106 107 108
This is an integrator. The time response of this amplifier is Vo (t) = ωu Vi (t)dt
Frequency (Hz)
b
The numerator is written as ωu as it has units of frequency. ωu is the point at which the amplifier magnitude response reaches 0dB
c
The error to ramp input will depend on ωu . Find that

53/67
Increasing the type of loop-gain
If increasing the type of the loop-gain yields benefits listed earlier,
why not build such amplifiers
It is difficult to obtain perfect integrators. Practical systems
will have finite gain at DCa
As type increases, order increases. The loop magnitude

Gain (dB)
response must have -20dB/decade slope when it crosses 0dB 100
gain for a stable system. Increasing in-band poles cause
higher rate of roll-off 0
Need in-band zeros(N-1, where N is the number of in-band
poles) to achieve stability. −100

Phase (°)
The zeros are difficult to generate and controlb and they
may cause unnecessary overshoot and increase in noise −150
Bode plot for type-2 system with an in-band zero is shown
For all practical purposes, electrical systems dont employ more 102 103 104 105 106 107 108
than 2-poles at the originc Frequency (Hz)

a
This would be the goal of building amplifiers. Building an integrator with minimal leakage(a leaky integrator is the one with finite DC gain
- Minimal leakage corresponds to maximum DC gain) with no other pole in vicinity
b
Zeros always come with poles. We try to keep these poles away while trying to bring the zero in
c
A rare notable exception is the PLLs used in space applications where ess = 0 is required to track objects that are accelerating
towards/away
54/67
Exercise - 5

ωu
A type-I amplifier with TF: s(1+ ωsp ) is closed in a negative feedback loop of closed loop gain of (a)
1 (b)3. If ωu = 2π · 100kHz,
1 Find ωp to achieve phase margin of 60◦ in both cases
2 Find ζ corresponding to the previous part
An amplifier defined by A(s) = 1+5000s is connected in negative feedback with a closed loop gain
2π·1kHz
of (a) 1 and (b) 5. x(t) = 0.1sin(2π · 1MHz · t) is applied at the input. Write the (approximate)
magnitude and phase of the output for both cases (gain of 1 and 5)
1000(1− ωsz )
Amplifier A(s) = (1+ ωs )(1+ ωs ) is closed in unity gain negative feedback. The poles53 are located
p1 p2
at 1kHz and 10MHz.
1 Where should the positive zero be located to obtain a phase margin of 60◦ ?
2 At the location obtained in the previous part, if you replace the zero with a pole(left-half plane with the same
value as the right-half plane zero) what is the phase margin?

53
Note the difference in units between Hz and rad/s
55/67
Worked out exercises
Evaluate the transfer function of the following circuits
C

Vin
(a) −
Vo −1
R Ans: sRC This is an inverting integrator54
+

Vin
(b) −
Vo
C Ans: −sRC This is an inverting differentiator
+

R2 Rf
V2

V1
(c) −
Vo −Rf −Rf
R1 Ans: Vo = R1 V1 + R2 V2
+

This is an inverting summing amplifier. The output is a linear sum of the two inputs55
54
This circuit is not bias stable as it does not have DC feedback. More on this later
55
This is made possible by the virtual ground node. The individual transfer functions are independent of each other
56/67
Worked out exercises

Rf

R1
Vin
−
Vo Rf
Vref Ans: Vo = Vref (1 + R1 ) − Vin RRf1
+

An inverting amplifier causes negative outputs for positive inputs necessitating dual
supply for the amplifier56
To invert the signal with a single supply voltage, the output DC bias needs to be
increased to appropriate levels. This is achieved in this circuit with the use of Vref
The output is obtained through superposition57

56
The amplifier output is limited by the supply rail voltages
57
From Vref it is non-inverting amplifier whereas from Vin it is inverting amplifier
57/67
 Appendix

Rotating phasor, Complex plane, Laplace transform, Working in the s-domain,

Relationship between damping factor(ζ) and phase margin (Φm ), Working with dB20
scale, Second order filter response

58/67
Rotating phasor
x(t) = e jθ(t) , where θ(t) (Phase in radians) is a
linearly increasing function of time indicates an
ideal rotating phasora .
Y(j)-axis projection results in Asin(ωt)b . This
Im A
relationship is shown asc e jωt = cos(ωt) + jsin(ωt)
Phase(θ) increases by 2π every cycle and the rate
0o of phase accumulation is angular frequency ω
Re T t ⇒ ω = 2π expressed in rad/s.
T
ω = dφ
R
dt φ =
, ωdt
-A T is the time-period of oscillation in seconds
sin(0o ) = 0.0
Verify the following equations with the phasor:
jωt −jωt jωt −jωt
cos(ωt) = e +e 2 and sin(ωt) = e −e 2j
a
Hit on play to run the animation
b
Similarly X-axis results in cosine component (not shown here) 59/67
 Complex plane

Two axes are required to represent a complex number. It could be Cartesian

coordinates (Real and Imaginary axes) or polar (Magnitude and phase)
Im
Cartesian coordinates are easier to work with for additions whereas polar makes it
easy when multiplication is involved
b
a + jb = re jθ where r = sqrt(a2 + b 2 ) and θ = tan−1 ( ba ) is the phase angle between
the vector (0,0) to (a,b) and the real axis in the counter-clockwise direction. Also r
a = r · cos(θ) and b = r · sin(θ)
The inverse tangent is a 4-quadrant operation. Careless application of the expression θ
by bringing the ”-” sign in the denominator to numerator will result in phase limited a Re
to I and IV quadrant alone( −π2
↔ π2 ) aloneab
The rotating phasor can be written as 1∠θ. If the magnitude is a function of time
(1e (σ+jω)t = e σt · e jωt ) represents an increasing or decreasing spiral. Equivalently
the sine and cosine will show increasing/decreasing envelope depending on whether
σ > 0 or not respectively
a
Numbers −1 + j and 1 − j display a phase angle of 135◦ and −45◦ respectively. Casual application of the phase angle expression would
yield −45◦ for both
b
Calculators which perform the rectangular to polar or vice-versa conversion show the right phase, but direct calculation of the phase
expression in the same calculator would show wrong value for II and III quadrant elements

60/67
A brief introduction to Laplace transform and s-domain

e st for complex s represents a wide variety of signals58 → Rising/falling exponentials, Sinusoids with
increasing/decreasing amplitudes or constant. s represents the complex frequency in rad s
Applying this input to an LTI system with impulse response h(t)
R∞ R∞
y (t) = h(t) ? e st = −∞ h(τ )e s(t−τ ) dτ = e st −∞ h(τ )e s(−τ ) dτ
R∞
The last term is the Laplace transform H(s) = −∞ h(τ )e s(−τ ) dτ . This is valid for all values of s for which
the integral converges
The output for an input e st is y (t) = H(s) · e st
The input and output are of the same form except for change in magnitude and phase59
e st is an eigen vector of LTI system, which for different values of s forms a class of input test vectors forming
an orthogonal set required to completely define the system in the s-domain
Differentiation in time domain translates to ”s” in Laplace domain. So N th order differential equation becomes N th
order polynomial in ”s” which easy to solve. Integration is mapped to 1s which corresponds to a system with pole at
the origin

58
The exponential is an everlasting one, not the causal signal
59
Note that H(s) for a constant s is a complex number
61/67
Closed loop frequency response
Small-signal stability has always been associated with Phase margin and Gain margin
Target is to always have acceptable transient response
It is to have all closed-loop poles (Roots of 1 + G (s)H(s) = 0) on the LHP of the s-plane
Root-locus or all time-domain techniques are difficult to operate with in circuit design60
Phase margin and gain margin are obtained by plotting the magnitude and phase response of the open
loop-gain(G (s)H(s))
They are favored because they are good metrics of relative stability
They cannot be trusted completely in cases of non-monotonic phase response (dominant zero, systems with
multiple gain/phase crossovers)
A transient response truly brings out the underlying dampness (or lack of it) of the loop and it is easily measurable
in lab. But it may be too costly during design
G (s)
Closed-loop frequency response ( 1+G (s)H(s) ) is a good indicator of the loop quality factor and the peaking can be
used to estimate the stability of the system
Systems with an observable zero in the forward path would create overshoots which are not accounted for in
phase margin
An over damped system would not exhibit any peaking while a well compensated one would show less than 3dB of
magnitude peaking.
60
They either require knowledge about all poles and their dependencies or give little information on what caused the closed-loop pole locations
62/67
Closed-loop peaking Vs Phase margin
7.5
CL_peaking vs PM

7.0

6.5

6.0 5.99415

5.5

5.0

4.5

4.0

3.5

3.0

2.5
2.34745
2.0

1.5

1.0

0.5

0.0

-0.5 29.0256Deg 45.0Deg

24.0 26.0 28.0 30.0 32.0 34.0 36.0 38.0 40.0 42.0 44.0 46.0 48.0 50.0 52.0 54.0 56.0 58.0 60.0 62.0 64.0 66.0 68.0 70.0 72.0 74.0
Deg (Deg)

The closed-loop peaking is plotted against Phase margin for a two-pole (with no zeros)
−( q π )
p 4M 2 −1
% Overshoot for step input= e ∗ 100, where Mp is the peaking observed in the magnitude response
A system with 45° phase margin exhibits 27% overshoot (with a peaking of 2.34dB) whereas one with 30° phase margin shows 44% overshoot (with a
peaking of 6dB)
For accurate systems61 , 60° phase margin with 0.3dB peaking is acceptable, whereas 30◦ with 6dB peaking is fine in a LDO. Generally 50◦ and above is
expected
61
For example, an amplifier serving a 12-bit ADC
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Working with dB20 scale
Analog design deals with huge range of numbers: linear scale struggles
Logarithm function compresses the scale. dB20a is defined as 20log10 (N) where N is
the number under consideration
N dB20
Strictly speaking dB20 is defined for ratiosb (No unit) like voltage gains, impedance 0.1 -20
ratios, Noise figure, reflection coefficient etc. But we often use it for transfer 0.5 -6
functions with units casually too (Change in current for a change in supply voltage √1 -3
which has units of 0, Impedance (W) etc)
(2)
1 0 dB20 N
p
(2) 3 0 1
Multiplication and division in linear scale correspond to addition and subtraction in 2 6 1 1.12
the dB20 scale. This makes it quite attractive to work with dB20 3 9.54 2 1.26
√ 4 12 3 1.41
Remember the conversion for key numbers (2, 2, 10, etc) and apply it to obtain 5 14 4 1.58
others. Try to verify the conversion by performing simple arithmetic: 5 is 6 15.56 5 1.78
10 6 2
2
= dB20(10) − dB20(20) = 20 − 6 = 14dB, 400 = 100 × 4 = 40 + 12 = 52dB 7 16.9
8 18.06 8 2.51
One decade is a ratio of 10. If f1 = 10, f2 = 1 and f3 = 100, f1 is higher than f2 by 9 19.08 10 3.16
one decade and lower than f2 by one decadec 10 20 20 10
20 26
An expression that is directly proportional (∝ N)has +20dB/decade slope and one 25 28
that is inversely proportional ∝ N1 displays −20dB/decade slope in the dB scale 50 34
100 40
a
Called so due to the function name in Cadence environment. In short it is referred as dB scale
b
In the RF domain, dBm, dBc, dBi are used they are relative to 1mW, Carrier power, Isotropic antenna, so they are ratios
c
Similarly an octave is a ratio of 2
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dB20 Vs linear scale

55
50
45
40
35
30
Mag (dB)

25
20
15
10
5
0 dB20
−5 N

−10
−4−2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54
Frequency (Hz)

The number in linear scale is the x-axis and the dB20 value is y-axis. For reference, the number in linear scale is
shown dotted
It can be noted that the dB20 scale meets the linear scale at 1 and at 29.4(≈ 30)
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Second order filter - Frequency responses
Low-pass, high-pass, band-pass, band-stop and all-pass responses could be realized in second order using the same
poles(denominator polynomial)
Poles with ζ of 0.707 (Butterworth response) are used. Find the zero locations of each filter.

Bode Diagram
0
lp
hp
-10 bp
bs
ap
Magnitude (dB)

-20

-30

-40

-50

-60
360
lp
hp
270 bp
bs
180 ap
Phase (deg)

90

-90

-180
104 105 106 107 108
Frequency (Hz) 66/67
Second order filter - step responses
Low-pass, high-pass, band-pass, band-stop and all-pass responses could be realized in second order using the same
poles(denominator polynomial)
Poles with ζ of 0.707 (Butterworth response) are used.
Why do you think the all-pass filter behaves in the way shown?

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