Digital Electronics Assignment | BSc (H) Electronics — II Semester Page 1

DEPARTMENT OF ELECTRONICS
BSc (H) Electronics — II Semester

DIGITAL ELECTRONICS
Assignment

Maximum Marks 20
Last Date of 20 April 2026
Submission
Digital Electronics Assignment | BSc (H) Electronics — II Semester Page 2

Q1(a). Number System Conversion: (123.8)₁₀

Step 1 — Decimal to Binary (123.8)₁₀ → (?)₂

Integer Part (123): Repeated Division by 2

123 ÷ 2 = 61 remainder 1 ← LSB

61 ÷ 2 = 30 remainder 1
30 ÷ 2 = 15 remainder 0
15 ÷ 2 = 7 remainder 1
7 ÷ 2 = 3 remainder 1
3 ÷ 2 = 1 remainder 1
1 ÷ 2 = 0 remainder 1 ← MSB

Integer Part = 1111011

Fractional Part (0.8): Repeated Multiplication by 2

0.8 × 2 = 1.6 → integer part = 1 ← MSB

0.6 × 2 = 1.2 → integer part = 1
0.2 × 2 = 0.4 → integer part = 0
0.4 × 2 = 0.8 → integer part = 0
0.8 × 2 = 1.6 → integer part = 1 (repeats...)

Fractional Part ≈ .1100 (4 places)

(123.8)₁₀ = (1111011.1100)₂

Step 2 — Binary to Octal

Group binary digits in sets of 3 from the decimal point:

Integer: 001 111 011 (pad left with zeros)

1 7 3

Fraction: 110 0 (pad right with zeros)

6 (0)

Result: (173.6)₈

(123.8)₁₀ = (173.6)₈

Step 3 — Binary to Hexadecimal

Digital Electronics Assignment | BSc (H) Electronics — II Semester Page 3

Group binary digits in sets of 4 from the decimal point:

Integer: 0111 1011 (pad left with zeros)

7 B

Fraction: 1100
C

Result: (7B.C)₁₆

(123.8)₁₀ = (7B.C)₁₆

Summary Table
Decimal Binary Octal Hexadecimal
(123.8)₁₀ (1111011.1100)₂ (173.6)₈ (7B.C)₁₆

Q1(b). Definitions

1. Fan-in and Fan-out

Fan-In The maximum number of inputs that a logic gate can accept
simultaneously without causing degradation in output voltage
levels. A gate with higher fan-in can be connected to more
input lines. Typical TTL gates have fan-in of 1 to 8.

Fan-Out The maximum number of standard logic gate inputs that can
be driven by the output of a single logic gate without
exceeding its drive capability. It is determined by the ratio of
output current to input current. Typical TTL fan-out = 10;
CMOS fan-out = 50+.

Fan-Out Illustration:

┌─────┐
│ │──── Gate Input 1
Source ────▷│GATE │──── Gate Input 2
│ │──── Gate Input 3
└─────┘──── Gate Input 4
... up to N inputs (Fan-out = N)
Digital Electronics Assignment | BSc (H) Electronics — II Semester Page 4

2. Speed–Power Product (SPP)

The Speed–Power Product is a figure of merit used to compare logic families. It is defined as:

SPP = Propagation Delay (tpd) × Power Dissipation (Pd)

Units: picoseconds × milliwatts = picojoules (pJ)

Lower SPP → Better Performance

Example Values:
┌─────────────────┬──────────────┬────────────┬─────────┐
│ Logic Family │ Delay (ns) │ Power(mW) │ SPP(pJ) │
├─────────────────┼──────────────┼────────────┼─────────┤
│ Standard TTL │ 10 │ 10 │ 100 │
│ Low-Power TTL │ 33 │ 1 │ 33 │
│ ECL │ 1-2 │ 25 │ 25 │
│ CMOS (5V) │ 50 │ 0.001 │ 0.05 │
└─────────────────┴──────────────┴────────────┴─────────┘
Digital Electronics Assignment | BSc (H) Electronics — II Semester Page 5

Q2. Full Adder Implementation Using PLA

Logic Functions of Full Adder

A Full Adder has three inputs: A, B, Cin (carry-in), and two outputs: Sum (S) and Carry-out
(Cout).

Sum (S) = A ⊕ B ⊕ Cin

Carry (Cout) = AB + BCin + ACin

Truth Table
A B Cin Sum (S) Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Sum-of-Products (SOP) Expressions

S = Σm(1, 2, 4, 7) = A'B'Cin + A'BCin' + AB'Cin' + ABCin
Cout = Σm(3, 5, 6, 7) = A'BCin + AB'Cin + ABCin' + ABCin
(simplified) = AB + BCin + ACin

PLA Structure and Logic Diagram

A PLA (Programmable Logic Array) consists of a programmable AND plane followed by a
programmable OR plane. Connections marked with '×' are programmed.

INPUTS: A A' B B' Cin Cin'

| | | | | |
─────────────────────────────────────────────
AND PLANE (Product Terms — 8 rows):

P1: A'B'Cin ── × × × ×
P2: A'BCin' ── × × × ×
Digital Electronics Assignment | BSc (H) Electronics — II Semester Page 6

P3: AB'Cin' ── × × × × ×
P4: ABCin ── × × × ×
P5: A'BCin ── × × ×
P6: AB'Cin ── × × ×
P7: ABCin' ── × × ×
(P4 is shared between S and Cout)

─────────────────────────────────────────────
OR PLANE (Sum Terms):

S Cout
P1: ×
P2: ×
P3: ×
P4: × ×
P5: ×
P6: ×
P7: ×

OUTPUTS: S Cout

FULL PLA SCHEMATIC (Conceptual):

A ──┬──────────────────────────────────── AND Plane ──┐

A' ──┤ │
B ──┤ (Programmable connections form all required │── OR
──▷ S
B' ──┤ product terms P1..P7) │
Cin ──┤ │── OR
──▷ Cout
Cin'──┘──────────────────────────────────────────────────┘
Digital Electronics Assignment | BSc (H) Electronics — II Semester Page 7

Q3. 4-Bit Serial-In Serial-Out (SISO) Shift Register

Introduction
A Serial-In Serial-Out (SISO) shift register accepts data bit-by-bit at its serial input and shifts
it through each stage, producing the output bit-by-bit from the last stage, one clock pulse at a
time. A 4-bit SISO register consists of four D-type flip-flops connected in cascade.

Operation
On each rising edge of the clock:
• Each flip-flop captures the output of the previous flip-flop.
• The input bit enters FF0 (first flip-flop).
• After 4 clock pulses, all 4 bits have passed through all stages.
• Data appears at the output of FF3 (last flip-flop) after 4 clock cycles.

Logic Diagram — 4-Bit SISO Shift Register

Serial ──────┐
Serial
Input │
Output
▼ │
┌─────────┐ ┌─────────┐ ┌─────────┐
┌─────────┐
│ D Q ├───▷│ D Q ├───▷│ D Q ├───▷│ D Q
├──▷ Qout
│ FF-0 │ │ FF-1 │ │ FF-2 │ │ FF-3
│
│ Q̄ │ │ Q̄ │ │ Q̄ │ │ Q̄
│
└────▲────┘ └────▲────┘ └────▲────┘
└────▲────┘
│ │ │ │
CLK ─────────┴──────────────┴──────────────┴──────────────┘
(Common Clock to all Flip-Flops)

Timing / State Table (Input: 1011)

Clock Serial In FF-0 (Q0) FF-1 (Q1) FF-2 (Q2) FF-3 (Q3)
Pulse
Initial — 0 0 0 0
1 1 1 0 0 0
2 0 0 1 0 0
Digital Electronics Assignment | BSc (H) Electronics — II Semester Page 8

3 1 1 0 1 0
4 1 1 1 0 1 ← Output

Key Characteristics:
• Propagation delay: 4 clock cycles for 4-bit data
• Operates synchronously — all FFs respond to the same clock edge
• Useful for serial data transmission and time delay circuits
Digital Electronics Assignment | BSc (H) Electronics — II Semester Page 9

Q4. Asynchronous Inputs: PRESET and CLEAR in Flip-Flops

Definition
Asynchronous inputs are control inputs that can override the normal clocked operation of a
flip-flop at any time, regardless of the clock signal. The two most common asynchronous
inputs are PRESET (PRE) and CLEAR (CLR).

PRESET (PRE) / SET

When activated (usually active LOW), PRESET forces the output Q to logic 1 (HIGH)
immediately, without waiting for a clock edge. It is also called direct set or asynchronous set.

CLEAR (CLR) / RESET

When activated (usually active LOW), CLEAR forces the output Q to logic 0 (LOW)
immediately, without waiting for a clock edge. It is also called direct reset or asynchronous
reset.

JK Flip-Flop with Asynchronous Inputs — Logic Symbol

PRE (Active LOW)

│
▼
┌───o───────────────┐
│ PRE │
J ────▷│ J Q ───▷│──── Q
│ │
CLK ───▷│ > Q̄ ───▷│──── Q̄
│ │
K ────▷│ K │
│ CLR │
└───o───────────────┘
▲
│
CLR (Active LOW)

Truth Table for Asynchronous Inputs

PRE CLR CLK J Q Condition
0 1 × × 1 Preset
(Set)
1 0 × × 0 Clear
(Reset)
Digital Electronics Assignment | BSc (H) Electronics — II Semester Page 10

0 0 × × 1* Invalid/
Forbidden
1 1 ↑ J/K Normal Clocked
Operation

Notes:
• × = Don't care; ↑ = Rising clock edge; * = Both Q and Q̄ go HIGH (invalid state)
• PRE and CLR are independent of the clock and take immediate effect.
• In practice, both PRE and CLR active simultaneously (0,0) is an invalid state and must be
avoided.
• They are extremely useful for initializing flip-flops to a known state at power-up or reset.
Digital Electronics Assignment | BSc (H) Electronics — II Semester Page 11

Q5. D/A and A/D Converters

(i) Binary-Weighted Resistor DAC

A Binary-Weighted DAC uses a set of resistors with values proportional to the binary weights
of each bit (R, R/2, R/4, R/8…). An op-amp summing amplifier produces an output voltage
proportional to the digital input value.

Circuit Diagram (4-bit Binary-Weighted DAC):

Rf = R
┌────┤///├────┐
│ │
Bit D3 (MSB) ─────┤ │
R (1kΩ) ─┤ (−) │
│ 741 ├───▷ Vout
Bit D2 ─────┤ Op-Amp │
2R (2kΩ) ─┤ (+) │
│ │
Bit D1 ─────┤ GND │
4R (4kΩ) ─┤ │
│ │
Bit D0 (LSB) ─────┘
8R (8kΩ)

Vout = −Rf × [D3/R + D2/2R + D1/4R + D0/8R]

= −Vref × [D3 × 1/2 + D2 × 1/4 + D1 × 1/8 + D0 × 1/16]

Advantages: Simple design, easy to understand.

Disadvantages: Requires very precise and widely varying resistor values; difficult to
fabricate accurately on IC.

(ii) R-2R Ladder DAC

The R-2R Ladder DAC overcomes the disadvantage of binary-weighted DAC by using only
two resistor values: R and 2R. It uses a ladder network that provides binary-weighted
currents to an op-amp summing junction.

Circuit Diagram (4-bit R-2R Ladder DAC):

D3(MSB) D2 D1 D0(LSB)
│ │ │ │
2R 2R 2R 2R
│ │ │ │
├────────┤ ├────────┤
│ R │ R │ R │
2R ───── ───── ───── 2R ─── GND
│ │
Digital Electronics Assignment | BSc (H) Electronics — II Semester Page 12

Node A Node B Node C Node D│

│ │
└─────── To Op-Amp (−)──────┘ Rf
(+) ──▷ GND ┌───///──▷ Vout
741 │

Equivalent at each node: Thevenin resistance = R

Each bit contributes: Vout contribution = Vref × Dn / 2^(4-n)

Advantages: Only two resistor values needed; better accuracy; easily integrated on IC.
Disadvantages: Requires more resistors than binary-weighted; switch resistance affects
accuracy.

(iii) Successive Approximation ADC (SAR ADC)

The Successive Approximation ADC converts an analog input to a digital output by
performing a binary search through all possible quantization levels. It is the most widely used
ADC due to its high speed and good resolution trade-off.

Block Diagram:

N-bit
Analog ┌──────────────┐ Digital Output
Input (Vin)──▷ │ │
│ Comparator ├──────────┤
┌────▷ │ │
│ └──────────────┘ │
│ ▼
│ ┌─────────────────┐
│ │ Successive │
│ │ Approximation │◁─── Clock
│ │ Register (SAR) │
│ └────────┬────────┘
│ │
│ ┌────────▼────────┐
│ │ DAC │
│ │ (N-bit) │
│ └────────┬────────┘
│ │
└─────────────────────────────┘
VDAC (feedback)

Working Principle — Step by Step:

Step 1: SAR sets MSB = 1, all other bits = 0 → DAC output =

Vref/2
Comparator checks: Is Vin > Vref/2?
→ YES: Keep MSB = 1 | NO: Set MSB = 0

Step 2: SAR sets next bit = 1 → new DAC output

Digital Electronics Assignment | BSc (H) Electronics — II Semester Page 13

Comparator checks again → bit is kept or cleared

... This continues for all N bits ...

Step N: After N clock cycles, SAR holds the N-bit digital

approximation of the analog input.

Example (4-bit ADC, Vref=16V, Vin=10.5V):

┌──────┬──────┬────────────────────┬────────────────┐
│ Step │ Bit │ VDAC (V) │ Decision │
├──────┼──────┼────────────────────┼────────────────┤
│ 1 │ D3=1 │ 8.0 (16/2) │ 10.5>8 → Keep │
│ 2 │ D2=1 │ 12.0 (8+4) │ 10.5<12→ Clear │
│ 3 │ D1=1 │ 10.0 (8+2) │ 10.5>10→ Keep │
│ 4 │ D0=1 │ 11.0 (8+2+1) │ 10.5<11→ Clear │
└──────┴──────┴────────────────────┴────────────────┘
Result: D3D2D1D0 = 1010 = (10)₁₀ ≈ 10.5V ✓

Key Specifications:
Parameter Value/Description
Conversion Time N clock cycles for N-bit resolution
Resolution Vref / 2ᴺ (voltage per LSB)
Speed Fast — typically 1–100 µs
Applications Data acquisition, microcontrollers, instrumentation