Review of MOS device and problems

with classical scaling

Deleep R. Nair

Department of Electrical Engg, IIT Madras

[Link]
 2
Course content
• Review of MOS transistor and problems with traditional (Dennard) scaling
• Review of MOS transistor technology
• Basic Quantum mechanics and Silicon band structure
• Mobility enhancement techniques (introduced in high volume
manufacturing in 2003)
• High k gate dielectrics and metal gates (introduced in 2007)
• FinFETs (introduced in 2012)
• High mobility channel materials (introduced in 2011)
• Nanosheet transistors (introduced in 2024 Samsung Galaxy Watch7)
• Layout dependent effects (became a serious issue since late 2000s)
 3
MOS Field Effect Transistor
• The MOSFET is a MOS capacitor
with Source/Drain terminals
• How does it work?
– Gate voltage (VGS) controls
mobile charge under gate
– Source-drain voltage (VDS) sweeps
this charge creating current (ID)
• Desired characteristics
- High “On” current (300-1300 μA/μm)
- Low “Off” current (10 pA-100 nA/μm)
 4
MOS Field Effect Transistor (1980s)

Single well CMOS process (1-2 μm)

 5
MOS Field Effect Transistor (1990s-2003)

Twin-well CMOS process (< 1 μm)

 6
Modern day MOSFET (two variants)
Fully depleted Silicon on Insulator (FDSOI)
ST/Samsung/GF/NXP

TSMC 2024 revenue

FinFET (16-3nm)
Intel/Samsung/GF/TSMC
 7

FinFET scaling is over?

Around the
5-7nm node,
SRAM scaling
seemed to
flatten out

[Link]
 8
Most recent form of MOSFET- Nanosheet transistor

Samsung VLSI 2004 (Multi-bridge channel FETs)

[Link]
 9
Future MOSFET- Stacked Nanosheet transistor or CFET

[Link]
cked-nanosheet-transistors-could-be-the-next-step-in-moores-law
 10
MOSFET Scaling
• MOSFETs have been steadily miniaturized over time
‒ 1970s: Gate length ~ 10 µm
‒ Today: Gate length ~ 15 nm
~ 15 generations of MOSFET with minor/major modifications over previous
generations
• Why they look different ? - Process and Device changes are required to improve
(or not worsen) performance /power /reliability /manufacturability of the devices
from one generation to other
• Reasons:
‒ Improved circuit operating speed (~30% every gen)
‒ Increased device density --> lower cost per function (~50% area reduction)
‒ More functionality in device/gadget
Herbert Kroemer in his Nobel prize lecture 11

[Link]
 12
MOSFET 2-D band diagram

Gate voltage reduces the barrier from source/drain to channel enabling

carrier injection
Qualitative operation of ideal MOSFET 13

The relative height of the two reservoirs of water corresponds to the drain-to-source
voltage. The relative height of the barrier above the water level of the source
corresponds to the gate to source voltage in excess of threshold. At a value of VGS =
VT, the top of the barrier is leveled with the water surface.
Reservoir analogy of an ideal MOSFET 14

In the cut-off regime, the barrier is above the water level on the source and drain and
water does not flow. In the triode or linear regime, the barrier is below the water level
of both the source and drain. Water flows from source to drain. In the saturation
regime, the barrier is below the water level of the source but above that of the drain.
Water flows from source to drain, but the water flow rate is independent of the
relative levels of the source and drain.
 15
Ideal MOSFET I-V Characteristics

Enhancement-Mode
N-channel MOSFET
 16
Output characteristics - Comparing BJT & MOSFET
Modulate injection
of carriers to base or
channel

Collect the carriers

at a reverse biased
junction

BJT MOSFET Transport is diffusion

in base and drift in
channel
 17
MOSFET Scaling
• Advantages over BJT:
‒ Critical dimension in lateral dimension compared vertical in BJT. Possible to
make transistors with different gate lengths on the same wafer.
‒ No bipolar logic family with very low standby power dissipation as CMOS.
Limits no: of transistors in a chip.
‒ MOS is a symmetrical device compared to BJT. More flexibility in design.
What does scaling means? 18
Drain Source
Reduce
contacted
gate pitch
and metal
wiring pitch

Contacted Gate pitch

 19
Bad scaling

Robert Pierret, Semiconductor Device Fundamentals, 2005

 20
Threshold voltage TSMC N2 from IEDM 2024

VT is usually measured in industry using constant

current method.

Foundry offers 4-6 different VT flavors for

power-performance trade-off
 21

Short Channel Effect (SCE)

“VT roll-off”

•|VT| decreases with L

‒Effect is exacerbated by
high values of |VDS|

•This effect is undesirable (i.e. we want to minimize it!) because

circuit designers would like VT to be invariant with transistor
dimensions and bias condition
 22
Qualitative Explanation of VT roll-off
•Before an inversion layer forms beneath the gate, the surface of
the Si underneath the gate must be depleted (to a depth WT)
•The source & drain pn junctions assist in depleting the Si
underneath the gate
‒ Less gate charge is required to invert the semiconductor surface (i.e.
|VT| decreases)

Long L: S D
Depletion charge
supported by S/D
Short L: S D

Depletion charge
supported by S/D
 23
Drain Induced Barrier Lowering (DIBL)
• As the source and drain get closer, they become electrostatically coupled, so
that the drain bias can affect the potential barrier to carrier diffusion at the
source junction
VT decreases (i.e. OFF state leakage current increases)

VT becomes a f(VDS) for short

channel devices.
 24

VT is usually measured in industry

using constant current method

DIBL = (VT,lin-VT,sat)/(VDD-VDS,lin)

Solution: Increase average channel doping

and reduce gate oxide thickness
 25
Punch-through
• A large drain bias can cause the drain-junction depletion region to merge
with the source-junction depletion region, forming a sub-surface path for
current conduction.
IDsat increases rapidly with VDS
• This can be mitigated by doping the semiconductor more heavily in the
sub-surface region, i.e. using a “anti-punch through” implant.
 26
MOSFET scaling (Dennard 1972)

The phenomenon of ‘yes, there is free lunch’ comes ever so rarely in engineering. The ability to build more transistors in a chip without having to worry
about cooling accelerated the availability of compute power for many decades, and is solely responsible for the rapid development of chip technology in
the past century.

An added benefit comes from the drop in delay time by a factor of 1/k which means that not only were we able to cram in more transistors with no
thermal penalty, but those transistors switched faster too, enabling higher clock speeds. This really is an instance of ‘having your cake and eating it too.’

[Link]
[Link]
 27
Scaling Rule of Thumb
• Lmin minimum gate length for “long channel” behavior (Empirical relation
based on simulation)

tox gate oxide thickness in Å

Lmin, Ws, WD, rj(S/D junction depth) in microns
• A FET is whether electrically long or short really depends upon the process
conditions rather than strictly only on the gate length.
• S/D junctions, depletion width (doping), oxide thickness must scale with
minimum gate length
tox
rj L rj
Ws WD
 28
Shallow Source and Drain (S/D)
• To minimize the short channel effect and DIBL, we want shallow (small rj)
S/D regions − but the parasitic resistance of these regions increases
when rj is reduced.

where r = resistivity of the S/D regions

• These regions need to be heavily doped (and better activated) to make
the increase in parasitic resistance small.

• One still needs heavily doped deep

source/drain to make contacts and
reduce the series resistance
 29
Hot carrier effects High electric field
near drain junction
increases carrier energy
and some of them can
get trapped inside oxide
and/or create new traps.

Increases VT, reduces Id

affecting long term
reliability
High energy carriers also
create EHPs through
impact ionization. The
generated holes flow to
substrate (Isub)
 30
Plain Vanilla MOSFET structure (before 2003)
• Halo/pocket implants to reduce encroachment of drain depletion region
and hence DIBL.
• It is created using tilted implantation along with S/D extension implants
• Spacer defines where to start the deep source/drain
 31
Sub-Threshold Current
• For |VG| < |VT|, MOSFET current flow is limited by carrier
diffusion into the channel region.
• The electric potential in the channel region varies linearly with
VG, according to the capacitive voltage divider formula:

• As the potential barrier to diffusion increases linearly with

decreasing VG, the diffusion current decreases exponentially:
 32
Sub-Threshold Swing, S

Inverse slope is subthreshold

swing, S [mV/decade]

NMOS Energy Band Profile

n(E) ∝
exp(-E/kT)
Typical values of S for planar MOSFET –
increasing

80-90 mV/decade
Source increasing
Theoretical min at 300 K - ~60 mV/decade
E

VGS Drain

distance
How to reduce S ?
 33
Id-Vg (linear and saturation mode)

Ion (N/P) = 500/300 μA/μm Ion (N/P) = 1620/1370 μA/μm

Ioff=20 pA/μm Ioff=100 nA/μm
 34
Gate Induced Drain Leakage (GIDL)

Band to band tunneling in

gate/drain overlap region when
VGD is –ve

This limits the off current of a

FET with high VT. In such
devices, off current (<
100pA/μm) could be dominated
by GIDL compared to sub
threshold leakage current
 35
GIDL in a PFET

GIDL makes IS ≠ ID
One mayn’t see this in a FET with low VT, which has Ioff > 10 nA/μm
V. Tiwari et al, IEEE Trans. Electron Devices, vol. 61, no. 5, pp.1270-1277, May 2014
 36
Gate Leakage current due to tunneling

For 2Ǻ reduction in
gate oxide thickness,
current increases by
10X

Tunneling a) to/from channel

and b) through overlap region
 37
CMOS Inverter
Identify leakage components causing static power dissipation in a CMOS inverter

1 0
0
1

VDD
0V

IJ
 38
The power problem in classical scaling

1. Gate length scaling increases source-drain leakage exponentially

☹ Prevents scaling of threshold voltage 🡪 prevents scaling of supply voltage.
2. Gate dielectric scaling increase gate leakage exponentially
3. Industry diverged into High Performance and Low Power at 90nm
☹ Prevents scaling of Tox 🡪 degrades channel control 🡪 increases sub-Vt leakage
 39
End of clock rate wars and rise of multi-core designs

[Link]
 40
Saturation of IDsat

C. Choi Ph.D thesis, Stanford

Variations Increase in drive current

in Lg and Vt @ constant Ioff is needed.
The scaling scenario 41

Materials: µ, Rs
Ioff
(log
scale)
Performance
improvement

Ion
Conventional
scaling
Igate

Materials ε

To Further scaling is possible by adding new

Classical scaling stopped
x at 130nm (circa 2001) performance enhancing elements
Transistor performance comparison across nodes/nodelet 42

Intel 45nm-32nm comparison (20-30%

improvement) IEDM 2009

Intel 22nm-22FL comparison IEDM 2011/2018

 43
What does node name means ?
Pitch Intel Intel Intel
22nm 14nm 10nm
Gate 90 nm 70 nm 54 nm
M1 80 nm 52 nm 36 nm
Fin 60 nm 42 nm 34 nm

Node M1 half pitch

Lgate
IEEE Spectrum Nov 2013, Aug 2020

Node name doesn’t represent any feature size on the wafer or in the design rules. There are
also nodelets or half nodes !!
 44
What does nodelet means ?

TSMC 3nm IEDM 2022

 45
Pitch scaling @ higher FLOPS/Watt
• At a very high level, desirable product features are
○ Performance per power (FLOPS/Watt)
○ More functionality per area at the same cost
• The major factor which enabled this was continuous
IEDM 2009
realization of smaller MOSFETs with larger drive currents

TSMC @ IEDM 2024

[Link]
[Link]
Apple processors

[Link]
Why gate length scaling is still important?
• Contacted Gate pitch=Gate length
+2*(Poly-Contact spacing) + Contact width

• Before 90nm node, all three terms in RHS

used to scale more or less equally to reduce
the gate pitch by ~0.7x every node
• However, gate length scaling has slowed down after 90nm node resulting contact and
poly-contact spacing should scale more to accommodate a longer than desired gate.
This results in higher gate & gate-contact capacitance/resistance, poor yield due to
poly/contact shorts etc
• Single gate is not able to control the channel below a physical gate length of 30 nm
(very large IOFF, DIBL, subthreshold slope etc)
[Link]
 How does adding another gate help?
IEDM 2012

Double gate FETs have lower

DIBL and SS compared to
single gate FETs for the same
The performance
gate length. This means it has
improvement in speed
higher ION for the same IOFF or
increases at lower
lower IOFF for the same ION
voltages
[Link]
[Link]
How does a double gate FET looks like?

Single gate on the top of channel One gate/channel is over front face of the fin, 2nd is
over the back face of the fin and a 3rd (smaller than
1st and 2nd) on top of the Fin.

FinFET is the only manufacturable double gate solution. Gate/spacer is deposited & etched
on all three sides of the fin in a single step. This ensures LGate and Cov is same on all sides.
49
How is FinFET different from a planar FET?
• Effective width of a FET with one fin=2HFIN + WFIN
• For more width, one has to add more fins. Allowable
FET width comes in discrete numbers compared to
continuous in planar FETs
• WFIN should be less than 0.6LG to have lower DIBL and
SS compared to planar gate.
• Realizing fins smaller than gate needs more complex
fabrication flow & double/quad patterning
• Front & Back surface of the fin has a different crystal
orientation compared to top or that of the wafer
• Very little doping in the channel. Different threshold
voltages are realized using gate work function
engineering
What comes after FinFET?
• FinFETs have been in production
since 2011. TSMC 3nm node FET IEDM 2022

has a gate length > 10 nm

• Needs nanosheets of Si with gate
wrapped around on all sides for
gate length scaling below 10 nm
• Nanosheets have also better
current/footprint than nano wires.
Nanosheet width (Wsheet) is not quantized.
• More complex fabrication than FinFET

• 1st product - Samsung Exynos W1000

inside Galaxy Watch7 (2024) [Link]
[Link]