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Cse260 Lab3 Task

The document outlines Experiment #3 for CSE 260: Digital Logic Design, focusing on the design and implementation of an even parity generator and checker using XOR gates (IC-7486). It includes objectives, required components, circuit diagrams, and procedures for constructing the circuits on a breadboard. Additionally, it provides truth tables for both the parity bit generator and checker to record results.

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4 views2 pages

Cse260 Lab3 Task

The document outlines Experiment #3 for CSE 260: Digital Logic Design, focusing on the design and implementation of an even parity generator and checker using XOR gates (IC-7486). It includes objectives, required components, circuit diagrams, and procedures for constructing the circuits on a breadboard. Additionally, it provides truth tables for both the parity bit generator and checker to record results.

Uploaded by

ribat.shama03
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Department of Computer Science and Engineering

BRAC University
CSE 260: Digital Logic Design

Experiment # 3: Parity Bit Checker and Generator


Objective:
■ To design and implement an even parity Generator and even parity checker
using XOR gates. (IC-7486).

Required Components:
1. IC 7486 × 1

Diagrams:
Building an even parity generator using XOR Gates for 4-bit Data:

Building an even parity checker using XOR Gates for 4-bit Data:

Procedure:
■ Construct the Circuits of both the parity bit generator and checker on the
breadboard.
■ Remember that each IC’s pin 14 is connected to the “+5V” position of the
DC Power Supply of AT-700, and pin 7 is connected to the “GND”
position.
■ Connect the inputs to the Data switches and outputs to any position of the
LED Display.

Result:
Complete both of the following truth tables.

Truth Table for Parity Bit Generator:


Data
Parity
D3 D2 D1 D0

a. 1 0 0 1

b. 0 0 0 1

c. 1 1 1 1

d. 0 0 0 0

Truth Table for Parity Bit Checker:


Data
Error
Parity D3 D2 D1 D0

a. 1 1 0 0 1

b. 0 0 0 0 1

c. 0 1 1 1 1

d. 1 0 0 0 0

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