Module 4

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 Module 4
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INTRODUCTION

•The components of a computer system communicate with each other through an

interconnection network
•The interconnection network consists of circuits needed to transfer information between
the processor, the memory unit, and a number of I/O devices
Input / Output (I/O)
1. External Devices
I/O Module
2. System Bus
3. I/O Module
Classification of External Devices
2. Machine-readable devices
External Device
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Keyboard/Monitor
Keyboard/Monitor
Keyboard/Monitor interaction
I/O MODULES
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Steps of data transfer from an external device to the processor
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I/O Module Structure
I/O Module Structure
I/O Module Structure
I/O Module Structure
Techniques for I/O operations
PROGRAMMED I/O
PROGRAMMED I/O
INTERRUPT-DRIVEN I/O
INTERRUPT-DRIVEN I/O
Direct Memory Access
Direct Memory Access
Overview of Programmed I/O
I/O Commands-issued by the processor to the I/O module
I/O Commands-issued by the processor to the I/O module
.
I/O Instructions- executed by the processor
With programmed I/O, there is a close correspondence between the I/o-related
Instructions that the processor fetches from memory and the I/O commands that
the Processor issues to an I/O module to execute the instructions.
• That is, the instructions are easily mapped into I/O commands, and there is often
a simple one-to-one Relationship.
• The form of the instruction depends on the way in which external devices are
addressed.
• Each device is given a unique identifier or address.
• When the processor Issues an I/O command, the command contains the address
of the desired device.
• Thus, each i/o module must interpret the address lines to determine if the
command is for itself.
I/O Instructions- executed by the processor
• When the processor, main memory, and I/O share a common bus, two modes of
addressing are possible.
1. memory mapped
• With memory-mapped I/O, there is a single address space for memory locations
and I/O devices.
• The processor treats the status and data registers of I/O modules as memory
locations and uses the same machine instructions to access both memory and I/O
devices.
• So, for example, with 10 address lines, a combined total of 2^10 = 1024 memory
locations.
• and I/O addresses can be supported, in any combination.
• With memory-mapped I/O, a single read line and a single write line are needed on
the bus.
I/O Instructions- executed by the processor
2. isolated
• Memory and I/O have separate address spaces.
• The command line specifies whether the address refers to a
memory location or
an I/O device.
• The full range of addresses may be available for both.
• Again, with 10 address lines, the system may now support both
1024 memory
locations and 1024 I/O addresses.
• Because the address space for I/O is isolated from that for
memory,
 Interrupt-Drive I/O overview

• For input, The module receives a READ command from the

processor.
• It reads data from the peripheral device.
• When data is ready in its data register, It sends an interrupt
signal.
• It waits until the processor requests the data.
• It places the data on the data bus.
• It becomes ready for the next I/O operation.
 Interrupt-Drive I/O overview
From the processor’s point of view, the action for input is as follows.
• The processor issues a READ command.
• It then goes off and does something else (e.g., the processor may be working on
several different programs at the same time).
• At the end of each instruction cycle, the processor checks for interrupts .
• When the interrupt from the I/O module occurs, the processor saves the context
(e.g., program counter and processor registers) of the current program and
processes the interrupt.
• In this case, the processor reads the word of data from the I/O module and stores
it in memory.
• It then restores the context of the program it was working on (or some other
program) and resumes execution.
.
Interrupt Processing
The occurrence of an interrupt triggers a number of events both in the processor
hardware and in software.
• When an I/O device completes an I/O operation, the following sequence of
hardware events occurs.
1. The device issues an interrupt signal to the processor.
2. The processor finishes execution of the current instruction before responding
to the interrupt.
3. The processor tests for an interrupt, determines that there is one, and sends an
acknowledgment signal to the device that issued the interrupt. The
acknowledgment allows the device to remove its interrupt signal.
4. The processor now needs to prepare to transfer control to the interrupt routine.
To begin, it needs to save information needed to resume the current program at
the point of interrupt.
Interrupt Processing
(a) the status of the processor, which is contained in a register called the program
status word (PSW)
(b) the location of the next instruction to be executed, which is contained in the
program counter.
These can be pushed onto the system control stack.

5. The processor now loads the program counter with the entry location of the
interrupt-handling program that will respond to this interrupt.
- Once the program counter has been loaded, the processor proceeds to the next
instruction cycle, which begins with an instruction fetch. control is transferred to
the interrupt-handler program.
6. At this point, the program counter and PSW relating to the interrupted program
have been saved on the system stack.
Interrupt Processing
7. The interrupt handler next processes the interrupt. This includes an examination
of status information relating to the I/O operation or other event that caused an
interrupt. It may also involve sending additional commands or acknowledgments to
the I/O device.

8. When interrupt processing is complete, the saved register values are retrieved
from the stack and restored to the registers .

9. The final act is to restore the PSW and program counter values from the stack.
As a result, the next instruction to be executed will be from the previously
interrupted program.
.
Design Issues in Interrupt-Drive I/O
Two design issues arise in implementing interrupt I/O.
1. There will almost invariably be multiple I/O modules, how does the processor
determine which device issued the interrupt?
2. if multiple interrupts have occurred, how does the processor decide which
one to process?
• Let us consider device identification first.
• Four general categories of techniques are in common use:
1. Multiple interrupt lines
2. Software poll
3. Daisy chain (hardware poll, vectored)
4. Bus arbitration (vectored)
Design Issues in Interrupt-Drive I/O
1. Multiple interrupt lines
• The most straightforward approach to the problem is to provide
multiple
interrupt lines between the processor and the I/O modules.
• However, it is impractical to dedicate more than a few bus lines or
processor pins
to interrupt lines.
• Consequently, even if multiple lines are used, it is likely that each line
will have
multiple I/O modules attached to it.
• Thus, one of the other three techniques must be used on each line.
 Design Issues in Interrupt-Drive I/O
2. Software poll
• When the processor detects an interrupt, it branches to an interrupt-service
routine whose job it is to poll each I/O module to determine which module
caused the interrupt.
• The poll could be in the form of a separate command line (e.g., TESTI/O).
• In this case, the processor raises TESTI/O and places the address of a particular
I/O module on the address lines.
• The I/O module responds positively if it sets the interrupt.
• Alternatively, each I/O module could contain an addressable status register.
• The processor then reads the status register of each I/O module to identify the
interrupting module.
• Once the correct module is identified, the processor branches to a device-service
routine specific to that device.
• The disadvantage of the software poll is that it is time consuming
 Design Issues in Interrupt-Drive I/O
3. Daisy chain
• For interrupts, all I/O modules share a common interrupt request line.
• The interrupt acknowledge line is daisy chained through the modules.
• When the processor senses an interrupt, it sends out an interrupt acknowledge.
• This signal propagates through a series of I/O modules until it gets to a
requesting module.
• The requesting module typically responds by placing a word on the data lines.
This word is referred to as a vector and is either the address of the I/O module or
some other unique identifier.
• In either case, the processor uses the vector as a pointer to the appropriate
device-service routine.
• This avoids the need to execute a general interrupt-service routine first. This
technique is called a vectored interrupt.
 Design Issues in Interrupt-Drive I/O
4. Bus arbitration (vectored)
• With bus arbitration, an I/O module must first gain control of
the bus before it can raise the interrupt request line.
• Thus, only one module can raise the line at a time.
• When the processor detects the interrupt, it responds on the
interrupt acknowledge line.
• The requesting module then places its vector on the data
lines.
 Drawbacks of Programmed and Interrupt-Driven I/O

1. The I/O transfer rate is limited by the speed with which the
processor can test and service a device.
2. The processor is tied up in managing an I/O transfer; a
number of instructions must be executed for each I/O transfer.
• When large volumes of data are to be moved, a more
efficient technique is required: direct memory access (DMA).
 DMA Function
DMA involves an additional module on the system bus.
• The DMA module is capable of mimicking the processor and, indeed, of taking
over control of the system from the processor.
• It needs to do this to transfer data to and from memory over the system bus.
• For this purpose, the DMA module must use the bus only when the processor
does not need it (cycle stealing), or it must force the processor to suspend
operation temporarily.
• DMA module in effect steals a bus cycle.
DMA BLOCK DIAGRAM
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 DMA Function
When the processor wishes to read or write a block of data, it issues a command to the
DMA module, by sending to the DMA module the following information:

-Whether a read or write is requested, using the read or write control line between the
processor and the DMA module

-The address of the I/O device involved, communicated on the data lines.

-The starting location in memory to read from or write to, communicated on the data lines
and stored by the DMA module in its address register

-The number of words to be read or written, again communicated via the data

lines and stored in the data count register.

 DMA Function
The processor then continues with other work.

• It has delegated this I/O operation to the DMA module.

• The DMA module transfers the entire block of data, one word at a time, directly

to or from memory, without going through the processor.

• When the transfer is complete, the DMA module sends an interrupt signal to the

processor.

• Thus, the processor is involved only at the beginning and end of the transfer
Direct Memory Access-Configuration
Shared System Bus Configuration

In this setup:
• All modules (Processor, Memory,I/O,DMA)share the same
system bus.
• The DMA module acts like a surrogate processor.
• It uses programmed I/O to transfer data between memory and
the I/O module.
• This configuration, while it may be inexpensive, is clearly
inefficient.
• As with processor controlled programmed I/O, each transfer of a
word consumes two bus cycles.( limited performance)
 Single-bus- integrated DMA-I/O
The number of required bus cycles can be cut substantially by integrating the

DMA and I/O functions.

• There is a path between the DMA module and one or more I/O modules that

does not include the system bus.

-Alternative DMA Configurations

-The DMA logic may actually be a part of an I/O module, or it may be a separate

module that controls one or more I/O modules.

-This concept can be taken one step further by connecting I/O modules to the

DMA module using an I/O bus.

 Alternative DMA Configurations
• This reduces the number of I/O interfaces in the DMA module to one and provides for an
easily expandable configuration.
• In both of these cases , the system bus that the DMA module shares with the processor
and memory is used by the DMA module only to exchange data with memory.
• DMA–I/O communication occurs outside the system bus.
This design improves scalability and reduces system bus traffic.
Embedded I/O
Systems
 Embedded I/O Systems
An Embedded I/O System is an Input/Output system used in embedded systems to
communicate between the microcontroller/microprocessor and external devices.

• It enables the embedded device to receive input from sensors or users and send output
to actuators or display units.
Applications of Embedded I/O Systems

• Automotive systems
• Medical devices
• Smart home systems
• Industrial automation
• Consumer electronics
• IoT devices
 EMBEDDED I/O SYSTEMS
• Embedded systems use a processor to control interactions with the
physical environment.
• They are typically built around microcontroller units (MCUs) which
combine a microprocessor with a set of easy-to-use peripherals such as
general-purpose digital and analog I/O pins, serial ports, timers, etc.
• Microcontrollers are generally inexpensive and are designed to minimize
system cost and size by integrating most of the necessary components onto
a single chip.
• Most are smaller and lighter, consume mill watts of power, and range in
cost from a few dimes up to several dollars.
• Microcontrollers are classified by the size of data that they operate on.
Embedded I/O System Architecture
 RED-V Board

• SparkFun RED-V board is an embedded I/O system.

• It specifically designed as a development board for testing and deploying
applications on a RISC-V microcontroller.
• A low-cost, open-source development board featuring the SiFive Freedom
E310 SoC.
• It uses a familiar Arduino Uno R3 footprint and is ideal for prototyping
open source, royalty-free microcontroller applications.
• It includes a RISC-V microprocessor with a 5-stage pipeline and many I/O
Peripherals.
 RED-V Board
Key Features:
Processor: SiFive Freedom E310 (FE310) SoC with a 32-bit
RV32IMAC RISC-V core.
Speed: Clock speed exceeding 320 MHz.
Form Factor: Arduino Uno R3 footprint (19 digital I/O pins, 9
PWM pins).
Memory/Storage: 16KB instruction cache, 16KB data scratchpad.
Connectivity: USB-C connector for programming/debugging (via
NXP K22 ARM Cortex-M4), and a Qwiic connector for I2C devices.
 Types of Embedded I/O Devices

1. Input Devices
• Used to send data to the embedded system.
• Eg: Sensors (temperature , pressure) Pushbuttons, Keypads ,
Switches ,Camera modules.
2. Output Devices
• Used to receive data from the embedded system.
Examples: LEDs, LCD display, Motors, Buzzers, Relays
 Types of Embedded I/O Devices
3. I/O Interfaces
• I/O Interfaces are the connection mechanisms that allow a processor or microcontroller
(like Arduino) to communicate with external input and output devices.
• They act as a bridge between CPU and external world. Why I/O Interfaces are
Needed?
• Processor understands only digital signals (0s and 1s)
• Many devices give analog or different types of signals
• So, interfaces are required for:
• Signal conversion
• Communication
• Control
-GPIO (General Purpose Input/Output)
-ADC (Analog to Digital Converter)DAC (Digital to Analog Converter)
-Serial Communication Interfaces
 Types of Embedded I/O Devices
4. Communication Interfaces
 GPIO (General Purpose Input/Output)
• General-purpose I/O (GPIO) pins are used to read or write digital
signals. Used for LEDs, switches, etc.
• GPIO pins require memory-mapped I/O registers to read input pin
values, write output pin values, and set the direction of the pin.
• In many embedded systems, the GPIO pins can be shared with one or
more special-purpose peripherals.
• additional configuration registers are necessary to determine whether
the pin is general- or special-purpose.
• Furthermore, the processor may generate interrupts when an event
such as a rising or falling edge occurs on an input pin.
• configuration registers may be used to specify the conditions for an
interrupt.
General-Purpose I/O
 General-Purpose I/O
-Table lists the GPIO registers and their address offsets relative to the GPIO
base address.
• Each GPIO pin is mapped to one bit of the registers.
• Reading from the input_val (input value) register reads the values of the
GPIO pins, and writing to the output_val (output value) register writes to
the GPIO pins.
• Before reading or writing to the pins, the input and output enable registers
(input_en and output_en) must be set to configure the pins as inputs or
outputs and the hardware-driven function enable register (iof_en) must be
cleared to configure the pins as GPIO controlled.
General-Purpose I/O
 Serial I/O
Serial I/O is a method of data transfer where data is sent one bit at a
time over a single communication line (or a small number of lines).
• Instead of sending 8 bits (1 byte) at once (parallel), sends bits
sequentially (one by one).
• Serial I/O is popular, especially when pins are limited, because it uses
few wires and is fast enough for many applications.
• Indeed, it is so popular that many standards for serial I/O have been
established and microcontrollers offer dedicated hardware to easily
send data via these standards.
• The SPI and UART are standard serial interfaces.
• Other common serial standards include inter-integrated circuit
(I2C), universal serial bus (USB), and Ethernet.
Serial Peripheral Interface (SPI)/ Synchronous Serial
 Serial Peripheral Interface (SPI)/ Synchronous Serial
• The controller produces the clock.
• It initiates communication by sending clock pulses on SCK.
• The controller sends data from its SDO pin to the peripheral’s SDI pin
one bit per cycle, starting with the most significant bit.
• The peripheral may simultaneously respond with its SDO pin back to
the controller’s SDI pin.
• Figure shows the SPI waveforms for an 8-bit data transmission.
• Bits change on the falling edge of SCK and are stable to sample on the
rising edge.
• The SPI interface may also send an active-low chip enable to alert the
receiver that data is coming.
Serial Peripheral Interface (SPI)/ Synchronous Serial
 Universal Asynchronous Receiver/Transmitter
(UART)
• A UART is a serial I/O peripheral that communicates between two
systems without sending a clock.
• Instead, the systems must agree in advance about what data rate to
use and must each locally generate their own clocks.
• Hence, the transmission is asynchronous because the clocks are not
synchronized.
• Even though:
• Clocks may have small frequency errors
• Phase relationship is unknown
UART
UART
• The lines idle at a logic “1” when not in use.
• Each character is sent as a start bit (0), 7 or 8 data bits,
• an optional parity bit, and one or more stop bits (1’s).
• Most typically, start and stop bits and 8 bits of data are sent.
• The UART detects the falling transition from idle to start to
lock on to the transmission at the appropriate time.
• Although seven data bits is sufficient to send an ASCII
character, eight bits are normally used because they can convey
an arbitrary byte of data.
UART
OTHER MICROCONTROLLER PERIPHERALS

• Microcontrollers frequently interface with other external

peripherals.
• common examples, including
-character mode liquid crystal displays (LCDs)
-VGA monitors
- Bluetooth wireless links
-motor controllers.
Character LCDs

• A character LCD is a small liquid crystal display capable of

showing one or a few lines of text.
• They are commonly used in the front panels of appliances
such as cash registers, laser printers, and fax machines that
need to
• display a limited amount of information.
• They are easy to interface with a microcontroller over
parallel, RS232, or SPI interfaces.
VGA Monitor

• A more flexible display option is to drive a computer

monitor.
• The VGA monitor standard was introduced in 1987 for the
IBM PS/2 computers, with a 640 × 480 pixel resolution on a
cathode ray tube (CRT) and a 15-pin connector conveying
color information with analog voltages.
-Modern LCD monitors have higher resolution but remain
backward compatible with the VGA standard.
 VGA Monitor
• In a CRT, an electron gun scans across the screen from left to right, exciting fluorescent
material to display an image.
• Color CRTs use three different phosphors for red, green, and blue, and three electron
beams.
• The strength of each beam determines the intensity of each color in the pixel.
• At the end of each scan line, the gun must turn off for a horizontal blanking interval to
return to the beginning of the next line.
• After all of the scan lines are complete, the gun must turn off again for a vertical blanking
interval to return to the upper left corner.
• This entire process repeats about 60 to 75 times per second to refresh the fluorescence
and give the visual illusion of a steady image.
• Modern displays typically use LCD technology, which doesn’t require the same electron
scan gun but uses the same VGA interface timing for compatibility
VGA Monitor
 Bluetooth Wireless Communication
• Many standards are now available for wireless communication, including Wi-Fi,
ZigBee, and Bluetooth.
• The standards are elaborate and require sophisticated integrated circuits, and give
the user a simple interface for wireless communication.
• One of these modules is the BlueSMiRF, which is an easy-to-use Bluetooth wireless
interface that can be used instead of a serial cable.
• Bluetooth operates in the 2.4 GHz unlicensed industrial-scientific medical (ISM)
band.
• It defines 79 radio channels spaced at 1 MHz intervals starting at 2402 MHz.
• It hops between these channels in a pseudorandom pattern to avoid consistent
interference with other devices, such as wireless routers operating in the same band.
• BlueSMiRF Silver module, communicates with another Bluetooth device, such as
a laptop with built-in Bluetooth, or a Bluetooth USB dongle connected to a PC.
Thus, it can provide a wireless serial link between a RED-V and a PC similar
Motor Control
Motor Control