1.

Write verilog code for

2 to 1 mux and 4 to 1 mux using if else statement.

2. Write verilog code for 4 to 1 mux and 8 to 1 mux using case

statement.

3. Write 3 to 8 decoder using case statement.

4. Write 8 to 3 priority encoder using if else, casez and casex.

[Link] code for swapping the two variables.

1. Using third variable
2. Without using 3rd variable
[Link] Practice Programs

1. Write a verilog code to generate clock for 10 ns time period.

2. Write a verilog code for swapping of two variables with all

three techniques.

3. Verilog code for SR flip flop.

4. Write verilog code to design a mod 4 counter using dff.

( Structural Style of modeling)

5. Prepare a writeup for all the data types in verilog ( Please

explore tri, trireg, wand, wor etc. ...)

6. Write a verilog program to verify all the operators.1. Write a

function to print fibonacci series .

2. Write a function return maximum of 3 integer values.

3. Write a function to check whther the number is prime or not.

4. Write a function to check whether the number is palindrome or

not.Q1. Write a 3-bit up counter, synchrnous/asynchronous (0-7)
Q2. Write a 3-bit downcounter (7-0)
Q3. Write a bcd counter (0-9)
Q4. Write a 3-bit up/down counter
Q5. Write a program which counts (0-1-2-3-4-5-6-7-6-5-4-3-2-1-0-
1--------)---Thnik1. Clock Generation (fixed Time period, for a
given freq, for given Duty Cycle, clock for fractional time
period)
write a verilog code for clock generation of time period 0.5
ns. (Hint: `timescale 1ns/1ps)
always #0.25 clk=~clk;
2. FA using data flow, behaviorl, using structural (HAs),
gatelevel
3. MUX using Ternary operator, if-else, case, using boolean
expression.
4. Higher order mux using lower order mux (Structural
Modeling ) ----8x1 using 4x1 and 2x1.
5. Priority encoder using if-else, casex, casez.
 6. latches and FFs (use the concept of force and release to
generate logic for rst)
7. n-bit adder using generate (Configurable Adder), test it
for different n values ( Concept of defparam)
8. Frequecny divider codes (Even/odd), make fucntions as
well as tasks.
9. Code for facorial (concept of Automatic Fucntion-
Recursive Function).
10. Code of Counters (Structural and Behvirol Modeling)
(a) n-bit up counter
(b) down counter
(c) up-down Counter
(d) 0 1 2 3 2 1 0 (2-bit up-down)--Beh only.
11. Clock generation by XOR gate.
12. Write a code which generate clock with duty cyle 40% for
10 cycle and 70% for next 10 cycle and [Link] All

Please write these codes and send me by Today EOD.

1. Verilog code to generate clock pulse of 10 ns period whose
first 10 cycles are of 60% duty cycle and next 10 cycles are of
40% duty cycle, then repeats the same.

2. Write a verilog code which accept n-bit number (use

`define/parameter concept), and prints the number of 1's , number
of 0's , number of X's and Number of Z's present in this vector.

For Example: number: 10zz0zz1, Number of 1: 2, Number of 0: 2,

Number of x= 2, Number of z= 2.

3. Write a verilog code to detect the sequence : 1xx (using Mealy

overlapping)1. Write a code to Demonstrate the enum data type.
2. write a code to make ID card (Name, F_name, DOB, MobNUMBER),
store the values for 12 Students (your classmates) and Print.
3. Demonstrate the use of packed structure . (Explore the
difference between packed and unpacked structure interms of
memory).Verilog Interview Questions

1. What is HDL? Primary use of Verilog?

2. How to define module in Verilog? Explain module instantiation.
3. Different Level of Abastractions? Various Modeling Styles?
4. Various regions in Verilog excution?
5. Purpose of Simualtion.
6. What is TB? How simulation takes places.
7. Major Components of TB.
8. Name the different data types in Verilog.
9. Default size, type (unsigned/signed), default value for data
types.
10. How can we specify the size of signals.
11. difference between wire and net.
12. difference between time and realtime.
13. default data type in port decalaration.
14. Declare input having integer characteristics.
15. Number specification (Sized/unsized), negative numbers,
(Default base, default size in unsized numbers).
16. a= 32'b0101; a= 32'bx011; a= 32'b1011; a= 32'bz101; (outputs)
17. a= 4'h123 (size of a and value).
18. Regions in Verilog
19. >> and >>> difference. (Explain with Example)
20. == and === difference (Explain with Example)
21. Differnce between logical and bitwise operators (&& vs &)
22. Reduction operators.
23. Unary, Binary and Ternary opertors? Justify
24. Assignment operators ( Continuous: assign, Procedural:
blocking/NBA, procedural continuous: assign/deassign,
force/release.
25. Questions based on Fork Join, Initial begin (nesting of them),
delays etc. ( Please refere our ppts and solve all questions
without help.)
26. Concept of sensitivity list.
27. difference between initial and always block. (Which one is
synthesizable)
28. Always block without sensitivity list???
29. debugging of code having multiple always/initial block ,
problems associated with these codes.
30. Concept of Race codition, solution to remove.
31. Nesting of procedural blocks allowed??
32. If one code has initial block as well as always block, which
one exectutes first?
33. uses of @, # , posedge, negedge.
34. Write a code for FA using (a) Data flow (b) behavirol (c)
Structural Modeling
35. write a code for 2:1 MUX and 4:1 MUX using ternary operator,
if-else and case statement.
36. write a code priority encoder using (a) casez (b) casez (c)
if-else
37. write codes for latches and FF (please have information
related to Synch / Asynch reset)
38. Verilog code for Clock Generation.
39. Verilog code for Shift register.
40. Verilog code for 3- bit a) up counter b) down counter c)
updown counter.
41. Verilog code for MOD counters. (MOD-5, BCD etc).
42. Verilog code for jhonson counter.
43. Verilog code for Frequency Divider by Even number. (Extend it
to make a task)
44. Verilog code for Frequency Divider by odd number. (Extend it
to make a task)
45. Mealy Sequence Detector (101). (Overaapping/Non Overlapping)
46. Moore sequecne Detector (101). (Overlapping / Non
Overlapping)
47. Write verilog code to count: 0-1-2-3-4-5-6-7-6-5-4-3-2-1-
0--------
48. Write a code to detect whether number is prime or not .
(Extend this program to generate prime numbers between 1 -20 using
task/function)
49. Write a verilog code to reverse/sort/reveerse sort an array
without using predefined methods.
50. write a verilog code to count number of 1's, 0's, x's, z's
present in a vector of length 8.
1. Why always block is not used inside a program block?
The program block is generally used to develop a test case that
initiates a stimulus and then
it should end. But the ‘always’ block does not have any
provision to end by itself. Thus, we
can not have a program block. Even if you try to do so, a
compilation error is expected.
For a need basic, we can use the ‘forever’ loop as a work-
around with a ‘break’ statement to
terminate the loop as per requirement.
2. What is FIFO? What are underflow and overflow conditions in
FIFO?
Write Verilog code for the design.
FIFO stands for first in first out which means that the first
element enters into the buffer and
comes out first.
Underflow: When an attempt is made to read data from an empty
FIFO, it is called an
underflow. The design should have an ‘empty’ flag to avoid
getting invalid values
Overflow: When an attempt is made to write data into the already
full FIFO, it is called an
overflow. The design should have a ‘full’ flag to avoid losing
the data sent from the previous
module.

Refer verilog implementation of FIFO to explain working read and

write pointers to
determine underflow and overflow conditions: Synchronous FIFO
3. What are all different applications of FIFO?
Buffers: To hold data immediately till we get acknowledgment
whether previous data is
processed by a design or not.
Clock domain crossing: To exchange data between two systems that
work on different
clock frequencies
Ordering requirement in design: FIFO helps to process the data in
the required order
which ensures data is not overridden mistakenly. This is very
helpful in microprocessors,
and GPU designs, etc.
Pipeline Stages: FIFO makes sure the data flows in different
pipeline stages to process
multiple instructions concurrently.
4. What will happen if there is no else part in if-else?
In such a case, the missing ‘else’ (i.e. valid = 0 in the
below case) infers to latch in
synthesis.
Example:
always@(*) begin
if(en) begin
data <= 8‘hFF;
 end
end
5. Swap register content with and without using an extra register.
Without using an extra register:
always @(posedge clk) begin
m <= n;
n <= m;
end

//Using an extra register:

//Here, temp is an extra register used.
always @(posedge clk) begin
temp = n;
n = m;
m = temp;
endQue : What are soft reset, hard reset, cold reset, and warm
reset in RTL design and verification?
Ans: Soft Reset: A soft reset, also known as a software reset, is
a type of reset that is initiated by software rather than
hardware. When a soft reset is triggered, the processor resets all
of its internal regs.
Hard Reset: Also called a hardware reset, a hard reset is a type
of reset that is started by sending a physical signal to the
device. When a hard reset is done, the device’s power is turned
off and on again, and all of its internal registers are set back
to their original values.
Cold Reset: A cold reset is a type of hard reset that involves
completely powering off the device and then turning it back on
again. This type of reset is typically used when there is a major
system malfunction or when the device needs to be completely
reinitialized.
Warm Reset: A warm reset is also a type of hard reset, but it only
involves resetting the device’s internal registers and not
completely powering off the device. This type of reset is
typically used when there is a minor system malfunction or when
the device needs to be reinitialized without disrupting any
ongoing operations.
Que : What is clock gating?
Ans: Clock gating is a technique to turn off the clock for certain
parts when they are not needed. It is used to reduce power
dissipation.
Que : What are multi-drivers?
Ans: When the net or signal has two or more sources, it is
referred to as a multidriver.
Que : What is assign & deassign, force & release?
Ans: In Verilog, assign and deassign are used for assignments on
registers, while force and release can be used to override the
assignment on registers and nets.
Generally, force and release are used for debugging.
Que : What are compiler directives in Verilog?
Ans: The compiler directives in Verilog are: “define,
“include,” “ifdef, `ifndef,” etc.
Que : How we can run statements parallel without fork-join?
Ans: By using the always we can run statements parallel
For example: always @ (posedge clk)
a=1;
always @ (posedge clk)
b=1;
In this, a and b will be run parallel.Q. What is Static Function
nd Function Static???
‘Static function‘ is a function whose scope is static. That
mean, a static function remains
same for ALL the objects of a class. In system memory, the
function is stored at a single
place and all the objects access that function memory.A static
function can only access
static variables of a class.
‘Function static‘ is another type of function that makes the
scope of its internal variables
as static. This type of function DO NOT initialize its variables
during each call. The scope
of internal variables of function becomes static. Rest of the
class variables scope remains
the same (auto). All the automatic variables of class are
initialized for every object, but
the function’s internal variables remains [Link] Verilog
Practice Problem:
1. Write an SV program to demonstrate the Inheritance Concept.
2. Write a program to demonstrate Polymorphism.
3. Write a program to demonstrate the Shallow Copy and Deep Copy.
4. Write a program to demonstrate to use of a mailbox.
5. Write a program to demonstrate a parametrized class. Overriding
the parameter values at handle declaration.
6. Write a program to generate 20 unique values in 0 to 50 range.
1. write a constraint to generate prime 10 prime numbers in 0-99
ranges (unique)
(Hint: use a function call)

2. Write a constraint to generate fibonacii series : 0 1 1 2 3

5 8......
3. write a constraint to generate : 1 2 2 3 3 3 4 4 4
4 .......Q10. module fork_join;

initial begin

$display("*BEFORE FORK..JOIN*");

fork
#15 $display($time,"\tThread A");
#5 $display($time,"\tThread B");
#10 $display($time,"\tThread C");
#2 $display($time,"\tThread D");
join

#7 $display($time,"\tThread E");

$display("*AFTER FORK..JOIN*");
 $finish;
end
endmodule

Q11. module fork_join;

initial begin

$display("*BEFORE FORK..JOIN*");

fork
begin
#15 $display($time,"\tThread A");
#5 $display($time,"\tThread B");
end
begin
#10 $display($time,"\tThread C");
#2 $display($time,"\tThread D");
end
join

#7 $display($time,"\tThread E");

$display("*AFTER FORK..JOIN*");

$finish;
end

endmodule

Q12. module fork_join_any;

initial begin

$display("*BEFORE FORK..JOIN_ANY*");

fork
#15 $display($time,"\tThread A");
#5 $display($time,"\tThread B");
#10 $display($time,"\tThread C");
Join_any

#2 $display($time,"\tThread D");
#12 $display($time,"\tThread E");

$display("*AFTER FORK..JOIN_ANY*");

#30 $finish;
end

endmodule

Q13. module fork_join_any;

 initial begin

$display("*BEFORE FORK..JOIN_ANY*");

fork
begin
#20 $display($time,"\tThread A");
#25 $display($time,"\tThread B");
end
begin
#10 $display($time,"\tThread C");
#2 $display($time,"\tThread D");
end
join_any
#4 $display($time,"\tThread E");
#3 $display($time,"\tThread F");

$display("*AFTER FORK..JOIN_ANY*");

#30 $finish;
end

endmodule

Q14. module fork_join_none;

initial begin

$display("*BEFORE FORK..JOIN_ANY*");

fork
#15 $display($time,"\tThread A");
#5 $display($time,"\tThread B");
#10 $display($time,"\tThread C");
join_none

#2 $display($time,"\tThread D");
#12 $display($time,"\tThread E");

$display("*AFTER FORK..JOIN_NONE*");

#30 $finish;
end

endmodule

Q15. module wait_fork;

initial begin
$display("*BEFORE_FORK*");
 fork
begin
$display($time,"\tThread A");
#15;
$display($time,"\tThread B");
end

begin
$display($time,"\tThread C");
#30;
$display($time,"\tThread D");
end
join_any

$display("*AFTER_FORK*");

$finish;

end
endmodule

Q16. module wait_fork;

initial begin
$display("*BEFORE_WAIT_FORK*");

fork
begin
$display($time,"\tThread A");
#15;
$display($time,"\tThread B");
end

begin
$display($time,"\tThread C");
#30;
$display($time,"\tThread D");
end
join_any

wait fork; //waiting for all active fork threads to be

finished

$display("*AFTER_WAIT_FORK*");

$finish;

end
endmodule

Q17. module disable_fork;

initial begin
 $display("*BEFORE_DISABLE_FORK*");

fork
begin
$display($time,"\tThread A");
#15;
$display($time,"\tThread B");
end

begin
$display($time,"\tThread C");
#30;
$display($time,"\tThread D");
end
join_any

fork
begin
$display($time,"\tThread A1");
#15;
$display($time,"\tThread B1");
end

begin
$display($time,"\tThread C1");
#30;
$display($time,"\tThread D1");
end
join_none

disable fork;

$display("*AFTER_DISABLE_FORK*");

$finish;

end
endmodule

Q18. module disable_specific_thread;

initial begin
$display("*BEFORE_DISABLE_SPECIFIC_THREAD*");

fork
begin : A1
$display($time,"\tThread A");
#30;
$display($time,"\tThread B");
end

begin : B1
 $display($time,"\tThread C");
#15;
$display($time,"\tThread D");
end
join_any

disable A1;

$display("*AFTER_DISABLE_SPECIFIC_THREAD*");

#50 $finish;

end
endmodule

How to design counter(asyn. And syn)

Flip flop conversion
Mod 5 counter using d both [Link] async.
Latches and flip flop difference
Sequential and combinational difference
Characteristics and excitation table of all flip flop

1. Simplify the Boolean function Y = Σ ( 0,2,3,5,7,10,11,15)

in POS form using KMap?
2. Give the AND-OR implementation of a circuit, using minimum
gates, that givesHIGH when the input is BCD equivalent of 5,7 or 9
and LOW otherwise. ?
3. (a) Show the AOI implementation of a 2:1 Mux? (b) Convert
this to 2-input NAND implementation?
4. Design the AND, OR, XOR, XNOR and NOT gates using minimum
number of 2:1 Muxes?
5. Design a circuit for 3-input majority function using a 4:1
Mux?
6. Design 10:1 Mux using 4:1 muxes.
7. (a) Expand the Boolean function f(x,y,z) = x’z’ + xy +
xz in terms of x?(b) Implement f using a 2:1 Mux and external
gates?
8. You are given a 2:4 decoder, a 2 input OR gate and a 3 input
OR gate. Using thesecomponents design a system which takes A & B
as inputs and generates the followingfour outputs: AB, (AB)' ,
A+B, (A+B)'.
9. Implement a full adder using (a) 4:1 Muxes (b) 2:1 Muxes
10. If each XOR gate has a propagation delay of 10ns and AND/OR
gate has a delay of5ns each (irrespective of number of inputs),
what is the total propagation delay in addingtwo 4 bit numbers in
case of (a) Normal full adder (b) Carry Look Ahead adder.
Hint: Step1: Generation of Pi, Gi (P = Ai XOR Bi and G = Ai AND
Bi)
Step2: Generation of carry: And-Or stage Ci+1 = Gi+ PiCi
Step3: Sum generation: Sum = Pi XOR Ci

11. Explain how a full adder can be used as majority function?

12. How will you count the number of 1's that are present in a
given 3-bit input using fulladder?
13. In the below circuit, the inverters have delay of T1 and T2
respectively. IN is a clock signal with 50% duty cycle and period
T. It is given that T1+T2 is less than T/2.
(a) What is the functionality of the circuit shown above?
(b) Derive the duty cycle of output waveform?
(c) What is the condition to get 50% duty cycle at the output
also?

14. Implement 2:4 decoder using 2:1 1muxes.

15. Implement 1:2 Demux using 2:1 Muxes.

16. Using a 4:16 decoder and minimum number of external gates

implement the following Boolean functions:(a) F(A,B,C,D) = Σ
(5,7,9,14)
(b) G(A,B,C,D) = Σ(0,1,2,3,4,6,7,8,9,10,11,14,15)
17. a. applications of flip-flops?
b. What is the difference between a LATCH and a Flip flop?
18. Which input combinations are not allowed in (a) NAND based (b)
NOR based S-RLatch? Explain
19. Design a D-latch using 2:1 Mux. Extend it to Dff.
20. Design a T-latch using 2:1 Mux. Extend it to Tff.
21. What is race-around condition? Explain it in case of J-K Latch
and solution to avoid that?
22. Construct a J-K flip flop using a DFF, 2:1 Mux and an-
inverter?
23 What is excitation table? Write Excitation Table for JK FF.
24. Which flip-flop can be used as delay switch and which flip
flop is used a toggle switch?
25. A AB flip flop has 4 operations: clear to 0, no change,
compliment and set to 1, when inputs A and B are 00, 01, 10 and 11
respectively. Derive the characteristic equation?
26. What is Moore model & Mealy model? Explain.
27. What is one-hot method? List the advantages and disadvantages?
28. What is Setup time, Hold time and clock skew? Explain.
29. Can hold time be negative? Explain.
30. What is the difference between a ripple counter and a
synchronous counter?
31. To count from 0 to N-1, how many flip-flops are needed?
32. Design a frequency divide-by-2 circuit using DFF and external
gates which gives(a)50% duty cycle (b) 25% duty cycle?
33. Design frequency divide-by-3 circuit using DFFs and external
gates which gives aduty cycle of 1/3?
34. There is a room which has two doors one to enter and another
to leave. There is a sensor in the corridor at the entrance and
also at the exit. There is a bulb in the room which should turn
off when there is no one inside the room. So imagine a black box
with the inputs as the outputs of sensors. What should the black
box be?
35. What are the unused states in a 3-bit Johnson counter?
36. What is the output frequency of a 4-bit binary counter for an
input clock of 160MHz?
37. If each flip flop has a clock-to-Q delay of 10ns, how much
time will it take for output to change to its next state in case
of (a) 4-bit Ripple Counter (b) 4-bit Synchronous counter?

38. What are the frequencies F1, F2, F3 and F4 after each stage if
an input clock of10MHz is applied?
1. Implement nand gate using mux.

2. implement 15:1 mux using 2:1mux.

3. Design the ckt for 3 bit input, for which output will be high
if the input is palindrome number

4. Represent -25 in 2's complement

5. Conversion of binary to gray

6. We have ckt with 4 inputs and 4 outputs, design a ckt which

gives output high when 4 bit input = 4 bit output.

7. Waveform of SR latch, SR ff, JK latch, JK ff.

8. What will be the output of following code,

reg a=0;
always@(a)
begin
a<=~a;
display("a=%d",a);
end
endmodule

9. Is there any difference between

byte a; and
bit signed [7:0] a;

10. Regions of verilog

11. Region based codes.

12. What is difference between $write and $display

13. What does $monitor work

14. How we can print like $monitor without using $monitor

15. We have two bcd counter. We have to count 00 to 60. What can
be done ?

16. 10x mealy overlapping state diagram

17. Which one is better

Mealy overlapping or non overlapping

1. Implement nand gate using mux.

2. implement 15:1 mux using 2:1mux.

3. Design the ckt for 3 bit input, for which output will be high
if the input is palindrome number

4. Represent -25 in 2's complement

5. Conversion of binary to gray

6. We have ckt with 4 inputs and 4 outputs, design a ckt which

gives output high when 4 bit input = 4 bit output.

7. Waveform of SR latch, SR ff, JK latch, JK ff.

8. What will be the output of following code,

reg a=0;
always@(a)
begin
a<=~a;
display("a=%d",a);
end
endmodule

9. Is there any difference between

byte a; and
bit signed [7:0] a;

10. Regions of verilog

11. Region based codes.

12. What is difference between $write and $display

13. What does $monitor work

14. How we can print like $monitor without using $monitor

15. We have two bcd counter. We have to count 00 to 60. What can
be done ?

16. 10x mealy overlapping state diagram

17. Which one is better

Mealy overlapping or non overlapping

Mock interview questions

.....................................................

1)
Integer x,y;
initial
begin
x = 5;
y = 8;
x<=x+y;
y<=x+y;
x=x-2;

$strobe(“strobe x=%0d, y=%0d”, x,y);

$display(“display x=%0d, y=%0d”, x,y);
end

What is the value x and y?

//2)
reg a;
initial a=0;
always@(a)
begin
a<=~a;
$display(“Value of a=%d”,a);
end

What is the value of a?

//3)
initial begin
x = 2;
#4;
y <= #1 x;
x = 1;
end

What is the value of x and y?

//4)How will the following program works?

always@(posedge clk)
begin
reg1<=inp1;
reg2<=reg1;
reg3<=reg2;
out<=reg3;
end

5)How will the following program works?

always@(posedge clk)
begin
reg1=inp1;
reg2=reg1;
reg3=reg2;
out=reg3;
end
6)What is johnson counter?where we can use them?
7)What are compliments?Explain 2's compliment over 1's complement?
8)design a 3:1 mux?
9)design 5:1 mux using 2:1 mux?
10)basic boolean theorems?
11)consensus theorem?
12)Why we use grey code in K map?
13)What are PI,EPI, SPI, and RPI in K map?
14)Explain working of d_ff with clock diagram?
one clock delay circuit?
15)Difference between reg and wire?
16)write code for d_latch and d_ff?
17)Make a circuit where input will be delayed by one clock?
18)Difference between Moore and mealy?
19)Design xor gate,or gate,D_latch,d_ff using 2:1 mux?
20)Design a ckt for frequency/3?
21)Explain about $monitor,$display,$strobe?
22)Write fsm for the sequence '10X' ?

Observe these Codes , Analyse and Comment on the Output of the

Snippet with Justification
Q1. module tb;
bit a;
initial begin
a= 1;
$display(a);
end
always@(a)
begin
a=~a;
end
endmodule

Q2. module tb;

bit a;
initial begin
a= 1;
forever@(a)
$display(a);
end
always@(a)
begin
a=~a;
end
endmodule

Q3. module tb;

bit a;
initial begin
a= 1;
$display(a);
end
always@(a)
 begin
a<=~a;
end
endmodule

Q4. module tb;

bit a;
initial begin
a= 1;
forever@(a)
$display(a);
end
always@(a)
begin
a<=~a;
end
endmodule
1. Make 10ns clock
2. Design(program) divide by 2 frequency divider without using
counter
3. Make a flow like Active then inactive then nba then again
active instead of postponed
4. 3 bit Palindrome question same that were asked to priyam
5. In 8 bit register , count the no. of 1, 0, x and z.(program)

Design a FSM which detects more than one 1's in last 3-samples

Mealy and moore both...

Q] Xor cct using NAND gate & verify it.

Q] 5X1 mux using 2X1 mux
Q] Design 4 bit palidrom cct.
Q] write FSM for palidrom cct.
Q] write a program to cheak palidrom of 32 bit.
Q] Design BCD counter of 60.
Q] Difference between Inter & intra assignment delay.
Q] How to identify binary number is odd or even.