Unit – 6 shift register

A register is a device which is used to store information. Flip flops are often used to make a
register. Each flip flop can store 1 bit of information and therefore for storing a n-bit word
n-flip-flops are required in the register. The input to a register or output from it may be
either in serial or parallel form depending upon the requirement.

A shift register is a storage device that used to store binary data. When a number of flip
flop are connected in series it is called a register. A single flip flop can stay in one of the two
stable states 1 or 0 or in other words the flip flop contains a number 1 or 0 depending upon
the state in which it is. A register can contain a series of bits which can be termed as a word
or a byte.

Shift Registers are used for data storage or for the movement of data and are therefore
commonly used inside calculators or computers to store data such as two binary numbers
before they are added together, or to convert the data from either a serial to parallel or
parallel to serial format. The individual data latches that make up a single shift register are
all driven by a common clock (CLK) signal making them synchronous devices.
Shift register IC’s are generally provided with a clear or reset connection so that they can be
“SET” or “RESET” as required. Generally, shift registers operate in one of four different
modes with the basic movement of data through a shift register being:
 Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a time,
with the stored data being available at the output in parallel form.
 Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of the register,
one bit at a time in either a left or right direction under clock control.
 Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time under clock
control.
 Parallel-in to parallel-out (PIPO) - the parallel data is loaded simultaneously into the
register, and transferred together to their respective outputs by the same clock pulse.
The effect of data movement from left to right through a shift register can be presented
graphically as:

Also, the directional movement of the data through a shift register can be either to the left,
(left shifting) to the right, (right shifting) left-in but right-out, (rotation) or both left and
right shifting within the same register thereby making it bidirectional. In this tutorial it is
assumed that all the data shifts to the right, (right shifting).

Serial-in to Parallel-out (SIPO) Shift Register

4-bit Serial-in to Parallel-out Shift Register

The operation is as follows. Lets assume that all the flip-flops ( FFA to FFD ) have just been
RESET ( CLEAR input ) and that all the outputs QA to QD are at logic level “0” ie, no parallel
data output.
If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the
output of FFA and therefore the resulting QA will be set HIGH to logic “1” with all the other
outputs still remaining LOW at logic “0”. Assume now that the DATA input pin of FFA has
returned LOW again to logic “0” giving us one data pulse or 0-1-0.
The second clock pulse will change the output of FFA to logic “0” and the output of FFB
and QB HIGH to logic “1” as its input D has the logic “1” level on it from QA. The logic “1” has
now moved or been “shifted” one place along the register to the right as it is now at QA.
When the third clock pulse arrives this logic “1” value moves to the output of FFC ( QC ) and
so on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back again
to logic level “0” because the input to FFA has remained constant at logic level “0”.
The effect of each clock pulse is to shift the data contents of each stage one place to the
right, and this is shown in the following table until the complete data value of 0-0-0-1is
stored in the register. This data value can now be read directly from the outputs of QA
to QD.
Then the data has been converted from a serial data input signal to a parallel data output.
The truth table and following waveforms show the propagation of the logic “1” through the
register from left to right as follows.
Basic Data Movement Through A Shift Register
Clock Pulse QA QB QC QD
No
0 0 0 0 0
1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1
5 0 0 0 0
Note that after the fourth clock pulse has ended the 4-bits of data (0-0-0-1) are stored in
the register and will remain there provided clocking of the register has stopped. In practice
the input data to the register may consist of various combinations of logic “1” and “0”.
Commonly available SIPO IC’s include the standard 8-bit 74LS164 or the 74LS594.

Serial-in to Serial-out (SISO) Shift Register

This shift register is very similar to the SIPO above, except were before the data was read
directly in a parallel form from the outputs QA to QD, this time the data is allowed to flow
straight through the register and out of the other end. Since there is only one output,
the DATA leaves the shift register one bit at a time in a serial pattern, hence the
name Serial-in to Serial-Out Shift Register or SISO.
The SISO shift register is one of the simplest of the four configurations as it has only three
connections, the serial input (SI) which determines what enters the left hand flip-flop, the
serial output (SO) which is taken from the output of the right hand flip-flop and the
sequencing clock signal (Clk). The logic circuit diagram below shows a generalized serial-in
serial-out shift register.

4-bit Serial-in to Serial-out Shift Register

This type Shift Register also acts as a temporary storage device or it can act as a time delay
device for the data, with the amount of time delay being controlled by the number of
stages in the register, 4, 8, 16 etc or by varying the application of the clock pulses.
Commonly available IC’s include the 74HC595 8-bit Serial-in to Serial-out Shift Register all
with 3-state outputs.
Parallel-in to Serial-out (PISO) Shift Register
The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-
out one above. The data is loaded into the register in a parallel format in which all the data
bits enter their inputs simultaneously, to the parallel input pins PA to PD of the register. The
data is then read out sequentially in the normal shift-right mode from the register
at Q representing the data present at PA to PD.
This data is outputted one bit at a time on each clock cycle in a serial format. It is important
to note that with this type of data register a clock pulse is not required to parallel load the
register as it is already present, but four clock pulses are required to unload the data.

4-bit Parallel-in to Serial-out Shift Register

As this type of shift register converts parallel data, such as an 8-bit data word into serial
format, it can be used to multiplex many different input lines into a single serial DATA
stream which can be sent directly to a computer or transmitted over a communications
line. Commonly available IC’s include the 74HC166 8-bit Parallel-in/Serial-out Shift
Registers.

Parallel-in to Parallel-out (PIPO) Shift Register

The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of shift
register also acts as a temporary storage device or as a time delay device similar to the SISO
configuration above. The data is presented in a parallel format to the parallel input
pins PA to PD and then transferred together directly to their respective output
pins QA to QA by the same clock pulse. Then one clock pulse loads and unloads the register.
This arrangement for parallel loading and unloading is shown below.

4-bit Parallel-in to Parallel-out Shift Register

The PIPO shift register is the simplest of the four configurations as it has only three
connections, the parallel input (PI) which determines what enters the flip-flop, the parallel
output (PO) and the sequencing clock signal (CLK).
Similar to the Serial-in to Serial-out shift register, this type of register also acts as a
temporary storage device or as a time delay device, with the amount of time delay being
varied by the frequency of the clock pulses. Also, in this type of register there are no
interconnections between the individual flip-flops since no serial shifting of the data is
required.

Universal Shift Register

Today, there are many high speed bi-directional “universal” type Shift Registers available
such as the TTL 74LS194, 74LS195 or the CMOS 4035 which are available as 4-bit multi-
function devices that can be used in either serial-to-serial, left shifting, right shifting, serial-
to-parallel, parallel-to-serial, or as a parallel-to-parallel multifunction data register, hence
the name “Universal”.
These universal shift registers can perform any combination of parallel and serial input to
output operations but require additional inputs to specify desired function and to pre-load
and reset the device.
Universal shift registers are very useful digital devices. They can be configured to respond
to operations that require some form of temporary memory storage or for the delay of
information such as the SISO or PIPO configuration modes or transfer data from one point
to another in either a serial or parallel format. Universal shift registers are frequently used
in arithmetic operations to shift data to the left or right for multiplication or division.
Shift Register Tutorial Summary
Then to summarize a little about Shift Registers
 A simple Shift Register can be made using only D-type flip-Flops, one flip-Flop for
each data bit.
 The output from each flip-Flop is connected to the D input of the flip-flop at its right.
 Shift registers hold the data in their memory which is moved or “shifted” to their
required positions on each clock pulse.
 Each clock pulse shifts the contents of the register one bit position to either the left or
the right.
 The data bits can be loaded one bit at a time in a series input (SI) configuration or be
loaded simultaneously in a parallel configuration (PI).
 Data may be removed from the register one bit at a time for a series output (SO) or
removed all at the same time from a parallel output (PO).
 One application of shift registers is in the conversion of data between serial and
parallel, or parallel to serial.
 Shift registers are identified individually as SIPO, SISO, PISO, PIPO, or as a Universal
Shift Register with all the functions combined within a single device.

Synchronous Sequential Circuit: Output changes at discrete interval of time. It is a circuit

based on an equal state time or a state time defined by external means such as clock.
Examples of synchronous sequential circuit are Flip Flops, Synchronous Counter.

In these all the flipflops are connected to common clock .so output that we get is faster
compared to asynchronous flipflop.
In a synchronous sequential circuit the memory element changes its state due to change in
input only on the negative or positive edge of the incoming clock pulse.

Asynchronous Sequential Circuit: Output can be changed at any instant of time by

changing the input. It is a circuit whose state time depends solely upon the internal logic
circuit delays. Example of asynchronous sequential circuit is Asynchronous Counter.

In asynchronous counters all the flipflops are not clocked simultaneously; one flipflop
should wait for the output of another flipflop. So, the output is delayed.

While asynchronous sequential circuits have delay element or unclocked flipflops that
change their state almost instantly as the inputs are changed as no clock pulse exists.

Asynchronous/Ripple Counter
 Flip flops are connected in such a way that the o/p of first flip-flop drives the clock of
next flip-flop.
 Flip-flops are not clocked simultaneously.
 Circuit is simple for more number of states.
 Speed is slow as clock is propagated through number of stages.
 Asynchronous Counter is also known as “Ripple Counter” because of the way the
clock pulses or ripples, its way through the flip-flop.

Synchronous Counter
 There is no connection between o/p of first flip-flop and clock of next flip-flop.
 Flip-flops are clocked simultaneously.
 Circuit becomes complicated as number of states increases.
 Speed is high as clock is given at a same time.
Counter
Counter is a sequential circuit. A digital circuit which is used for counting pulses is known
counter. Counter is the widest application of flip-flops. It is a group of flip-flops with a clock
signal applied. Counters are of two types.
 Asynchronous or ripple counters.
 Synchronous counters.
Asynchronous or ripple counters
The logic diagram of a 2-bit ripple up counter is shown in figure. The toggle (T) flip-flop are
being used. But we can use the JK flip-flop also with J and K connected permanently to logic
1. External clock is applied to the clock input of flip-flop A and QA output is applied to the
clock input of the next flip-flop i.e. FF-B.

Logical Diagram

Truth Table

Synchronous counters
If the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such a
counter is called as synchronous counter.
2-bit Synchronous up counter
The JA and KA inputs of FF-A are tied to logic 1. So FF-A will work as a toggle flip-flop. The
JB and KB inputs are connected to QA.
Logical Diagram

Classification of counters
Depending on the way in which the counting progresses, the synchronous or asynchronous
counters are classified as follows −
 Up counters
 Down counters
 Up/Down counters

UP/DOWN Counter
Up counter and down counter is combined together to obtain an UP/DOWN counter. A
mode control (M) input is also provided to select either up or down mode. A combinational
circuit is required to be designed and used between each pair of flip-flop in order to achieve
the up/down operation.
Type of up/down counters
 UP/DOWN ripple counters
 UP/DOWN synchronous counter
 UP/DOWN Ripple Counters
In the UP/DOWN ripple counter all the FFs operate in the toggle mode. So either T flip-flops
or JK flip-flops are to be used. The LSB flip-flop receives clock directly. But the clock to every
other FF is obtained from (Q = Q bar) output of the previous FF.
UP counting mode (M=0) − The Q output of the preceding FF is connected to the clock of
the next stage if up counting is to be achieved. For this mode, the mode select input M is at
logic 0 (M=0).
DOWN counting mode (M=1) − If M = 1, then the Q bar output of the preceding FF is
connected to the next FF. This will operate the counter in the counting mode.

Example
3-bit binary up/down ripple counter.
3-bit − hence three FFs are required.
UP/DOWN − So a mode control input is essen al.
For a ripple up counter, the Q output of preceding FF is connected to the clock input of the
next one.
For a ripple up counter, the Q output of preceding FF is connected to the clock input of the
next one.
For a ripple down counter, the Q bar output of preceding FF is connected to the clock input
of the next one.
Let the selection of Q and Q bar output of the preceding FF be controlled by the mode
control input M such that, If M = 0, UP counting. So connect Q to CLK. If M = 1, DOWN
counting. So connect Q bar to CLK.
Block Diagram

Truth Table
 Modulus Counter (MOD-N Counter)
The 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple counter is called as
MOD-8 counter. So in general, an n-bit ripple counter is called as modulo-N counter.
Where, MOD number = 2n.
Type of modulus
 2-bit up or down (MOD-4)
 3-bit up or down (MOD-8)
 4-bit up or down (MOD-16)
Application of counters
 Frequency counters
 Digital clock
 Time measurement
 A to D converter
 Frequency divider circuits
 Digital triangular wave generator.

PROGRAMMABLE LOGIC ARRAY

A programmable logic array (PLA) has a programmable AND array at the inputs and
programmable OR array at the outputs. The PLA has a programmable AND array instead of
hard-wired AND array. The number of AND gates in the programmable AND array are
usually much less and the number of inputs of each of the OR gates equal to the number of
AND gates. The OR gate generates an arbitrary Boolean function of minterms equal to the
number of AND gates. Figure below shows the PLA architecture with four input lines, a
programmable array of eight AND gates at the input and a programmable array of two OR
gates at the output.
Advantages
PLA architecture more efficient than a PROM.
Disadvantage
PLA architecture has two sets of programmable fuses due to which PLA devices are
difficult to manufacture, program and test.