1) a) Division by 2 b) Multiplication by 2 c) Addition by 2 d) Subtraction by 1
2) In an arithmetic right shift, the vacant MSB is filled with:
a) 0 b) 1 c) Sign bit d) LSB
3) Barrel shifters are mainly used to:
a) Reduce area b) Perform shifts in one clock cycle
c) Store data d) Reduce power only
4) Which shifter preserves the sign of a signed number?
a) Logical left b) Logical right c) Arithmetic right c) Rotate left
5) Rotation differs from shifting because rotation:
a) Discards bits b) Preserves all bits c) Adds zeros d) Changes sign
6) A half adder can add:
a) Three bits b) Two bits only c) Four bits d) Multi-bit numbers
7) Carry propagation delay is highest in:
a) Carry Look-Ahead Adder b) Carry Skip Adder
c) Ripple Carry Adder d) Carry Save Adder
8) Which adder is commonly used in multipliers?
a) Ripple Carry Adder b) Carry Save Adder
c) Half Adder d) Carry Look-Ahead Adder
9) A full adder has how many inputs?
a) 2 b) 3 c) 4 d) 5
10) Carry Look-Ahead Adders improve speed by:
a) Reducing gate count b) Predicting carry in advance
c) Using serial addition d) Reducing bit width
11) Hardware multiplication is primarily based on:
a) Shifting and addition b) Division c) Subtraction d) Rotation
12) Booth’s algorithm is mainly used to:
a) Reduce memory b) Speed up addition
c) Handle signed multiplication efficiently d) Reduce clock frequency
13) Array multipliers are known for their:
a) Small area b) Regular structure c) Low power only d) Serial operation
14) Which multiplier is the slowest?
a) Booth multiplier b) Wallace tree multiplier c) Serial multiplier d) Array
15) Wallace tree multipliers reduce:
a) Power consumption b) Number of partial product stages
c) Memory size d) Control complexity
16) Parity generators are mainly used for:
a) Error detection b) Error correction c) Data compression d) Encryption
17) Even parity means the total number of 1s is:
a) Odd b) Even c) Prime d) Zero
18) Which logic gate is commonly used in parity generation?
a) AND b) OR c) XOR d) NAND
19) Parity checking can detect:
a) All errors b) Single-bit errors c) Burst errors d) Timing errors
20) Parity generator is a______________ circuit
a) Sequential b) Combinational c) Memory element d) Feedback system
21) A digital comparator compares:
a) Voltages b) Frequencies c) Binary numbers d) Power levels
22) Comparator output indicates:
a) Equal only b) Greater only c) Less only d) Equal, greater, or less
23) A 4-bit magnitude comparator compares___________________.
a) 2-bit numbers b) 3-bit numbers c) 4-bit numbers d) 8-bit numbers
24) Cascading comparators is done to:
a) Reduce power b) Increase bit-width comparison
c) Reduce delay d) Improve noise margin
25) Comparator outputs are generally:
a) Analog b) Tri-state c) Digital logic levels d) Floating
26) A zero detector checks whether:
a) All bits are 1 b) All bits are 0 c) MSB is 0 d) LSB is 0
27) For a pseudo nMOS design the impedance of pull up and pull down ratio is
[ ]
a) 4:1 b) 1:4 c) 3:1 d) 1:3
28) _____________ is a circuit that detects the output of logic is always 1. [ ]
a) 0 detector b) 1 detector c) All 0 detector d) None
29) _________ Comparator determines if the numbers A and B are equal [ ]
a) Magnitude b) Equality c) Error d) None
30) For signals which are updated frequently _____ is used. [ ]
a) static storage b) dynamic storage
c) static and dynamic storage d) buffer
31) Which contributes to the wiring capacitance?
[ ]
a) fringing fields b) interlayer capacitance
c) peripheral capacitance d) all the mentioned
32) Interlayer capacitance occurs due to ___________. [ ]
a) separation between plates b) electric field between plates
c) charges between plates d) parallel plate effect
33) Which layer has high capacitance value? [ ]
a) metal b) diffusion c) silicide d) polysilicon
34) A transmission gate (TG) logic is formed by connecting NMOS and PMOS Transistors
in _____. [ ]
a) Series b) Parallel c) both (a) or (b) d) none of these
35) A PLD device consist of ________and ______arrays [ ]
a) OR, AND b) AND, OR c) NAND, NOR d) AND, AND
36) In CMOS NAND gate, p transistors are connected in__________ [ ]
a) series b) parallel c) cascade d) random
1) The typical values of sheet resistance for the n-well semiconductor is ____.
[ ]
a) 1-5 KΩ/square b) 10-50 KΩ/square
c) 1-5 Ω/square d) 100-500 Ω/square
2) ________________ of faults are easier to detect.
[ ]
a) 50% b) 60% c) 70% d) 80%
3) In CMOS domino logic ___________ is used.
[ ]
a) two phase clock b) three phase clock
c) one phase clock d) four phase clock
4) CMOS domino logic is same as ______ with inverter at the output line.
[ ]
a) clocked CMOS logic b) dynamic CMOS logic
c) gate logic d) switch logic
1) The programming technology used in Field Programmable Logic Device is
______ and _________.
2) A combinational logic circuit with n-inputs requires ____ test vectors for
testing.
3) JTAG stands for_______________.
4) Design for Testability (DFT) is based on the two concepts of ______ and
_____.
5) _____ Faults assign a fixed value of either 0 or 1 to the input or output of a
gate.
6) For a 4:1 Nmos inverter circuit, total delay per nmos pair is ______.
7) ___________ Layer has high resistance value?
8) The power dissipation in Pseudo-nMOS is reduced to about ________
compared to nMOS device.
9) Programmable Logic Array has _____________.
10) Clocked sequential circuit’s are_____________.
37) The internal architecture of FPGA consists of _____________, _________ and
_______________.
38) Dynamic logic circuit design uses a sequence of _______ and ____ phase.
39) FPGA is the acronym for_______________.
40) FPGA Programming technologies are ______, ________.
41) ________ of the area is dedicated for testability.
42) ___________ is used to drive high capacitance load.
43) Register cell consists ______________.
44) Transistors being permanently open or short state are referred as ____ faults.
45) ____________ testing is performed during the design process.
46) A typical CPLD consist of _______, _______ and ____.
5) In a typical pseudo-nmos logic, the pull-up network is replaced by a single
_____ transistor. a) NMOS
b) PMOS c) CMOS d) Bi-CMOS
[ ]
6) The minimum no. of test vectors required for testing a sequential logic
circuit with n-inputs is given by _____.
[ ]
a) 2 m
b) 2 n
c) 2 (m+n)
d) 2mn
7) What is the sum ________ and carry________? if the two-bit number is 1 1
and the previous carry is 1. a)0 , 0
b) 0 , 1 c) 1 , 0 d) 1 , 1
[ ]
8) In design process gate minimization techniques are used to simplify the
logic. [ ]
a) True b) False
9) Propagation time is directly proportional to ____________.
[ ]
a) x b) 1/x c) x2 d) 1/x2
10) Overall delay is directly proportional to ___________.
[ ]
a) n b) 1/n c) n2 d) 1/n2
11)