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Sample de Lab Questions

The document outlines various digital circuit design tasks, including the implementation of combinational circuits like full adders, half subtractors, and demultiplexers, as well as sequential elements such as shift registers and counters. It also includes tasks for converting binary codes, verifying Boolean functions, and validating De Morgan's Laws through truth tables. Each task emphasizes the use of fundamental logic gates and specific integrated circuits to achieve the desired functionalities.

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darshanprabadevi
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5 views1 page

Sample de Lab Questions

The document outlines various digital circuit design tasks, including the implementation of combinational circuits like full adders, half subtractors, and demultiplexers, as well as sequential elements such as shift registers and counters. It also includes tasks for converting binary codes, verifying Boolean functions, and validating De Morgan's Laws through truth tables. Each task emphasizes the use of fundamental logic gates and specific integrated circuits to achieve the desired functionalities.

Uploaded by

darshanprabadevi
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

i. Design and implement a combinational circuit for full adder using basic gates.

ii. Design and implement a Parallel-In-Serial-Out (PISO) Shift Register using suitable sequential
logic elements.
i. Design a half subtractor circuit using logic gates. Construct the circuit and read output
difference and borrow. Verify its truth table.
ii. Design and implement 1:4 demultiplexer using logic gates.
i. Design a half subtractor circuit using logic gates. Construct the circuit and read output sum and
carry. Verify its truth table.
ii. Design and implement 4-bit Binary to Gray code converter
i. Design a half adder circuit using logic gates. Construct the circuit and read output sum and
carry. Verify its truth table.
ii. Design and implement 4-bit Gray to Binary code converter
i. Design and implement a 4-bit magnitude comparator utilizing the 7485 IC, and verify its
functionality by comparing two 4-bit binary inputs to determine whether one is greater than, less
than, or equal to the other.
ii. Design and implement a 4:1 multiplexer using fundamental digital logic gates, and
demonstrate its operation by selecting one of four input signals based on the corresponding
control (select) lines.
i. Design and implement 4-bit Binary to Gray code converter.
ii. Design and implement a 2-to-4 line decoder using fundamental logic gates, and verify its
functionality.
i. Design and implement a combinational circuit for full subtractor using basic gates.
ii. Design and implement a Parallel-In Parallel-Out (PIPO) Shift Register using suitable sequential
logic elements.
i. Design and implement a Parallel-In Parallel-Out (PIPO) Shift Register using suitable sequential
logic components.
ii. Design and implement a combinational logic circuit that performs the functionality of a Half
Subtractor using fundamental digital logic gates
i. Design and implement a Serial-In Serial-Out (SISO) and Serial-In Parallel-Out (SIPO) Shift
Register.
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ii. Implement and verify the Boolean function 𝑌 = (𝐴' + 𝐵)(𝐵 + 𝐶 )using fundamental logic
gates, and validate the correctness of the implementation through truth table analysis.
i. Design and implement a MOD-10 ripple counter using JK flip-flop, and verify its counting
sequence.
ii. Experimentally verify De Morgan’s Laws using basic logic gates and confirm the equivalence
through truth table validation.
i. Design and implement a 4-bit adder–subtractor circuit using the IC 7483, and demonstrate its
capability to perform both binary addition and subtraction operations.
ii. Design and implement a 4-to-2 encoder using fundamental digital logic gates, and verify its
operation by encoding four input lines into a two-bit binary output.
i. Design and implement a 4-bit Excess-3 to BCD code converter using appropriate digital logic
circuitry, and verify the accuracy of the conversion for all valid Excess-3 inputs.
ii. Verify De Morgan’s Laws using fundamental logic gates and demonstrate the logical
equivalence through experimental validation.

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