Digital Logic Design

Chapter 6
Counters
By
Dagnachew M.

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 Counters
▪ Counters are circuits that cycle through a specified number of states.
A Counter is constructed from two or more flip-flops which change
states in a prescribed sequence when input pulses are received.

▪ Two types of counters:

❖ synchronous (parallel) counters

❖ asynchronous (ripple) counters

▪ Ripple counters allow some flip-flop outputs to be used as a source

of clock for other flip-flops.

▪ Synchronous counters apply the same clock to all flip-flops.

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 1. Asynchronous (Ripple)
Counters
▪ Asynchronous counters: the flip-flops do not change states at exactly
the same time as they do not have a common clock pulse.

▪ Also known as ripple counters, as the input clock pulse “ripples”

through the counter – cumulative delay is a drawback.

▪ n flip-flops → a MOD (modulus) 2n counter.

▪ (Note: A MOD-x counter cycles through x states.)
▪ Output of the last flip-flop (MSB) divides the input clock frequency by
the MOD number of the counter, hence a counter is also a frequency
divider.
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Asynchronous (Ripple) Counters
▪ Example: 2-bit ripple binary counter.

▪ Output of one flip-flop is connected to the clock input of the next

more-significant flip-flop.
HIGH

J Q0 J Q1
CLK C C
Q0
K K

FF0 FF1
CLK 1 2 3 4

Q0

Timing diagram
Q0 0 1 0 1 0
00 → 01 → 10 → 11 → 00 ...
Q1 0 0 1 1 0
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Asynchronous (Ripple) Counters
▪ Example: 3-bit ripple binary counter.

HIGH

J Q0 J Q1 J Q2
CLK C Q0 C Q1 C
K K K
FF0 FF1 FF2

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2 0 0 0 0 1 1 1 1 0

Recycles back to 0 5
Asynchronous (Ripple) Counters
▪ Example: 4-bit ripple binary counter (negative-edge triggered).

HIGH
Q0 Q1 Q2 Q3
J J J J
CLK C C C C
K K K K
FF0 FF1 FF2 FF3

CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Q0

Q1

Q2

Q3 6
 n
Asyn. Counters with MOD no. < 2
▪ States may be skipped resulting in a truncated sequence.
▪ Technique: force counter to recycle before going through
all of the states in the binary sequence.
▪ Example: Given the following circuit, determine the
counting sequence (and hence the modulus no.)

C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs Q K Q K Q K
CLR CLR CLR
are 1
(HIGH). B
C

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 n
Asyn. Counters with MOD no. < 2
▪ Example (cont’d):
C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs Q K Q K Q K
CLR CLR CLR
are 1
(HIGH). B
C

1 2 3 4 5 6 7 8 9 10 11 12
Clock MOD-6 counter
A produced by
clearing (a MOD-8
B
binary counter)
C when count of six
NAND 1 (110) occurs.
Output 0

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 n
Asyn. Counters with MOD no. < 2
▪ BCD counters are counters with 10 states (modulus-10) in their sequence.
They are commonly used in daily life (e.g.: utility meters, odometers, etc.).

▪ Design an asynchronous decade counter.

(A.C)'

HIGH
D C B A
J Q J Q J Q J Q

CLK C C C C
K K K K
CLR CLR CLR CLR

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 n
Asyn. Counters with MOD no. < 2
▪ Example (cont’d): Counting sequence of circuit (in
CBA order).
1 2 3 4 5 6 7 8 9 10 11 12
Clock
A 0 1 0 1 0 1 0 1
0 0 1 1 0 0 0 0
B
0 0 0 0 1 1 0 0
C
NAND 1
Output 0

111 000
Temporary 001
state
Counter is a MOD-6
110 010 counter.

101 011
100

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 Asynchronous Down Counters
▪ So far we are dealing with up counters. Down counters, on the other
hand, count downward from a maximum value to zero, and repeat.

▪ Example: A 3-bit binary (MOD-23) down counter.

J Q
Q0 J Q
Q1 J Q
Q2
3-bit binary
CLK C C C up counter
Q' K Q' K Q'
K

J Q
Q0 J Q
Q1 J Q
Q2
3-bit binary
CLK C C C down counter
Q' K Q' K Q'
K

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2. Synchronous (Parallel) Counters
▪ Synchronous (parallel) counters: the flip-flops are clocked at the same time by
a common clock pulse.

▪ We can design these counters using the sequential logic design process.
▪ Example: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops
with identical J,K inputs).

Present Next Flip-flop

state state inputs
00 01
A1 A0 A1+ A0+ TA1 TA0
0 0 0 1 0 1
11 10 0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1

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 Synchronous Counters…
▪ Example: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical
J,K inputs).
Present Next Flip-flop
state state inputs
A1 A0 A1+ A0+ TA1 TA0 TA1 = A0
0 0 0 1 0 1
0 1 1 0 1 1 TA0 = 1
1 0 1 1 0 1
1 1 0 0 1 1

A0 J A1
J Q Q
C C
Q' K Q'
K

CLK

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Synchronous (Parallel) Counters
▪ Example: 3-bit synchronous binary counter (using T flip-flops, or JK flip-flops with
identical J, K inputs).

Present Next Flip-flop

state state inputs
A2 A1 A0 A2+ A1+ A0+ TA2 TA1 TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
A1 A1 A1

1 1 1 1 1 1 1
A2 1 A2 1 1 A2 1 1 1 1

A0 A0 A0
TA2 = A1.A0 TA1 = A0 TA0 = 1

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 Synchronous Counters…
▪ Example: 3-bit synchronous binary counter (cont’d).
TA2 = A1.A0 TA1 = A0 TA0 = 1

A2 A1 A0

Q Q Q
J K J K J K
CP
1

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 Synchronous Counters…
▪ Example: 4-bit synchronous binary counter.
TA3 = A2 . A1 . A0
TA2 = A1 . A0
TA1 = A0
TA0 = 1

1 A1.A0 A2.A1.A0

A0 J A1 J A2 J A3
J Q Q Q Q
C C C C
Q' K Q' K Q' K Q'
K

CLK

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 Synchronous Counters…
▪ Example: Synchronous decade/BCD counter.
Clock pulse Q3 Q2 Q1 Q0
Initially 0 0 0 0
1 0 0 0 1 T0 = 1
2 0 0 1 0
3 0 0 1 1 T1 = Q3'.Q0
4 0 1 0 0
5 0 1 0 1 T2 = Q1.Q0
6 0 1 1 0
7 0 1 1 1 T3 = Q2.Q1.Q0 + Q3.Q0
8 1 0 0 0
9 1 0 0 1
10 (recycle) 0 0 0 0

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Synchronous (Parallel) Counters
▪ Example: Synchronous decade/BCD counter
(cont’d).

T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q1.Q0 + Q3.Q0

Q0

1 T T Q1 T Q2 T Q3
Q Q Q Q
C C C C
Q' Q' Q' Q'

CLK

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Up/Down Synchronous Counters
▪ Up/down synchronous counter: a bidirectional
counter that is capable of counting either up or
down.

▪ An input (control) line Up/Down (or simply Up)

specifies the direction of counting.

❖Up/Down = 1 → Count upward

❖Up/Down = 0 → Count downward 19

Up/Down Synchronous Counters
▪ Example: A 3-bit up/down synchronous binary counter.
Clock pulse Up Q2 Q1 Q0 Down
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

TQ0 = 1 Up counter Down

TQ0 = 1 counter
TQ1 = ([Link]) + (Q0'.Up' )
TQ1 = Q0 TQ0 = 1
TQ2 = ( [Link] ) + (Q0'. Q1'. Up' )
TQ2 = Q0.Q1 TQ1 = Q0’
TQ2 = Q0’.Q1’
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 Up/Down Synchronous Counters
▪ Example: A 3-bit up/down synchronous binary counter
(cont’d). TQ0 = 1
TQ1 = ([Link]) + (Q0'.Up' )
TQ2 = ( [Link] ) + (Q0'. Q1'. Up' )

Q0 Q1

1 T T T Q2
Q Q Q
Up C C C
Q' Q' Q'

CLK

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Designing Synchronous Counters
Example: A 3-bit Gray code counter (using JK flip-flops).

Present Next Flip-flop 000

100 001
state state inputs
Q2 Q1 Q0 Q2+ Q1+ Q0+ JQ2 KQ2 JQ1 KQ1 JQ0 KQ0
0 0 0 0 0 1 0 X 0 X 1 X 101 011
0 0 1 0 1 1 0 X 1 X X 0
0 1 0 1 1 0 1 X X 0 0 X 111 010
0 1 1 0 1 0 0 X X 0 X 1 110
1 0 0 0 0 0 X 1 0 X 0 X
1 0 1 1 0 0 X 0 0 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 1 X 0 X 1 X 0

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Designing Synchronous Counters
▪ 3-bit Gray code counter: flip-flop inputs.

Q1Q0 Q1Q0 Q 1Q 0
Q2 Q2 00 01 11 10 Q2 00 01 11 10
00 01 11 10
0 0 1 X X 0 1 X X
1
1 X X X X 1 X X 1 X X 1

JQ2 = Q1.Q0' JQ1 = Q2'.Q0 JQ0 = Q2.Q1 + Q2'.Q1'

= (Q2  Q1)'
Q1Q0 Q1Q0 Q1Q0
Q2 00 01 11 10 Q2 00 01 11 10 Q2 00 01 11 10
0 X X X X 0 X X 0 X 1 X
1 1 1 X X 1 1 X 1 X
KQ2 = Q1'.Q0' KQ1 = Q2.Q0 KQ0 = Q2.Q1' + Q2'.Q1
= Q2  Q1

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Designing Synchronous Counters
▪ 3-bit Gray code counter: logic diagram.
JQ2 = Q1.Q0' JQ1 = Q2'.Q0 JQ0 = (Q2  Q1)'
KQ2 = Q1'.Q0' KQ1 = Q2.Q0 KQ0 = Q2  Q1

Q0 Q1 Q2
J Q J Q J Q
C C C
Q1 Q2
K Q' K Q' ' K Q' '
Q0
'
CLK

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 Exercise
1. Design 3 bit up down synchronous binary counter using

A. T flip flop

B. D flip flop

C. J K flip flop
1. Design random synchronous counter that count
1,3,5,7and 9 respectively Using jk flip flop .

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