Part 1: Fundamentals & Standard Strategies
Section 1: Fundamentals & Volt-Second Balance
1. Volt-Second Calculation: You are using a converter with a DC link voltage (Vdc) of
400V. You need to synthesize a reference voltage (Vref) of 260V over a switching
period (Tsw) of 100 µs using two available levels: 0V and +Vdc. Calculate the
required durations for t1 (at 0V) and t2 (at +Vdc) to maintain volt-second balance.
2. Nearest Level Control (NLC): In a 5-level inverter with available pole voltage levels
of 2Vdc, Vdc, 0, -Vdc, and -2Vdc, a reference signal requires an instantaneous
voltage of 1.3Vdc. Identify the two nearest voltage levels the controller should switch
between and explain why switching between 0V and 2Vdc would be less ideal.
Section 2: Carrier-Based PWM Strategies
1. LS-PWM Disposition: What are the three types of LS-PWM dispositions? Draw the
carriers in one switching period for 9-level operation. Between In-Phase Disposition
(IPD) and Alternative Phase Opposite Disposition (APOD) which one is generally
preferred for achieving the best Total Harmonic Distortion (THD), and which is
typically used specifically to reduce Common Mode Noise?
2. PS-PWM Frequency Doubling: A Cascaded H-Bridge (CHB) inverter uses 3 cells
per phase. If the carrier frequency (f_cr) for each individual cell is 2 kHz, calculate
the effective switching frequency seen in the multilevel output waveform.
3. Topology Suitability: You are designing a control scheme for a Neutral Point
Clamped (NPC) inverter. Explain why Level-Shifted PWM (LS-PWM) is more
inherently suitable for this topology compared to a standard Cascaded H-Bridge. Can
you use LSPWM to operate a CHB topology?
4. Source Utilization: In a Cascaded H-Bridge converter, why does using Phase-
Shifted PWM (PS-PWM) result in better thermal management and longevity of the
DC sources compared to using Level-Shifted PWM?
Section 3: Common Mode Injection (CMI)
1. Line-to-Line Invariance: Prove mathematically that adding a common mode voltage
(Vcm) to all three phase-reference waveforms (Va, Vb, Vc) does not affect the actual
line-to-line voltage (Vab) seen by the load.
2. Third-Harmonic Injection: If the fundamental peak of a sine wave is 1.0
(normalized to the carrier peak), and you inject a third harmonic at 1/6 the magnitude
of the fundamental, can you draw the resulting sine waves, the common mode signal
and the resulting waveforms for one fundamental period?
3. Kim-Sul Algorithm (Min-Max): Given instantaneous three-phase reference voltages
Va, Vb, and Vc, use the Kim-Sul formula to calculate the optimum offset voltage
(V_offset) that should be subtracted from all phases to ensure maximum DC bus
utilization. Can you draw the resulting sine waves, the common mode signal and the
resulting waveforms for one fundamental period?
Section 4: Implementation & Safety
1. Complementary Pairs: In a 3-level NPC leg consisting of switches S1, S2, S3, and
S4 (ordered top to bottom), identify the two complementary switch pairs.
Part 2: Advanced Analysis & Waveform Derivation
1. Phase-Shifted PWM Harmonic Analysis: For a 7-level Cascaded H-Bridge (CHB)
inverter how many full bridge cells are required per phase? Now for this converter:
Each cell has a carrier frequency of f_sw = 2 kHz. What is the effective switching
frequency of the output voltage. Draw the individual output voltages of the H-Bridge
cells (vo1, vo2, vo3) over two switching cycles, showing the specific phase shifts
between their switching instances.
2. Kim-Sul Algorithm Calculation: Given the following instantaneous fundamental
reference voltages: Va = 0.8, Vb = 0.4, Vc = -0.9, Assume the DC bus limits are +1
and -1. Calculate the exact V_offset required using the Min-Max (Kim-Sul) approach
to "center" these references within the DC bus.
3. Switching State Transitions & Dead-time: In a 3-level NPC leg, the voltage states
are 0, +Vdc/2, Vdc and state transitions from 0 to Vdc involve specific switches.
Draw the gate signals (S1, S2, S3, S4) for a transition where the pole voltage moves
from 0 to +Vdc/2.
4. Volt-Second Balance in Sub-Cycles: A reference voltage Vref = 150V must be
synthesized using a 3-level inverter with available levels of 0V, 300V, and 600V. The
switching frequency is 10 kHz.
o Constraint: Due to a specific operational requirement, the 600V level must be
turned on for exactly 1/8th of the switching period in every cycle.
o Calculate the required "dwell times" for the 0V, 300V, and 600V levels within
a single period to maintain the average 150V output. Draw the resulting output
voltage, identify the various levels with time durations. What is the lowest
voltage level that can be realized with this constraint?
5. Pulse generation: Draw the block diagram of a generic pulse generation scheme for
any multilevel topology using pulse summation concept. Consider the case of a 5-
level inverter. If one has to operate a 3-level NPC leg by directly giving the pulses
generated from comparison with the carrier draw its block diagram clearly identifying
the pulse generated from the top carrier and bottom carrier.
6. Hybrid topology: Draw the hybrid topology of an NPC and cascaded MLI. What is
the preferred PWM scheme (LSPWM, PSPWM or anything elese). For a 5-level
operation of this topology, draw the carriers for one switching period.