Digital logic Design

Chapter Five
Sequential Logic Circuit

by
Dagnachew M.
Email: dagnu1522@[Link]

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 Sequential Logic Circuit
➢ The logic circuits whose outputs at any instant of time depend on the present
inputs as well as on the past outputs are called sequential circuits.
➢ In sequential circuits, the output signals are fed back to the input side.
➢ A memory element is a medium in which one bit of information (0 or 1) can
be stored. or retained until necessary, and thereafter its contents can be
replaced by a new value.
The contents of memory elements can be changed by the outputs of
combinational circuits
that are connected to its input

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 Sequential Circuits

 Asynchronous
Inputs Outputs
Combinational
Circuit
Memory
Elements

 Synchronous
Inputs Outputs
Combinational
Circuit
Flip-flops
Clock

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 Latches and Flip-Flop
➢
3 Basic 1-bit digital memory circuit is known as a flip flop.

➢ It can have only two states, either the 1 state or the 0 state.

➢ A flip-flop is also known as a bistable multi vibrator.

➢ Flip-flops can be obtained by using NAND or NOR gates.

➢ Flip-flop is It has one or more inputs and two outputs.

➢ The two outputs are complementary to each other.

 Latches and Flip-Flop…. .
➢ Q and Q' cannot be at the same state simultaneously.
➢ If it happens by any chance, it violates the definition of a flip-flop
and hence is called an undefined condition.
➢ The state of Q is called the state of the flip-flop, whereas the
state of Q' is called the complementary state of the flip-flop.
➢ Latch are basically similar to flip-flop.
➢ The difference between latch and flip-flop is in the method used
for changing their state.

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 Latches

 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0

R
0 0
Q

S Q
0 1

Initial Value

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 Latches

 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0

R
0 1
Q

S Q
0 0

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 Latches

 SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R
1 0
Q

S Q
0 1

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 Latches

 SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R
1 1 0 1 1 0 1 Q=0
Q

S Q
0 0

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 Latches

 SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
0 0 0 1 1 0 1
Q=0
Q 1 0 0 1 0 Q=1

S Q
1 1

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 Latches

 SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
0 1 0 1 1 0 1
Q=0
Q 1 0 0 1 0 Q=1
1 0 1 1 0 Q=1

S Q
1 0

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 Latches

 SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
1 0 0 1 1 0 1
Q=0
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’

S Q
1 10

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 Latches

 SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
1 10 0 1 1 0 1
Q=0
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0 Q = Q’
S Q
1 0

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 Latches

 SR Latch
S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S R Q
Q Invalid
0 0 Q=Q’=1
0 1 1 Set
1 0 0 Reset
R Q
1 1 Q0 No change
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 Latches

 SR Latch
S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S’ R’ Q
Q No change
1 1 Q0
1 0 0 Reset
Q 0 1 1 Set
R Q=Q’=1 Invalid
0 0
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 Controlled Latches

 SR Latch with Control Input

R R S S
Q Q
C C
S Q R Q
S R

C S R Q
0 x x Q0 No change
1 0 0 Q0 No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q=Q’ Invalid
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 Controlled Latches

 D Latch (D = Data) Timing Diagram

S
C
D
Q
C D
R Q
Q

t
C D Q
Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set

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 Controlled Latches

 D Latch (D = Data) Timing Diagram

S
C
D
Q
C D
R Q
Q

C D Q Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set

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 The difference between latch and flip flop

 Controlled latches are level-triggered

 Flip-Flops are edge-triggered

CLK Positive Edge

CLK Negative Edge

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 Flip-Flops
Master-Slave D Flip-Flop

 The construction of a D flip-flop with two D latches and an inverter is

shown in Fig. below
The first latch is called the master and the second the slave.

 When the clock is 0, the output of the inverter is 1. The slave latch is
enabled, and its output Q is equal to the master outputY . The master latch
is disabled because Clk = 0.

 When the input pulse changes to the logic-1 level, the data
from the external D input are transferred to the master. The slave,
however, is disabled as long as the clock remains at the 1 level, because its
enable input is equal to 0.
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 Flip-Flops

 Master-Slave D Flip-Flop
D D Q D Q Q
D Latch D Latch
(Master) (Slave)
C C

Master Slave
CLK
CLK

D
Looks like it is negative
edge-triggered QMaster

QSlave
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 Flip-Flops

Characteristic equation of a D flip-flop is

C D Q

0 x Q0 Q(t+1) = D.
1 0 0
1 1 1

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 Flip-Flops

 JK Flip-Flop

J
D Q Q
K
CLK Q Q

J Q
D = JQ’ + K’Q
K Q
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 Flip-Flops

 T Flip-Flop

T J Q T D Q

Q
K Q

T Q
D = JQ’ + K’Q
D = TQ’ + T’Q = T  Q Q

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Flip-Flop Characteristic Tables

D Q D Q(t+1)
0 0 Reset
Q 1 1 Set

J K Q(t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset
K Q 1 0 1 Set
1 1 Q’(t) Toggle

T Q T Q(t+1)
0 Q(t) No change
Q
1 Q’(t) Toggle
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Flip-Flop Characteristic Equations

D Q D Q(t+1)
0 0 Q(t+1) = D
Q 1 1

J K Q(t+1)
J Q 0 0 Q(t)
0 1 0 Q(t+1) = JQ’ + K’Q
K Q 1 0 1
1 1 Q’(t)

T Q T Q(t+1)
0 Q(t) Q(t+1) = T  Q
Q
1 Q’(t)
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 Flip-Flop Characteristic Equations

 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 Reset
0 1 1
K Q
1 0 0 Set
1 0 1
1 1 0 Toggle
1 1 1

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 Flip-Flop Characteristic Equations

 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 0 Reset
0 1 1 0
K Q
1 0 0 Set
1 0 1
1 1 0 Toggle
1 1 1

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 Flip-Flop Characteristic Equations

 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 0 Reset
0 1 1 0
K Q
1 0 0 1 Set
1 0 1 1
1 1 0 Toggle
1 1 1

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 Flip-Flop Characteristic Equations

 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 0 Reset
0 1 1 0
K Q
1 0 0 1 Set
1 0 1 1
1 1 0 1 Toggle
1 1 1 0

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 Flip-Flop Characteristic Equations

 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
J Q 0 0 1 1 K
0 1 0 0 0 1 0 0
0 1 1 0 J 1 1 0 1
K Q Q
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Q(t+1) = JQ’ + K’Q

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Excitation Table of a Flip-Flop

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 INTERCONVERSION OF FLIP-FLOPS

➢ In many applications, we are being given a type of flip-flop, whereas we may

require some other type.

➢ To design the conversion logic we need to combine the excitation table

for both flip-flops and make a truth table with data input(s) and Q as the

inputs and the input(s) of the given flip-flop as the output(s)

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 Example 1

Convert S-R Flip-flop to D Flip-flop

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Example 2 Convert S-R Flip-flop to a J-K Flip-flop

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Example 3 Convert S-R Flip-flop to a T Flip-flop

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 Exercise
1. Convert D Flip-flop to an S-R, to J-K and to T Flip-flop

2. Convert J-K Flip-flop to a D and T Flip-flop

3. Convert T Flip-flop to an S-R, to J-K and to D Flip-flop

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