VLSI-Module4

Shareefa Fairoose P.

February 2026

Static CMOS Full Adder

Basic Logic Equations of full adder outputs S and Co are:

S = A ⊕ B ⊕ Ci

Co = AB + BCi + ACi

The carry expression can be rewritten as:

Co = AB + Ci (A + B)

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Generate, Propagate and Delete Concepts
For faster carry analysis, the full adder is described using three signals:

• Generate (G):
G = AB
When both A and B are 1, the circuit generates a carry independent of Ci .
• Propagate (P):
P =A⊕B
If P = 1, the input carry Ci is propagated to the output.
• Delete (D):
D = AB
When both inputs are 0, any incoming carry is deleted.

Using G and P, the carry output becomes:

Co = G + P C i

The sum can be written as:

S = P ⊕ Ci

Static CMOS Implementation of Full Adder

Figure 1: Complimentary Static CMOS Full Adder

One way to implement a Full Adder is:

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 • Take the Boolean logic equations.

• Directly translate them into complementary CMOS circuits.

• The logic expressions are often reorganized to reduce transistor count.

• Example for such a reorganized equation is as follows:

Co = AB + Ci (A + B)

S = ABCi + Co (A + B + Ci )
Corresponding adder design using complementary static cmos is shown in fig 1

Ripple Carry Adder

Figure 2: ripple carry adder showing critical path

A Ripple Carry Adder (RCA) is one of the simplest and most commonly used digital
adders. It is constructed by cascading multiple Full Adders (FA) to add multi-bit binary
numbers.
For an N -bit addition:

• Each stage consists of one Full Adder.

• The carry output of one stage becomes the carry input of the next stage.

• The carry propagates (ripples) from LSB to MSB.

Delay Analysis of Ripple Carry Adder

The main disadvantage of the RCA is its delay.

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Worst Case Delay

The worst-case delay occurs when the carry propagates through all stages.

td = O(N )

More precisely,

tadder = (N − 1)tcarry + tsum

where:

• tcarry = propagation delay from Ci to Co

• tsum = propagation delay from Ci to S

Important Observation

• The carry path dominates the delay.

• Optimizing tcarry is more important than optimizing tsum .

Design Goal: Make the carry propagation path as fast as possible.

Circuit Optimization Concept

To improve speed:

• Place NMOS and PMOS transistors connected to Ci as close as possible to the

output.

• Reduce unnecessary inverting stages in the carry path.

Reducing the number of inverters reduces propagation delay.

Inversion Property
No of inverting stages in the carry path can be reduced by exploiting the inverting prop-
erty (inverting all the inputs of full adder cell also inverts all the outputs )

S(A, B, Ci ) = S(A, B, Ci )

Co (A, B, Ci ) = Co (A, B, Ci )

This property helps reduce the number of inverting stages in the carry chain.

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 Figure 3: inversion property

Figure 4: Minimize critical path by reducing inverting stages

Reducing Critical Path Using Inversion Property

Alternating normal and inverting full adders helps reduce carry path delay by eliminating
extra inversion stages.

Better Full Adder Structures

• The Mirror Adder design-24 transistors

• Transmission-Gate Full Adder-24 transistors

• Manchester Carry-Chain Adder

Manchester Carry-Chain Adder

The Manchester Carry-Chain Adder is an improved carry propagation structure designed
to reduce the delay of conventional ripple carry adders.
Instead of allowing the carry to ripple through full adders, this structure directly prop-
agates the carry using Generate (G), Propagate (P), and sometimes Delete (D)
signals.

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Basic Carry Equation
For a single bit position:

Co = Gi + Pi Ci

where

Gi = Ai Bi (Carry Generate)

Pi = Ai ⊕ Bi (Carry Propagate)

Interpretation:

• If Gi = 1, carry is generated regardless of Ci .

• If Pi = 1, input carry Ci is propagated to output as Co .

• If neither condition holds, carry is suppressed.

Static Manchester Carry Stage

Figure 5: Static manchester carry stage

In the static implementation:

• Transmission gate controlled by Pi connects Ci to Co .

• Pull-up network controlled by Gi .

• Pull-down network controlled by Delete signal Di .

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The carry output equation becomes:

Co = (Pi Ci + Gi )Di

1. If Pi = 1, input carry Ci is passed to output.

2. If Gi = 1, output is pulled high.

3. If delete condition Di = 1, output is pulled low.

Advantages of Static Manchester Stage

• Reduces number of logic levels.

• Faster than ripple carry structure.

• Improves carry-lookahead efficiency.

• Full voltage swing (robust operation).

Dynamic Manchester Carry Stage

Figure 6: Dynamic Manchester carry stage

To further improve speed, a dynamic logic implementation is used.

Key Modifications

• Transmission gate replaced by NMOS pass transistor.

• Clock signal ϕ controls operation.

• Uses precharge and evaluation phases.

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Operation Phases

1. Precharge Phase (ϕ = 0)

• Output node is precharged to logic 1.

• PMOS precharge transistor is ON.

• NMOS pull-down network is OFF.

ϕ = 0, Co = 1

2. Evaluation Phase (ϕ = 1)

• Precharge transistor turns OFF.

• Pull-down network activates.

• Output may discharge conditionally.

ϕ = 1, Co = Pi Ci + Gi

Dynamic Operation Cases

• If Gi = 1 (Generate condition), output node discharges.

• If Pi = 1 (Propagate condition), previous carry conditionally discharges the node.

• If neither condition is true, output remains precharged.

Why Manchester Carry is Faster

Compared to Ripple Carry Adder:

• Carry does not pass through complete full adder logic.

• Uses direct pass-transistor path.

• Fewer transistor stacks.

• Reduced capacitive loading.

Static version is robust and simpler. Dynamic version is faster but requires clocking.

The propagation delay of a Manchester Carry Chain adder can be approximated using
Elmore delay as

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 N (N + 1)
tp = 0.69 RC
2
where N is the number of stages, R is the effective resistance of each pass device, and C
is the capacitance at each internal node.

The Carry –bypass adder ( Carry-Skip Adder)

Figure 7: Carry bypass adder

The Carry–Bypass Adder (also called Carry–Skip Adder) is an improvement over the Rip-
ple Carry Adder (RCA). In a Ripple Carry Adder, the carry must propagate sequentially
through each full adder, which increases delay for large word sizes. The Carry–Bypass
Adder improves speed by skipping over blocks where carry propagation is guaranteed.
Consider a 4-bit adder block consisting of four Full Adders (FA).
For each bit position k:

Pk = Ak ⊕ Bk (Propagate)
Gk = Ak Bk (Generate)

Carry equation of a full adder:

Ck+1 = Gk + Pk Ck

Block Propagate Condition

For a 4-bit block, define the Block Propagate signal:

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 BP = P0 · P1 · P2 · P3

If all propagate signals are HIGH, then the input carry Ci,0 will be bypassed to output
as in Figure 7. using a multiplexer.

BP = 1 ⇒ Co,3 = Ci,0

Otherwise, the carry is determined normally by ripple through the block as in a ripple
carry adder:

Co,3 = C3

Thus,
(
Cin , if BP = 1
Cout =
C3 , otherwise

Advantages
• Faster than Ripple Carry Adder.

• Simple hardware implementation.

• Suitable for medium-speed arithmetic units.

Limitations
• Slightly more hardware than Ripple carry adder.

• Delay improvement depends on block size.

The Carry–Bypass Adder reduces carry propagation delay by allowing the carry to skip
over blocks when all propagate conditions are satisfied. It offers a good trade-off between
speed and hardware complexity.

Carry bypass in manchester carry chain adder

• The carry propagate either through the bypass path or a carry is generated in some
where in the chain as shown in fig.8.

• carry propagation is realized using pass-transistor logic, which makes the carry
chain faster and more compact.

• In a carry-bypass adder, the carry either ripples within a small block or skips
blocks using bypass logic, thus reducing worst-case delay compared to a normal
ripple configuration.

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 Figure 8: Manchester carry chain implementation of bypass adder

N-bit Adder: Carry Skip adder - Delay estimation

Figure 9: Carry skip adder with 4-bit block size

• For computing delay of an N-bit adder

• First assume the total adder is divided in to (N/M)equal-length bypass stages,each

of which contains M bits. (Eg. in Fig.9., N=16 and M=4).

• Worst-case delay → carry from bit 0 to bit 15 = carry generated in bit 0, ripples
N


through bits 1, 2, and 3, skips the middle two groups M − 2 , ripples in the last
group from bit 12 to bit 15.

Total Propagation time can be derived from the above figure and is given by
 
N
td = tsetup + M tcarry + − 1 tbypass + (M − 1)tcarry + tsum
M

• tsetup : the fixed overhead time to create the generate and propagate signals

• tcarry : the propagation delay through a single bit

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 • tbypass : the propagation delay through the bypass multiplexer of a single stage

• tsum : the time to generate the sum of the final stage

Comparison between Ripple Carry Adder (RCA) and Carry By-

pass Adder (CBA)

Figure 10: Carry Ripple vs Carry Bypass Adder

In a Ripple Carry Adder, delay increases linearly with N because the carry must propa-
gate through every bit stage.

tp ∝ N

Hence, its slope is steep.

In a Carry Bypass Adder, carry can skip (bypass) groups of bits when propagate con-
ditions are satisfied. This reduces the overall delay growth rate, so the slope is more
gradual compared to ripple carry.

The Linear Carry Select adder

In a Ripple Carry Adder (RCA), each full adder must wait for the incoming carry
before producing its output carry. This increases the overall delay because the carry
ripples sequentially through all bits.
To reduce this delay, the Carry Select Adder (CSA) is used. Instead of waiting for
the actual carry input:

• Each block computes two possible results in parallel:

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 – One assuming carry-in = 0
– One assuming carry-in = 1

• When the real carry arrives, the correct result is selected using a multiplexer (MUX).

Thus, carry computation is partially completed in advance.

Working of Linear Carry Select Adder

• The adder is divided into equal-sized blocks.

• Each block contains M bits.

• Suppose a block adds bits k to k + 3 (example of 4-bit block).

• Two carry paths are implemented (for carry-in = 0 and carry-in = 1).

• When the actual carry Co,k−1 becomes available, the multiplexer selects the correct
output with minimal delay.

Compared to Ripple Carry Adder: One extra carry path is required and One multiplexer
per stage is required. Hardware overhead of Linear Carry Select Adder is approximately
30% more than ripple carry structure.

Structure
A full carry select adder is constructed by chaining multiple equal-length adder stages,
similar to the carry bypass approach. Critical path is shaded in gray.

Figure 11: Carry select adder

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Worst-Case Propagation Delay Model
The first-order delay model is:
 
N
tadd = tsetup + tmux + M tcarry + tsum
M

Where:

• tsetup = fixed setup delay

• tsum = sum generation delay
• tmux = multiplexer delay
• N = total number of bits
• M = number of bits per stage
• tcarry = delay of carry through one full adder
• Carry delay through one block:
= M tcarry

• Since there are N

M
blocks, overall delay is proportional to:
N
M
• Propagation delay is linearly proportional to N , but smaller than ripple carry adder.

The Linear Carry Select Adder improves speed by precomputing carry outputs for both
possible carry inputs and selecting the correct one using multiplexers. but with some
increase in hardware compared to RCA.

Square Root Carry Select Adder

In a Linear Carry Select Adder, all stages have equal block size. This creates a
mismatch in signal arrival times:

• Carry results from ripple chains become stable early.

• Multiplexer select signals arrive later.
• This increases the overall critical path delay.

To optimize the design, it is essential to identify the critical timing path.

For a 16-bit linear CSLA: Assume full adder delay= multiplexer delay = 1 unit. Worst-
case delay ripples through the first stage carry chain and then through the multiplexer
chain of subsequent stages.

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Concept of Square Root Carry Select
To reduce delay:

• Equalize the delay through carry path and multiplexer path.

• Increase block sizes progressively.

Instead of equal-sized blocks:

Stage sizes: M, (M + 1), (M + 2), . . .

Example: 1st stage → 2 bits, 2nd stage → 3 bits, 3rd stage → 4 bits, and so on. (Shown
in Fig 12). This gradually increases carry generation time to match multiplexer delay.

Figure 12: square root carry select adder

Mathematical Model
Total number of bits:

N = M + (M + 1) + (M + 2) + · · · + (M + (P − 1))

This simplifies to:

P2
 
1
N= +P M−
2 2

If M ≪ N , the first term dominates:

√
P ≈ 2N

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Delay Expression
For carry select:

√
tadd = tsetup + M tcarry + ( 2N )tmux + tsum
√
Since P ≈ 2N ,

√
tadd ∝ N

Key Results

Figure 13: Adder delays comparison

• Ripple Carry Adder → Delay ∝ N

• Linear Carry Select → Delay ∝ N (smaller slope)

√
• Square Root Carry Select → Delay ∝ N

Thus, for large N , delay of square root carry select adder increases much more slowly,
almost becomes a constant for large N.
The Square Root Carry Select Adder improves performance by:

• Increasing block sizes progressively

• Balancing carry and multiplexer delays

• Achieving sub-linear delay growth

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Multiplier

Figure 14: A multiplier architecture

• A binary multiplier is an electronic circuit used in digital electronics, such as a

computer, to multiply two binary numbers

• A variety of computer arithmetic techniques can be used to implement a digital

multiplier

• Most techniques involve computing a set of partial products, and then summing
the partial products together.

• Partial product generation: The partial product array in Fig. 14 is generated

using AND gates.

• An n-bit by n-nit multiplier requires n2 AND gates for partial product generation

• Partial Product Accumulation: The partial products are then added to give
the final results.

• Each partial product is generated by multiplying the multiplicand with a bit of

multiplier—is the AND operation— and shifting the result on the basis of the
multiplier bit position

• Partial product accumulation followed by a final addition to produce the final

result.

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Array multiplier
An array multiplier accepts the multiplier and multiplicant as inputs and uses an array
of cells to calculate the bit product xi · yj individually in a parallel manner

Figure 15: Array Multiplier

n-bit × n-bit Array Multiplier

• An n-bit by n-bit multiplication requires:

– n2 AND gates,
– n(n − 2) full adders (FAs),
– n half adders (HAs).
• Due to the regular array organization, the determination of delay is not straight-
forward.
• In this structure, the partial product adders are implemented using ripple-carry
configurations.

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 Figure 16: Array Multiplier Block diagram

• For performance optimization, the critical timing path must first be identified.
• A large number of paths with identical delay can be observed in the array structure.
• The total propagation delay of the multiplier can be expressed as:
tmult = [(M − 1) + (N − 2)] tcarry + (N − 1)tsum + (N − 1)tAN D

• tcarry is the propagation delay between input and output carry, tsum is the delay
between input carry and sum bit of full adder, and tAN D is the delay of the AND
gate.
• Since all critical paths have the same length, improving only one path (for example,
by replacing one ripple-carry adder with a faster adder such as a carry-select adder)
will not significantly improve overall performance. Instead all critical paths must
be optimized simultaneously.

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• From the delay equation, minimization of tmult requires minimization of both tcarry
and tsum .

• It is often beneficial to design the circuit such that: tcarry ≈ tsum , for balanced
performance.

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