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Module 3-QB

The document outlines a series of questions related to the Computer Organization and Architecture course for B.Tech students at Vimal Jyothi Engineering College. It covers topics such as memory hierarchy, cache memory, mapping techniques, block replacement policies, and virtual memory concepts. Each question is categorized by its module, submodule, and complexity level, with references to specific pages in the course textbook.

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4 views5 pages

Module 3-QB

The document outlines a series of questions related to the Computer Organization and Architecture course for B.Tech students at Vimal Jyothi Engineering College. It covers topics such as memory hierarchy, cache memory, mapping techniques, block replacement policies, and virtual memory concepts. Each question is categorized by its module, submodule, and complexity level, with references to specific pages in the course textbook.

Uploaded by

ajalsmart4
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Vimal Jyothi Engineering College

(Autonomous)
DEPARTMENT OF
IVth Semester - [Link]
Course : PBCST404 - COMPUTER ORGANIZATION AND
ARCHITECTURE

QNo QUESTION CO MARK


Module 3
Submodule 1
Topic 1

1. Define memory hierarchy. Explain its organization with a neat diagram and discuss its

significance. CO3 (6.00)


( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Question Paper ) (Computer Organization and
Architecture Designing for Performance, page: 113-115 )

2. Define the memory hierarchy and explain how it balances the trade-offs between cost,

capacity, and access time. CO3 (6.00)


( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, page: 113-115 )

3. Define Average Memory Access Time (AMAT). Show how AMAT is affected by hit time,

miss rate, and miss penalty in a two-level memory system. Calculate AMAT for a system
CO3 (6.00)
where L1 hit time is 5 ns, miss rate is 4%, and miss penalty is 50 ns.
( Theory ) ( Applying(P) ) ( Hard ) (Ref : Book ) (Computer Organization and Architecture Designing for
Performance, page: 155 )

4. In what ways does the memory hierarchy contribute to higher performance in a computer
CO3 (2.00)
system?
( Theory ) ( Understanding(U) ) ( Easy ) (Ref : Book ) (Text 2 104-108 )

5. What is the general relationship among access time, memory cost, and capacity?
CO3 (2.00)
( Theory ) ( Understanding(U) ) ( Easy ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, Page: 146-148 )

6. Describe any four key characteristics of the memory system.


CO3 (2.00)
( Theory ) ( Remembering(R) ) ( Easy ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, Page: 146-148 )
Submodule 2

7. How do the various mapping techniques present in cache memory differ from each other?
CO3 (6.00)
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, page: 124-130 )

8. What is locality of reference? Explain temporal locality and spatial locality with suitable

program examples. CO3 (6.00)


( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, page: 146 )

9. Explain how instruction execution exhibits locality of reference. Discuss how loops,

procedure calls, and arrays contribute to locality. CO3 (6.00)


( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, page: 146 )

Topic 1

1 of 5
10. What are the three address fields used in cache mapping? How do they differ in different

cache mapping techniques? CO3 (2.00)


( Theory ) ( Remembering(R) ) ( Medium ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, Page: 124-130 )

11. Explain why cache memory is faster than main memory.


CO3 (2.00)
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, page: 104-108 )

12. What is the distinction between spatial locality and temporal locality?
CO3 (2.00)
( Theory ) ( Remembering(R) ) ( Easy ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, Page: 150-152 )
Submodule 3
Topic 1

13. A computer system uses a cache of 256 blocks, each block containing 8 words. The main

memory has 8192 blocks and is addressed using 16-bit word addresses.

a) Determine and show the address format for direct mapping. (3 marks) CO3 (6.00)

b) Determine and show the address format for 8-way set associative mapping. (3 marks)
( Theory ) ( Applying(P) ) ( Hard ) (Ref : Book ) (Computer Organization and Architecture Designing for
Performance, page: 148 )

14. A cache memory has 64 blocks, each block contains 8 words. Main memory is word-
addressable with a 14-bit address, and it has 2048 blocks. Clearly label tag, index (or set),

and word offset bits.


Show the format of the main memory address for: CO3 (6.00)

a) Direct mapping. (3 marks)


b) 4-way set associative mapping. (3 marks)
( Theory ) ( Applying(P) ) ( Hard ) (Ref : Book ) (Computer Organization and Architecture Designing for
Performance, page: 148 )

15. Consider a cache consisting of 128 blocks of 16 words each, for a total of 2k words, and

assume that the main memory is addressable by a 16-bit address and it consists of 4k
blocks. Show the format of the main memory address in the following mapping

techniques: CO3 (6.00)

a) Direct mapping. (3 marks)

b) 2-way set associative mapping. (3 marks)


( Theory ) ( Applying(P) ) ( Hard ) (Ref : Book ) (Computer Organization and Architecture Designing for
Performance, page: 148 )

16. A computer system uses a 32-bit memory address. The cache size is 64 KB, the block
size is 64 bytes, and the cache follows an 8-way set-associative mapping. Determine the
CO3 (2.00)
number of cache lines and number of sets in the cache.
( Theory ) ( Applying(P) ) ( Hard ) (Ref : Book ) (Computer Organization and Architecture Designing for
Performance, Page: 148 )

17. A computer system has a main memory of 32 KB and a cache memory of 4 KB. The block
size is 64 bytes. Determine the number of cache lines and the size of the memory
CO3 (2.00)
address.
( Theory ) ( Applying(P) ) ( Hard ) (Ref : Book ) (Computer Organization and Architecture Designing for
Performance, Page: 148 )
2 of 5
18. A computer system has a main memory of 64 KB and a cache memory of 8 KB. The block

size is 32 bytes. Determine the number of cache lines and the number of main memory
CO3 (2.00)
blocks.
( Theory ) ( Applying(P) ) ( Hard ) (Ref : Book ) (Computer Organization and Architecture Designing for
Performance, Page: 148 )
Submodule 4
Topic 1

19. Describe optimal block replacement policy. A cache memory with 4 lines uses the optimal

replacement policy. Determine the hit rate and miss rate for the given reference string:
A, B, C, D, A, E, B, C, D, A, A, B, C, D, C, C
CO3 (6.00)
Show the cache status for each reference.

( Theory ) ( Applying(P) ) ( Hard ) (Ref : Book ) (Computer Organization and Architecture Designing for
Performance, page: 136 )

20. Describe LRU block replacement policy. A cache memory with 4 lines uses the LRU

replacement policy. Determine the hit rate and miss rate for the given reference string:
A, B, C, D, A, E, B, C, D, A, A, B, C, D, C, C
CO3 (6.00)
Show the cache status for each reference.

( Theory ) ( Applying(P) ) ( Hard ) (Ref : Book ) (Computer Organization and Architecture Designing for
Performance, page: 136 )

21. Describe FIFO (First In First Out) block replacement policy. A cache memory with 4 lines

uses the FIFO replacement policy and it follows a fully associative mapping mechanism.
Determine the hit rate and miss rate for the given reference string:

A, B, C, D, A, E, B, C, D, A, A, B, C, D, C, C CO3 (6.00)

Show the cache status for each reference.

( Theory ) ( Applying(P) ) ( Hard ) (Ref : Book ) (Computer Organization and Architecture Designing for
Performance, page: 136 )

22. Describe optimal block replacement algorithm with its pros and cons.
( Theory ) ( Remembering(R) ) ( Medium ) (Ref : Book ) (Computer Organization and Architecture CO3 (2.00)
Designing for Performance, Page:136 )

23. Compare FIFO and LRU replacement policies.


CO3 (2.00)
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, Page: 136 )

24. Why is block replacement not required in direct-mapped cache?


CO3 (2.00)
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, Page:124-130 )
Submodule 5
Topic 1

25. Explain how multi-level cache organization helps in balancing speed, cost, and capacity in
modern processors. CO3 (6.00)
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, page: 138-140 )

3 of 5
26. Compare single-level cache and multi-level cache architectures. Explain why multi-level
cache organization is preferred in modern processors. CO3 (6.00)
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, page: 138-140 )

27. Discuss the need for multiple-level caches in modern computer architectures. Explain
with a neat diagram. CO3 (6.00)
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, page: 138-140 )

28. Explain why multiple-level caches are used to reduce cache misses.
CO3 (2.00)
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Design : The
Hardware/Software Interface: RISC-V Edition 489-492 )

29. Explain why multilevel caches are preferred over a single-level cache.
CO3 (2.00)
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Design : The
Hardware/Software Interface: RISC-V Edition, pages: 489-492 )

30. How does L3 cache help in reducing cache misses?


CO3 (2.00)
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Design : The
Hardware/Software Interface: RISC-V Edition, pages: 489-492 )
Submodule 6
Topic 1

31. Explain the following combinations of update policies:

a) Write-Through with Write-Allocate. (2 marks)


b) Write-Through with No-Write-Allocate. (2 marks) CO3 (6.00)

c) Write-Back with Write-Allocate. (2 marks)


( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, page: 136-138 )

32. What is a write miss in cache memory? Discuss in detail the write-allocate and no-write-
allocate policies. CO3 (6.00)
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, page: 136-138 )

33. Describe the working of the Write-Through cache policy. Explain how write operations are
handled in this policy and list its advantages and disadvantages. CO3 (6.00)
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, 136-138 )

34. What is the role of a dirty bit during block replacement?


CO3 (2.00)
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, page: 136-137 )

35. Differentiate the write policies that are used when a write miss occurs.
CO3 (2.00)
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, page: 136-137 )

36. Differentiate the write policies that are used when a write hit occurs.
CO3 (2.00)
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Book ) (Computer Organization and Architecture
Designing for Performance, page: 136-137 )
Submodule 7
Topic 1

37. Explain the structure and working of a page table. How does it support memory
protection? CO3 (6.00)
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Question Paper ) (KTU-Dec 2020, Question No-18
Dec 2022 ,Question No-19 )

4 of 5
38. With a neat diagram, explain the paging-based address translation process in a virtual
memory system. CO3 (6.00)
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Question Paper ) (KTU-Dec 2021,Question No-15
Dec 2023 ,Question No-17 )

39. Explain the virtual memory concept and describe the address translation process using a
CO3 (6.00)
page table with a neat diagram.
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Question Paper ) (KTU- Dec 2022,Questio No-16. )

40. What is meant by a TLB hit and TLB miss? CO3 (2.00)
( Theory ) ( Understanding(U) ) ( Easy ) (Ref : Question Paper ) (KTU- Dec 2022, Question No-5 )

41. What is address translation in virtual memory systems?


CO3 (2.00)
( Theory ) ( Understanding(U) ) ( Easy ) (Ref : Question Paper ) (KTU-Dec 2021 Question No.3, Dec
2022 Question No.4 )

42. Define virtual memory and state its importance.


CO3 (2.00)
( Theory ) ( Understanding(U) ) ( Easy ) (Ref : Question Paper ) (KTU- Dec 2022 Question No:2, KTU-
Dec 2023 Question No:1 )
Submodule 8
Topic 1

43. Explain how virtual memory provides efficient memory utilization and protection in modern
CO3 (6.00)
operating systems.
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Question Paper ) (KTU-Dec 2022, Question No-17 )

44. What is a Translation Lookaside Buffer (TLB)? Explain its structure, working, and
advantages. CO3 (6.00)
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Question Paper ) (KTU-Dec 2023,Question No-18
Dec 2021,Question No-16 )

45. Explain memory protection in virtual memory systems. Discuss how access rights and
CO3 (6.00)
protection bits prevent illegal memory access.
( Theory ) ( Understanding(U) ) ( Medium ) (Ref : Question Paper ) (KTU-Dec 2021,Question No-20 )

46. Explain the term page number and offset. CO3 (2.00)
( Theory ) ( Understanding(U) ) ( Easy ) (Ref : Question Paper ) (KTU-Dec 2023,Question No-6. )

47. What is memory protection? How is it achieved using paging? CO3 (2.00)
( Theory ) ( Understanding(U) ) ( Easy ) (Ref : Question Paper ) (KTU Dec 2022, Question No-7. )

48. What is a Translation Lookaside Buffer (TLB)? Why is it needed?


CO3 (2.00)
( Theory ) ( Understanding(U) ) ( Easy ) (Ref : Question Paper ) (KTU-Dec 2021,Question No-6, Dec
2023,Question No-4. )

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