32-bit Asynchronous Register File for RV32I Processor
Course: Computer Organization and Processor Design
Professor: Dr. Vikram Kumar Pudi
Student Name: Leela Nikhil M
Roll No: EE23B026
Student Name: Roshan Kumar CH
Roll No: EE23B009
1. Introduction
A register file is an essential part of a processor that stores operands and
intermediate data required during instruction execution. In RISC-V processors, the
register file enables fast and efficient access to data by the execution units.
This report presents the design and verification of a 32-bit asynchronous
register file for an RV32I processor using Verilog HDL. The register file supports
one write port and two read ports and operates without a clock signal, allowing
immediate read and write operations. The design follows the RISC-V specification,
including the special behaviour of register x0, which is hardwired to zero and
ignores all write attempts.
2. Architecture of the Register File
The register file consists of 32 general-purpose registers, each having a 32-bit
width, in accordance with the RV32I architecture. The design supports one
asynchronous write port and two asynchronous read ports, enabling
simultaneous access to multiple registers. All operations are performed without
using any clock signal, ensuring that read and write actions occur immediately
based on control and address inputs.
3. Verilog HDL Implementation
3.1 Register File Module
module register_file (
input wire we,
input wire [4:0] waddr,
input wire [31:0] wdata,
input wire [4:0] raddr1,
input wire [4:0] raddr2,
output wire [31:0] rdata1,
output wire [31:0] rdata2
);
reg [31:0] regfile [31:0];
integer i;
initial begin
for (i = 0; i < 32; i = i + 1)
regfile[i] = 32'b0;
end
always @(*) begin
if (we && (waddr != 5'd0))
regfile[waddr] = wdata;
end
assign rdata1 = (raddr1 == 5'd0) ? 32'b0 : regfile[raddr1];
assign rdata2 = (raddr2 == 5'd0) ? 32'b0 : regfile[raddr2];
endmodule
3.2 Testbench
module tb_register_file;
reg we;
reg [4:0] waddr;
reg [31:0] wdata;
reg [4:0] raddr1;
reg [4:0] raddr2;
wire [31:0] rdata1;
wire [31:0] rdata2;
register_file uut (
.we(we), .waddr(waddr), .wdata(wdata),
.raddr1(raddr1), .raddr2(raddr2),
.rdata1(rdata1), .rdata2(rdata2)
);
initial begin
$dumpfile("[Link]");
$dumpvars(0, tb_register_file);
we = 0; waddr = 0; wdata = 0; raddr1 = 0; raddr2 = 0;
#10 we = 1; waddr = 5'd5; wdata = 32'hAAAA5555;
#10 waddr = 5'd10; wdata = 32'h12345678;
#10 we = 0;
#10 raddr1 = 5'd5; raddr2 = 5'd10;
#10 we = 1; waddr = 5'd0; wdata = 32'hFFFFFFFF;
#10 we = 0; raddr1 = 5'd0; raddr2 = 5'd5;
#10 $finish;
end
endmodule
4. Simulation and Waveform Results
Simulation of the designed register file was carried out using EDA Playground with
Icarus Verilog as the simulation tool. The functional behaviour of the register file
was analysed using EPWave, where waveform results were used to verify
asynchronous write operation, dual read capability, and correct enforcement of the
zero register behaviour.
4.1 Asynchronous Write Operation
Figure 1: Asynchronous Write Operation
The waveform illustrates the asynchronous write behaviour of the register file.
When the write enable signal (we) is asserted, the data present on wdata is written
immediately into the register specified by waddr, without requiring any clock
signal. The change in register contents occurs as soon as the control and address
inputs become valid, confirming the clockless nature of the write operation.
4.2 Dual Read Operation
Figure 2: Dual Asynchronous Read Operation
This waveform demonstrates the dual read capability of the register file. Two
different read addresses (raddr1 and raddr2) are applied simultaneously, and the
corresponding outputs (rdata1 and rdata2) update immediately. The absence of
any clock dependency confirms that both read ports operate asynchronously and
independently, allowing simultaneous access to multiple registers.
4.3 Zero Register (x0) Behaviour
Figure 3: Zero Register Write Protection
The waveform verifies the special behaviour of the zero register (x0) as defined by
the RV32I specification. Even when a write operation is attempted on register x0
with write enable asserted, the output remains zero. This confirms that register x0 is
hardwired to zero and that all write attempts to this register are successfully
ignored.
5. Conclusion
The 32-bit asynchronous register file was successfully designed and functionally
verified using Verilog HDL. The simulation results clearly demonstrate correct
asynchronous write operation, dual read capability, and strict enforcement of the
zero register (x0) constraint as required by the RV32I specification. The absence of a
clock signal confirms the purely combinational nature of the read ports and the
immediate response of the write operation. Overall, the design meets all specified
requirements and serves as a reliable building block for integration into an RV32I
processor datapath.