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Asynchronous Register File RV32I Report

This document details the design and verification of a 32-bit asynchronous register file for the RV32I processor using Verilog HDL. The register file features one write port and two read ports, supporting asynchronous operations without a clock signal. Simulation results demonstrate successful implementation, including correct write operations and dual read capabilities, along with the enforcement of the zero register behavior.

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5 views4 pages

Asynchronous Register File RV32I Report

This document details the design and verification of a 32-bit asynchronous register file for the RV32I processor using Verilog HDL. The register file features one write port and two read ports, supporting asynchronous operations without a clock signal. Simulation results demonstrate successful implementation, including correct write operations and dual read capabilities, along with the enforcement of the zero register behavior.

Uploaded by

leelanikhil14
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd

32-bit Asynchronous Register File for RV32I Processor

Course: Computer Organization and Processor Design

Assignment: Asynchronous Register File Design

Student Name: ____________________

Roll No: ____________________

Date: ____________________
1. Introduction
This report presents the design and verification of a 32-bit asynchronous register file for an
RV32I processor using Verilog HDL. The design supports one write port and two read ports
and follows the RISC-V specification, including the special behavior of register x0.

2. Architecture of the Register File


The register file consists of 32 registers, each of 32-bit width. It supports asynchronous
write and dual asynchronous read operations without using any clock signal.

3. Verilog HDL Implementation

3.1 Register File Module

module register_file (
input wire we,
input wire [4:0] waddr,
input wire [31:0] wdata,
input wire [4:0] raddr1,
input wire [4:0] raddr2,
output wire [31:0] rdata1,
output wire [31:0] rdata2
);

reg [31:0] regfile [31:0];


integer i;

initial begin
for (i = 0; i < 32; i = i + 1)
regfile[i] = 32'b0;
end

always @(*) begin


if (we && (waddr != 5'd0))
regfile[waddr] = wdata;
end

assign rdata1 = (raddr1 == 5'd0) ? 32'b0 : regfile[raddr1];


assign rdata2 = (raddr2 == 5'd0) ? 32'b0 : regfile[raddr2];

endmodule
3.2 Testbench

module tb_register_file;

reg we;
reg [4:0] waddr;
reg [31:0] wdata;
reg [4:0] raddr1;
reg [4:0] raddr2;
wire [31:0] rdata1;
wire [31:0] rdata2;

register_file uut (
.we(we), .waddr(waddr), .wdata(wdata),
.raddr1(raddr1), .raddr2(raddr2),
.rdata1(rdata1), .rdata2(rdata2)
);

initial begin
$dumpfile("[Link]");
$dumpvars(0, tb_register_file);

we = 0; waddr = 0; wdata = 0; raddr1 = 0; raddr2 = 0;

#10 we = 1; waddr = 5'd5; wdata = 32'hAAAA5555;


#10 waddr = 5'd10; wdata = 32'h12345678;
#10 we = 0;
#10 raddr1 = 5'd5; raddr2 = 5'd10;
#10 we = 1; waddr = 5'd0; wdata = 32'hFFFFFFFF;
#10 we = 0; raddr1 = 5'd0; raddr2 = 5'd5;
#10 $finish;
end

endmodule

4. Simulation and Waveform Results


Simulation was performed using EDA Playground with Icarus Verilog and EPWave.

4.1 Asynchronous Write Operation

Figure 1: Asynchronous Write Operation


4.2 Dual Read Operation

Figure 2: Dual Asynchronous Read Operation

4.3 Zero Register (x0) Behavior

Figure 3: Zero Register Write Protection

5. Conclusion
The 32-bit asynchronous register file was successfully designed and verified. Simulation
results confirm correct write operation, dual read capability, and proper enforcement of the
zero register constraint.

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