Module-2

Contto enit is importat elemit cpU and aot

as the Brain o
Cenpan, -Exest
Instructim
Decode
nto Conmonl Comnon
Contro Avi thmali
unit (Cu) |Loqic Unit(4L)
Store
Tnstsutbe
fetek Resultinto
Memory
hemMemory

Enen Tnstutin uppovted by Canputo

Cempti cou hast
be dserdad by cu &executid comectly.
Coto unit cmts 4low ta Thstue tiony base
the processor, Memory & lo dvie.
Digil Conpata ito iniiati
’ It natu yoleveit dami 4contal signal for al
PROARAM EXecwTION

|Tustutin cyele Tnshuetonyca nshnétionyele

[fetch Decode Execuite) Trteyupt|

’ Control unt gennit Cot

’A Prgram setsequsnee of Instruetions , ahd in struitiny
ave exeeulid thugh instelion
 2
’ fundtien lomtast nit
í Tngtuetim fetehing rom Masn emy
Öj) beeodng o Instucion t Inteprts the Inshulb
t undntand pohat openoti aetion ic raquired.
(ii) Exe eution of Tnstyetions / To qeurati Cen tat ig naly
fo te exeetion t In etruction,
hok s Control sinal

Tnterfacy with Monm ory &T<o deice

Contl ¢ Dta Peus
’ Exeeuto
Thshuetim Ryister
Instuetiog
Covtrnh signc
withn cU
Flay Oontro -Contl sijnal
wnit t m Cool Buy
Clock >Control slnel

Axternal
-’ AcU recuvs Data|Thstuetions fem the
User and tam|atz . it int Conthol Gmal and
deliver it to C PU.
Contol,unit

Harduired Micstorgremel
Contt unit
Contol wit

Contol igmld Cntrol Siqhals arare

lagie cirait qemnatid, uig Micmpgramig
 Module
ContolDeoign

I Harduwired 2. Micooprogramed
Control nit
Coutol wnit

Sequaidil Statis AadhwCot

Statús Logic Covitrol Memory
siynads uits sianals
miaditiuti
Register
Tnstuetio
Register 4
Decod
Ih struction
Rgister
.Contrt
1 Siznala
Gevyeral steture
Hardwired Contro cits General shruehere ot
6f
Micoprogramed Gontounits

CRU Coitol units both Harduired aud Microprogramad, aYe

CMicro) inotuctions PipelinA

generota Coito| sigmali to He Dati Path

eters the Dati Path at "Cortyol Points
Comtral signls
tuhere thiy select th tine tins to be parformed
at specifie tims and ote the data through
the appro pYri ate parta 'of the dota path ynit. !
Control wit reconfigures the dotapath to implemut
Some sþacifid instruetion
 Diferences between
Hardwired and Microprog rammed Contnl unitr

Parametera Havdwired
Conto unit
Microprog ramned
Control 'unite

I. Cotal signala Genatid wing Handaaau Generated aing satwan

2. Stucture Basedonm Hordware, soit Basea om, sttware
is Ripid So it, is (lanible
[Link] bme by Reduigmit Done
[Link] kinset Smat eimple
S. Ditiuut
G. Pmuetin Not Possißle Possible

slee
8. Cot tow Costas no Coni Hih ostt due
Memot, bit t many to'Contl Mmy
Lnstueion stit is
mise

9. rocessor Resfomed Rrse i

Pro ces sor, Ctsc> Compl Irstruch
(REseReducsd Dstuebonset
Cat Compul
1
Conpot)
More" chip- Area Ley chi Area
lo. ChipArea

INTEL

(2. Ape'catie ARM

 DESIGN HARDWIREA CoNTROL UNTL

|Lnsteetim Roictes

Deeo
ST

BECIN Ete - Stale

Staus.(Aeco) MachenecFsm

Cock
(T., . )
’ In Hardwired imnplemtation,, CU
machine ciyeut Tts Tle Lryice sinada are

tua ot opeode and petomydettetactions for

d i t t Instetiows.
Inputa
A Deoon wee have n-binary binag
n decadd
Dtus, Tt takes eneodd T|PS and
binay os itnd
’ Tke elbck bortion oot Contolwnt issus a ept tive
Seaunee ot pulae. gt it na tor maaait te
Peisd o cloctk ulss Must ba to allou

CU emits d i tcontal signals t tim uits

aidai a singe instructim eycle (Ti, Ti
Twetuetim Cqele, tha CU muit ted back
t e coui to veinitialize it T.
 DEsiaN ot MSCRoPR0<RAMMAD Co NTROL UNIT

MICROINATRUTonS

- MIcro programig is a mehod of Contnt unit

selec ion ant requeneeig ngomet
(n a Contt Mmoy,
Eack MicvoTrotuetion dscribesa set t Micvoopnatin occowny
n me

- Asequune MioTstruetim i khewn Mioopagram

Micro Instuetin omat

yVerlical MicoInstueto
) Hovizmtal MicoTwtueto

Minstruetion Adalro
Jump Cenditin
nCenditi onel
orerflew

-Tndirect Bit
Bus Cantral als.
InatycHon fomat
1) Horizntal MicYo

Miro Instueion Add nsr

-Jump Cenditia

?funclion Codes.

2) Nartical MicbImtructn fomat

16 24 31

Contol field
Operand i oþeraud 2 Contrl Memry
( ohcodey etring Tnfomatiei
22-bit Micn Instruetion formt t t8M yg lem t
Madel
 I) Hoi2gntal MicoTnstry etiu
-Lmy fomati
-Abilty to Express higb degres odParallelism
- H e ene oding on to Tnomaton
2 Vertical Mio Tmtuetin
-sht frmatt aperatien
Exprass Parallel mioo
Limitead Abi lity to Tnfomatio
Centl
Censidnable enerdg ¢ the
DESIAN OF MrCROPRoARAMMkD CoNTROL UNI?

Instuton Roqicer

Decod

ALU

Logic Control
Read
Memoy
(

Rugicter
Nest Addsees
Contol
Decoder

Contnl
Siynals ithh to
’ Set o
MioTnstruciows(uProgramy is stored na Contol Memo
’ Contro Add ves Regisky - Contaahs Addre ss o Next u Ln
stryct'on
to be Read
uhen a MicoInstueton is read from he
Conto Mem6ry,
it it tranered to the Contol
Bufer
Reading oa uIuteliom hon te Conbo Register.
executya Istrucie
Memoy it the same
Seg uuneeng unit Loadr he Centol A4drer Rester ant
Funetiv Contlunitissuss a Read Commend.

|. To execuitr anTwstuctin, the sagmeig LogHe

unit
/ssuey a READ lemman to the Contnl "Memy
2. Tae wyd whoe Atdres is specitkied in the Contl Addres
Rsg- s raad int the Crnts Butter eugiskr
3 Tae contat of contst Butor Reg qunrata Contrl signal!
and Nent Addhey inmatisn bir the aqneg lopie unit
ic umt \oads nw Add vess nto the
Contal Addres based om net Atdes (nformatn

en the Value the ALU and Cemtal

butor register 5n dh the the delsins is made

I. Get the NentInstucan- Add ene to theContoAddees

2. Jump k a new Yotine based om
a Tump Miyo Tnstue ton
Load the Addres
inti
the Cottol Addres
[Link] to Machine Inctuc tion kone - Load the Cont Adde:g
Reg. based on the oþcoda
In tu Instuetion
 ubpus Delbds- pper De oder tamlos the opeode
o Tnstuetzo
(nto a Contol Mnoy Addres,
Decoder Dee s hot wsed fr Hoi zontal
SLoweY
Mioo instbuetin, bt it weal frr vertical
Micyo instuetione,
 MrCRo PRo<KAM SEgUECING
>Pistsospo MicrInstue ions are stored in Coitnt Memoy
th and each a Roiine.
’ pach Canhitey instsuctim has its own peqram Yotin
reculg
th nstuctin,
’ Haudesare that contr Hhe Addve cs
Henony, must ba Capabl st sewneig the Ihstu Eion
ithen a Roti and be able to brnh fro tne

rmitin to anothe

steps MicioTnstruetimSAyencs
A initial address is loaded in Contel Adreer Rig. whn pouser
þower
D An rst miyomaiuek
tumedA ON. ( This Add rer: is uaally the addreis
ir
hat ativatis the Instuetin fetch routi)
control AdAhus
rotinn is seqnced by inrenetig the
feteh
structios.
Register throgh te rest ot its un instuctien is in
otne, He
A+ the end o the feteh
Conpata,
the instructio Riyistur d outinthat ditmis tHe
( Contol Menoy go thrangh the
etective adds o the ohnand,
electire addes Computatin route n control, memony
f instrectien, which
Can be yeachd thrugh a brauel micro
lecenditoned on the sta of the mode bits of instructions
shen te Adda etfective addss Cempatatn is completed,
He Address s the oprand is availahle i Hae memy
Addlress Ruister.
Tae micro ohatien teps to be gensted in phocesar Ryiste
Paah instructio has it's own micropragrasn
stored in a ven locati o lontrod memoya
 Code, bitt
Insttin cod
Thetansmatito the
shee tu roulane is oCatal
to an addhes in eontro memoA
is retkd as a'Mapping procest".

Contiol Addhss, bnee the rquired roline

te Micr ingtuetibs that exets the Instucion may
be keaumerd by in eremtig eont Addreu Ruz but soSemetie
en the valu t etai sfaty bits in
frousss
Lnstuctin Code
Ryistor,

Mappin
Lotic
fBranih Muxilne
Iroute

Multiplewes Reg.(SeR
Lusie
Celectl
Stats Control Addre
Bits Tnerementur
Ryister CARJ

lontol
Memoy
Caleta Mioooþerafim
tats Bit
Byane Aedyes

frr Corthol temory

Moping st Tnstrucien PLDPruqramasle
Implemeed by Mew ot an
IC Called
the Rom
Logic dricy sinilaa to
’

to the T words i
sþaciky a braneh
LImtuetion
MiCroprgram
routine
Cemtrl Memoy, where a
fr (ocataa The stalay bit for tis tybe
branck ae bits in he ofuusim Gde fantf he instruzlen
A
’ For each shuaten Code thne exista uproqram routne
control Hamy Hhat eecutis the instusto.
Conlte,
Lohe te executim ot the instualsn
tatek rutie
Control must yetin to tha
ca7abilas equredtn a
Tle Addus sogueneing
are

dipndi on
nenditinal braneh or Conditional braneh
stets bit Condiins.
te instuetin to an
ta
Procus fom the bits st
A Hoppang
addresr tr Contol memer.
subrotine Cal and Retin,
4 Afaeily fr
 PIrELINE CONTROL (13)

-’ Pipining pserids a basic wway to spedup Aritmitie opuatimg

’IH is also ed to implamt ettire inetucirm-proce ing
bshavioof a high pufomanee
LNSTRUCTIONO PIPELINEs
Instretimt pamthhough
theg a sequune
Duihg progTam ereaition, ipaliwis
lend tthumselves natiraly tt
o
d procesing skps that
AcPU Can be o"ganized One or More pepalins, whose Varios
Stages- Feteh opcods and oerande, execute instuctions
and
stor Reult n Registeylesternal
taoney.
’ An Tnstueten pipali is matikundi recomf'urable
pipuline dusignad to spudup a Compeitas puntormauce by
tiuty overlogpuig the prcessing 4 Instuetins.
PIPELINE STRUTURE

CoNrRoL Bus

Data
Data

s Sm

(Stuete fa m-stage ipline)

along
Stci=,2,-.my) Computee Resutis passes them,
uith unprocessed Inputt ohuands
to for tunth processig and
set
S; yeCeves a nes

Si
ae placed bale
’ Butt Rogisters and othia Sumchrmews dotic each
Stags, So thot staqes do not interfuu wsth oths
 ’ Perfomanee speudup &au Tatuetion pipiue duives fe
the faot that upt 'm'indipnd an
imtuetny can be pongrea

Tawo fastr d asimplest Pipeline Instuekon

fetch stage (S)
Exeeut sthge (sy
Tioo stag piphiw ineneasns thhanghgut by overlapig Tistucti
Fetluy audThotuetin Eeuti.
instuetin ith addhess A; executad by shge s
o Ii Aadres Aitr
Censeeiie
Ih instetie witth neut
on
tehsd b sage si, aud so
Multi stage Tnstructim helining
MAtN MEMDRY MAZN

Data
fetch a n d p Data Write
Read ALU
Decede
Logie
Registey:
S,: Ihstruction
fetch operand S:ALU s:operand
Stere
(I) Load bhundioy
Executo (os)
(Ex)

zti oftf aa CPU Incorpoating a frur saye

-’ An m-stage instruetion hiplinng can overlap the procing

t upto m-insTrucins to manimize thooughgut,
en the Maimm Nor f Stes
Can be

brrckw.
 )
(he 4-stages Si:sy ufom the tataig tunetiang
isingt
1. IE:Twtretion fetching and Deeoding
Memog to RE
2. OL : Ohunand Loding thom th
Aote iyg using the ALU and RF
3. Ex : Data Main Memony
storing to Hha
A. oS : huhand

nd Memory store (store n Hemoy spr

atioy
ant
Stags , Ss, [Link] share tha ceu's Ban local Rgis ters
in RFLeaister fil), Tun pegistevs act interstage
inplanst pata tramner
Stag Ss and
ALU

Stage contetes m a Siugle epU clock eyele st

’ t each
’ at
& ClU as a whole Can be cloked
L(Te), Ripetine
Brgunep (4)= Z at it's Magimmeoetin rot
PERfoRMANcE
PIrE LINE

taget Aond.
tuith respect t
Can be
easured by it's threughet in
meesured tems
Perfrmanee
(MIPs) and
Milia d Tnstruetions exe cutid pe second
Not clock cyelee p Tnstrustiey (CPI).
Whre,
MIS f ’ lipaline elock bregeney i Mte
MHz,
Mrlss TWughput

’MEls=f|
MIPs
Shaa-TineDigrom for pipalne lesfena
Shaee-time gra tor m-staya pipeline has tha fom o
shucti
m’ No slag d pepelaine
No cloek lyely to Conplate he exeetin dt
Söme Segne N-instutiong

SI
II T|
I

SH
2 2
shaa-Tm Diagram
I’Ihshucta bing krolmeel and by stage (S)
Tmtucton
utill'eal in
Bonksfee’ Stagu ae not
Segienee 4entavailall

whin heded
m-stages E(m) i
Busy rea(Blanek Box)
Eny =

44
:76
 Meawue t Paline pinfomane 1

Stm) = t(m)
Pipline
Tmy Erection time for
Seme tasyet woklond.
whue
qan m- staye
Now' Resomdlly! Exeeution time fr
T y ’ Same woklo e e l r

asenme Non pilind prossar

Case

an related
and shadu¢

Sny nE)

-
No st
'staga
So, Ey E(4)=0s8

Cannotexed ym.
23ad
Stmy =
we

optimi zig ) hane to

inrean No.

lertomanalacte Rati pc
Piatine preyuy
f’ Pjpaisie cletk Cost.
1 k ’ Hard ware
 Lt pipuline (P) has m-stngus ond implemnt sat at she ati
(instuetñg" SI,
eticent Mon pihalid prounsr thataleo
implameit ST(sot 4Tytruaio)
so bwe can anune tHhat eaek stnge(S;) aline (P)

Menee,
Pr p's
Clek perid

Tas, Pipaline's Hardwoie Cast is Sivn by

k= cm td]
Harduan Constet factnr coet dpipaline's pat prrunit egic
Cost

Cost pe slage

PcRk

f PR'= KT

pce bem + bd)mn t ad

bcm+ ac+ bdym +ad

 Haximize PeR with Tespect to No t stogs (my

to 7ero
So, m
bcm actbd)m+ ad
d

d
d

be nt +(acrbdym od]
bcm.
+ac+helsmn +ad
2bem+ actbdyx

ad bem
m ad
Nb

Maximum or sbimum alu sf m

m ad
optimum

duu to Buter Bqist

Data
d Cost d Pipalinds
 Drao th

Qud b =c =1.
ad
m be

Henee,
oY Minimum Cost pu
Þu Ineueti scessed ie

bcm+ (aetbdym + ad

Ixx + (Sxl +lxs)xs+SXS

peR =0:os
|00

PCR

-04

O03

0-02