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VLSI Lab Experiments

The document outlines a series of experiments focused on designing and verifying various CMOS circuits, including inverters, NAND, NOR gates, a full adder, a multiplexer, static and dynamic logic, a D flip-flop, NMOS characteristics, a current mirror, and a CS amplifier. Each experiment includes aims, circuit designs, procedures, results, and conclusions confirming the functionality of the circuits. Overall, all experiments successfully demonstrated the intended logic and characteristics.

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3 views10 pages

VLSI Lab Experiments

The document outlines a series of experiments focused on designing and verifying various CMOS circuits, including inverters, NAND, NOR gates, a full adder, a multiplexer, static and dynamic logic, a D flip-flop, NMOS characteristics, a current mirror, and a CS amplifier. Each experiment includes aims, circuit designs, procedures, results, and conclusions confirming the functionality of the circuits. Overall, all experiments successfully demonstrated the intended logic and characteristics.

Uploaded by

VZM DIARIES
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

Experiment 1: CMOS Inverter

Aim: To design CMOS inverter and obtain VTC.

Software: LTSpice

Circuit: PMOS to VDD, NMOS to GND, common drain output

Truth Table: 0→1, 1→0

Waveform: Inverted output, S-shaped VTC

Procedure: Design, apply DC sweep & transient

Result: Inversion verified

Analysis: Switching ~VDD/2

Conclusion: CMOS inverter works correctly


Experiment 2: NAND & NOR

Aim: Design CMOS NAND & NOR

Circuit: NAND (NMOS series, PMOS parallel), NOR opposite

Truth Table verified

Waveforms: Logic outputs

Procedure: Simulate all inputs

Result: Correct outputs

Conclusion: Gates verified


Experiment 3: Full Adder

Aim: Design CMOS full adder

Inputs: A, B, Cin

Outputs: Sum, Carry

Truth table verified

Result: Correct logic

Conclusion: Full adder works


Experiment 4: 2:1 MUX

Aim: Design MUX using transmission gate

Logic: Y = S■D0 + SD1

Result: Correct selection

Conclusion: MUX verified


Experiment 5: Static CMOS Logic

Aim: Implement Y=(AB+C)'

Procedure: Pull-up & pull-down design

Result: Output correct

Conclusion: Static CMOS works


Experiment 6: Dynamic CMOS

Aim: Design dynamic logic

Phases: Precharge & Evaluate

Result: Correct output

Conclusion: Dynamic logic verified


Experiment 7: D Flip-Flop

Aim: Design D FF

Operation: Edge triggered

Result: Q follows D

Conclusion: Flip-flop verified


Experiment 8: NMOS Characteristics

Aim: Plot ID-VDS & ID-VGS

Regions: Cutoff, Linear, Saturation

Result: Graphs obtained

Conclusion: Characteristics verified


Experiment 9: Current Mirror

Aim: Design NMOS current mirror

Result: Current mirrored

Conclusion: Mirror works


Experiment 10: CS Amplifier

Aim: Design CS amplifier

Gain: Negative

Result: Gain ≈ -6

Conclusion: Amplifier verified

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