EXP NO :- 02
Multiplexers and Demultiplexers
DATE :- 20/08/2025
AIM :- To simulate Multiplexers and Demultiplexers in behavior, structural, and
dataflow model of Verilog HDL.
SOFTWARE USED :- Xylinx Vivado
HARDWARE USED :- Basys3 Board
4 to 1 MULTIPLEXERS
THEORY :-
A 4-to-1 multiplexer (MUX) is a combinational circuit that selects one of four input lines
and forwards it to a single output line.
It uses two selection inputs (S₁, S₀) to choose which input (I₀–I₃) is connected to the
[Link] functions as a data selector, allowing multiple data sources to share one
transmission line.
Logic Expression :-
Y = (~s1&~s0&i0) | (~s1&s0&i1) | (s1&~s0&i2) | (s1&s0&i3)
Truth Table :- Logic Diagram :-
s1 s0 Y
0 0 i0
0 1 i1
1 0 i2
1 1 i3
VERILOG DESIGN CODE :-
Behavioral Model
module mux4_1(y, i0, i1, i2, i3, s1, s0);
output reg y;
input i0, i1, i2, i3;
input s1, s0;
always @(*) begin
case ({s1, s0})
2'b00: y = i0;
2'b01: y = i1;
2'b10: y = i2;
2'b11: y = i3;
default: y = 1'bx;
endcase
end
endmodule
Data Flow Model
module mux4_1(y,i0,i1,i2,i3,s1,s0);
output y;
input i0,i1,i2,i3;
input s1,s0;
assign y = (~s1&~s0&i0)|(~s1&s0&i1)|(s1&~s0&i2)|(s1&s0&i3);
endmodule
Structural Model
module mux4_1(y, in, sel);
output y;
input [3:0] in;
input [1:0] sel;
wire s1n, s0n;
wire a0, a1, a2, a3;
not (s1n, sel[1]); // Inverters
not (s0n, sel[0]);
and (a0, s1n, s0n, in[0]); // i0 selected
and (a1, s1n, sel[0], in[1]); // i1 selected
and (a2, sel[1], s0n, in[2]); // i2 selected
and (a3, sel[1], sel[0], in[3]); // i3 selected
or (y, a0, a1, a2, a3);
endmodule
Testbench :-
module mux4_1_tb();
reg i0,i1,i2,i3,s1,s0;
wire y;
mux4_1 uut(y,i0,i1,i2,i3,s1,s0);
initial
begin
i0 = 1'b1;i1 = 1'b0; i2 = 1'b1; i3 = 1'b0;
s0 = 1'b0 ; s1 = 1'b0;
#10 s0 = 1'b0 ; s1 = 1'b1;
#10 s0 = 1'b1 ; s1 = 1'b0;
#10 s0 = 1'b1 ; s1 = 1'b1;
end
endmodule
Output Waveform :-
FPGA Board Implementation :-
INPUT INPUT(SELECTOR) OUTPUT
i3(R2) = 1 s1(V16) = 0 Y(U16) = 1(LD0)
i2(T1) = 0 s0(V17) = 1
i1(U1) = 1
i0(W2) = 0
8 to 1 MULTIPLEXER
Theory :- An 8-to-1 multiplexer (MUX) is a combinational logic circuit that selects one
input out of eight input lines (I₀–I₇) and routes it to a single output.
It uses three selection lines (S₂, S₁, S₀) to determine which input is connected to the
[Link] acts as a data selector, enabling multiple signals to share one communication
line.
Logical Expression :-
Y = (~S2&~S1&~S0&i0) | (~S2&~S1&S0&i1) | (~S2&S1&~S0&i2) | (~S2&S1&S0&i3) |
(S2&~S1&~S0&i4) | (S2&~S1&S0&i5) | (S2&S1&~S0&i6) | (S2&S1&S0&i7)
Truth Table :- Logical Diagram :-
s2 s1 s0 Y
0 0 0 i0
0 0 1 i1
0 1 0 i2
0 1 1 i3
1 0 0 i4
1 0 1 i5
1 1 0 i6
1 1 1 i7
VERILOG DESIGN CODE :-
Behavioral Model
module mux8_1_behavioral ( input [7:0]i , input [2:0] sel, output reg y);
always @(*) begin
case(sel)
3'b000: y = i0;
3'b001: y = i1;
3'b010: y = i2;
3'b011: y = i3;
3'b100: y = i4;
3'b101: y = i5;
3'b110: y = i6;
3'b111: y = i7;
endcase
end
endmodule
Test bench :-
module mux8_1_tb;
reg i0,i1,i2,i3,i4,i5,i6,i7;
reg [2:0] sel;
wire y;
mux8_1_behavioral uut(.i0(i0), .i1(i1), .i2(i2), .i3(i3), .i4(i4), .i5(i5), .i6(i6), .i7(i7), .sel(sel), .y(y));
initial begin
i0=1; i1=0; i2=1; i3=0; i4=1; i5=0; i6=1; i7=0;
sel = 3'b000; #10 ;
sel = 3'b001; #10 ;
sel = 3'b010; #10 ;
sel = 3'b011; #10 ;
sel = 3'b100; #10 ;
sel = 3'b101; #10 ;
sel = 3'b110; #10 ;
sel = 3'b111; #10 ;
$finish;
end
endmodule
Output Waveform :-
FPGA Board Implementation :-
INPUT INPUT(SELECTOR) OUTPUT
i7(R2) = 0 s2(W16) = 0 Y(U16) = 1(LD0)
i6(T1) = 1 s1(V16) = 1
i5(U1) = 0 s0(V17) = 1
i4(W2) = 1
i3(R3) = 1
i2(T2) = 1
i1(T3) = 1
i0(V2) = 0
16 to 1 MULTIPLEXER USING 4to1 MULTIPLEXER
Theory :-
A 16-to-1 multiplexer (MUX) selects one of sixteen input lines (I₀–I₁₅) and routes it to a
single [Link] can be constructed using five 4-to-1 MUXs — four act as the first stage,
and one as the final stage to select among their outputs.
The circuit uses four selection lines (S₃, S₂, S₁, S₀) where the lower two (S₁, S₀) control
the first-stage MUXs and the upper two (S₃, S₂) control the final-stage MUX.
Truth Table :- Logical Diagram :-
s3 s2 s1 s0 Y
0 0 0 0 i0
0 0 0 1 i1
0 0 1 0 i2
0 0 1 1 i3
0 1 0 0 i4
0 1 0 1 i5
0 1 1 0 i6
0 1 1 1 i7
1 0 0 0 i8
1 0 0 1 i9
1 0 1 0 i10
1 0 1 1 i11
1 1 0 0 i12
1 1 0 1 i13
1 1 1 0 i14
1 1 1 1 i15
VERILOG DESIGN CODE :-
module mux16_1(input [15:0] in, input [3:0] sel, output y);
wire out0,out1,out2,out3;
mux4_1 m0(out0, in[0], in[1], in[2], in[3], sel[1], sel[0]);
mux4_1 m1(out1, in[4], in[5], in[6], in[7], sel[1], sel[0]);
mux4_1 m2(out2, in[8], in[9], in[10], in[11], sel[1], sel[0]);
mux4_1 m3(out3, in[12], in[13], in[14], in[15], sel[1], sel[0]);
mux4_1 m4(y, out0, out1, out2, out3, sel[3], sel[2]);
endmodule
Test bench :-
module mux16_1_tb;
reg [15:0] in_tb;
reg [3:0] sel_tb;
wire y_tb;
mux16_1 uut(.in(in_tb), .sel(sel_tb), .y(y_tb));
initial begin
in_tb = 16'b1001_0110_1100_1110;
sel_tb = 4'b0000; #10;
sel_tb = 4'b0001; #10;
sel_tb = 4'b0010; #10;
sel_tb = 4'b0011; #10;
sel_tb = 4'b0100; #10;
sel_tb = 4'b0101; #10;
sel_tb = 4'b0110; #10;
sel_tb = 4'b0111; #10;
sel_tb = 4'b1000; #10;
sel_tb = 4'b1001; #10;
sel_tb = 4'b1010; #10;
sel_tb = 4'b1011; #10;
sel_tb = 4'b1100; #10;
sel_tb = 4'b1101; #10;
sel_tb = 4'b1110; #10;
sel_tb = 4'b1111; #10;
$finish;
end
endmodule
Output Waveform :-
FPGA Board Implementation :-
INPUT INPUT(SELECTOR) OUTPUT
i15(R2) = 0 i3(W17) = 0 s3(W19) = 1 Y(U16) = 1(LD0)
i14(T1) = 0 i2(W16) = 0 s2(U17) = 0
i13(U1) = 0 i1(V16) = 0 s1(T17) = 0
i12(W2) = 0 i0(V17) = 0 s0(T18) = 0
i11(R3) = 0
i10(T2) = 0
i9(T3) = 0
i8(V2) = 1
i7(W13) = 0
i6(W14) = 0
i5(V15) = 0
i4(W15) = 0
32 to 1 MULTIPLEXER USING 4to1 AND 8to1 MULTIPLEXER
Theory :- A 32-to-1 multiplexer (MUX) selects one of thirty-two input lines (I₀–I₃₁) and
routes it to a single output [Link] can be implemented using four 8-to-1 MUXs in the first
stage and one 4-to-1 MUX in the second [Link] lower three select lines (S₂, S₁, S₀)
control each 8:1 MUX, while the upper two select lines (S₄, S₃) select one of the four 8:1
outputs through the 4:1 [Link] hierarchical structure simplifies design and efficiently
handles large input combinations.
Logic Diagram :-
Truth Table :-
VERILOG DESIGN CODE :-
module mux32_1 ( input [31:0] in, input [4:0] sel, output y );
wire [3:0] mux_out;
mux8_1_behavioral M1 (.i0(in[0]), .i1(in[1]), .i2(in[2]), .i3(in[3]),
.i4(in[4]), .i5(in[5]), .i6(in[6]), .i7(in[7]),
.sel(sel[2:0]), .y(mux_out[0]));
mux8_1_behavioral M2 (.i0(in[8]), .i1(in[9]), .i2(in[10]), .i3(in[11]),
.i4(in[12]), .i5(in[13]), .i6(in[14]), .i7(in[15]),
.sel(sel[2:0]), .y(mux_out[1]));
mux8_1_behavioral M3 (.i0(in[16]), .i1(in[17]), .i2(in[18]), .i3(in[19]),
.i4(in[20]), .i5(in[21]), .i6(in[22]), .i7(in[23]),
.sel(sel[2:0]), .y(mux_out[2]));
mux8_1_behavioral M4 (.i0(in[24]), .i1(in[25]), .i2(in[26]), .i3(in[27]),
.i4(in[28]), .i5(in[29]), .i6(in[30]), .i7(in[31]),
.sel(sel[2:0]), .y(mux_out[3]));
mux4_1 M5 (.y(y), .i0(mux_out[0]), .i1(mux_out[1]),
.i2(mux_out[2]), .i3(mux_out[3]),
.s1(sel[4]), .s0(sel[3]));
endmodule
Test bench :-
module tb_mux32_1;
reg [31:0] in;
reg [4:0] sel;
wire y;
mux32_1 uut (.in(in), .sel(sel), .y(y));
initial begin
in = 32'hA5A5A5A5; // test pattern
for (sel = 0; sel < 32; sel = sel + 1) begin
#10;
end
end
endmodule
Output Waveform :-
1 to 4 DEMULTIPLEXER
Theory :- A 1-to-4 Demultiplexer (DeMUX) is a combinational logic circuit that takes a
single input and routes it to one of four output lines.
It uses two selection lines (S₁, S₀) to determine which output line receives the input
[Link] acts as a data distributor, sending one input signal to multiple destinations
based on select inputs.
Logical Expression :-
assign y0 = (~sel[1] & ~sel[0]) & din
assign y1 = (~sel[1] & sel[0]) & din
assign y2 = ( sel[1] & ~sel[0]) & din
assign y3 = ( sel[1] & sel[0]) & din
Truth Table :- Logical Diagram :-
s1 s0 y3 y2 y1 y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
VERILOG DESIGN CODE :-
Behavioral Model
module demux1_4_behavioral ( input din, input [1:0] sel, output reg y0, y1, y2, y3);
always @(*) begin
y0 = 0; y1 = 0; y2 = 0; y3 = 0; // Default values
case(sel)
2'b00: y0 = din;
2'b01: y1 = din;
2'b10: y2 = din;
2'b11: y3 = din;
endcase
end
endmodule
DataFlow Model
module demux1_4_dataflow ( input din, input [1:0] sel, output y0, y1, y2, y3);
assign y0 = (~sel[1] & ~sel[0]) & din;
assign y1 = (~sel[1] & sel[0]) & din;
assign y2 = ( sel[1] & ~sel[0]) & din;
assign y3 = ( sel[1] & sel[0]) & din;
endmodule
Structural Model
module demux1_4_structural (input din, input [1:0] sel, output y0, y1, y2, y3);
wire n0, n1;
not (n0, sel[0]);
not (n1, sel[1]);
and (y0, din, n1, n0);
and (y1, din, n1, sel[0]);
and (y2, din, sel[1], n0);
and (y3, din, sel[1], sel[0]);
endmodule
Test bench
module tb_demux_1to4;
reg din;
reg [1:0] sel;
wire y0, y1, y2, y3;
demux_1to4 uut (.din(din), .sel(sel), .y0(y0), .y1(y1), .y2(y2), .y3(y3));
initial begin
din = 1; sel = 2'b00; #10;
din = 1; sel = 2'b01; #10;
din = 1; sel = 2'b10; #10;
din = 1; sel = 2'b11; #10;
din = 0; sel = 2'b00; #10; // Test with din = 0 (all outputs 0)
din = 0; sel = 2'b01; #10;
din = 0; sel = 2'b10; #10;
din = 0; sel = 2'b11; #10;
$finish;
end
endmodule
Output Waveform :-
FPGA Board Implementation :-
INPUT(SELECTOR) OUTPUT
s1(R2) = 1 y3(V19) = 0
s0(T1) = 0 y2(U19) = 1
y1(E19) = 0
din(V17) = 1 y0(U16) = 0
1 to 8 DEMULTIPLEXER
Theory :- A 1-to-8 Demultiplexer (DeMUX) is a combinational circuit that takes a
single input and directs it to one of eight output [Link] uses three selection lines (S₂, S₁,
S₀) to determine which output line carries the input [Link] functions as a data
distributor, sending one input signal to any one of several destinations based on select
inputs.
Truth Table :- Logical Diagram :-
s2 s1 s0 y7 y6 y5 y4 y3 y2 y1 y0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
VERILOG DESIGN CODE :-
module demux1_8 (input din, input [2:0] sel, output reg y0, y1, y2,y3, y4, y5, y6, y7);
always @(*) begin
y0=0; y1=0; y2=0; y3=0; y4=0; y5=0; y6=0; y7=0; // Default reset of outputs
case(sel)
3'b000: y0 = din;
3'b001: y1 = din;
3'b010: y2 = din;
3'b011: y3 = din;
3'b100: y4 = din;
3'b101: y5 = din;
3'b110: y6 = din;
3'b111: y7 = din;
endcase
end
endmodule
Test bench
module tb_demux1_8;
reg din;
reg [2:0] sel;
wire y0,y1,y2,y3,y4,y5,y6,y7;
demux1_8 uut (.din(din),.sel(sel),.y0(y0),.y1(y1),.y2(y2),.y3(y3),.y4(y4),.y5(y5),.y6(y6),.y7(y7));
initial begin
din = 1; // Test with din = 1
sel = 3'b000; #10;
sel = 3'b001; #10;
sel = 3'b010; #10;
sel = 3'b011; #10;
sel = 3'b100; #10;
sel = 3'b101; #10;
sel = 3'b110; #10;
sel = 3'b111; #10;
din = 0; // Test with din = 0 (all outputs should remain 0)
sel = 3'b000; #10;
sel = 3'b111; #10;
$finish
end
endmodule
Output Waveform :-
FPGA Board Implementation :-
INPUT(SELECTOR) OUTPUT
s2(R2) = 1 y7(V14) = 1
s1(T1) = 1 y6(U14) = 0
s0(U1) = 1 y5(V15) = 0
y4(W18) = 0
y3(V19) = 0
din(V17) = 1 y2(U19) = 0
y1(E19) = 0
y0(U16) = 0
1 to 16 DEMULTIPLEXER USING 1to4 DEMULTIPLEXER
Theory :- A 1-to-16 Demultiplexer (DeMUX) is a combinational logic circuit that takes
a single input and routes it to one of sixteen output lines.
It uses four selection lines (S₃, S₂, S₁, S₀) to determine which output line carries the input
signal. It acts as a data distributor, allowing one input signal to be sent to multiple
possible destinations.
Logical Diagram :- Truth Table :-
VERILOG DESIGN CODE :-
module demux_1to16 ( input din, input [3:0] sel, output [15:0] y);
wire d0, d1, d2, d3; // Outputs from the first-level 1-to-4 demux
// First level 1-to-4 demux: selects which 4-output group is active
demux_1to4 level1 (.din(din), .sel(sel[3:2]), .y0(d0), .y1(d1), .y2(d2), .y3(d3));
// Second level: each d0-d3 drives a 1-to-4 demux
demux_1to4 level2_0 (.din(d0), .sel(sel[1:0]), .y0(y0), .y1(y1), .y2(y2), .y3(y3));
demux_1to4 level2_1 (.din(d1), .sel(sel[1:0]), .y0(y4), .y1(y5), .y2(y6), .y3(y7));
demux_1to4 level2_2 (.din(d2), .sel(sel[1:0]), .y0(y8), .y1(y9), .y2(y10), .y3(y11));
demux_1to4 level2_3 (.din(d3), .sel(sel[1:0]), .y0(y12), .y1(y13), .y2(y14), .y3(y15));
endmodule
Test bench
module tb_demux_1to16;
reg din;
reg [3:0] sel;
wire [15:0] y;
demux_1to16 uut (.din(din), .sel(sel), .y(y));
integer i;
initial begin
// Test with din = 1
din = 1;
for(i=0; i<16; i=i+1) begin
sel = i;
#10;
end
// Test with din = 0 (all outputs should be 0)
din = 0;
for(i=0; i<16; i=i+1) begin
sel = i;
#10;
end
$finish;
end
endmodule
Output Waveform :-
FPGA Board Implementation :-
INPUT(SELECTOR) OUTPUT
s3(R2) = 1 y15(L1) = 0
s2(T1) = 1 y14(P1) = 0
s1(U1) = 0 y13(N3) = 1
s0(W2) = 1 y12(P3) = 0
y11(U3) = 0
din(V17) = 1 y10(W3) = 0
y9(V3) = 0
y8(V13) = 0
y7(V14) = 0
y6(U14) = 0
y5(U15) = 0
y4(W18) = 0
y3(V19) = 0
y2(U19) = 0
y1(E19) = 0
y0(U16) = 0