Department of Electronics and Computer Science
FE(CMPN) SEM-II
Computer Organization & Architecture
By
Amaya Pethe
Amaya Pethe
Module 4 : Control Unit Design
• Control unit implementation approaches and their
comparative analysis. Hardwired Control Unit: State Table
Method, Delay Element Methods, sequence counter
method,
• Microprogrammed Control Unit: wilkies design, Micro
Instruction-Formats, Hoizontal and vertical microinstruction,
RISC Vs CISC
Amaya Pethe
Von Neumann model(Typical CPU
Organization.)
PCU
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Pethe
[Link] Memory for Instructions and Data
•The diagram shows one memory block connected through a system bus.
•In Von Neumann architecture, program instructions and data share the same
memory.
2. System Bus
•A single system bus connects memory and CPU components.
•Used for transferring data, addresses, and control signals.
3. CPU divided into two main units
a. DPU (Data Processing Unit)
•ALU
•Accumulator (ACC)
•Register File (R1, R2, R3, etc.)
•Status Register (S, Z, AC, P, CY flags)
b. PCU (Program Control Unit)
• PC (Program Counter)
• IR (Instruction Register)
• Control Circuit/unit
• MAR (Memory Address Register)
• SP (Stack Pointer)
4. Memory Interface Registers
MBR (Memory Buffer Register) for data transfer between memory and CPU.
Architecture Summary
In Von Neumann Architecture:
CPU = ALU + Control Unit + Registers
Single memory stores both data and instructions
Fetch–Decode–Execute cycle is performed using
PC, IR, MAR, and MBR
All components communicate through a common
system bus
Instruction interpretation
It is the process where a CPU's control unit decodes and
executes machine-level instructions (0s and 1s) fetched from
memory
It involves interpreting the opcode (operation) and operands
(data location) within the instruction format to perform
actions, such as arithmetic or data transfers.
Key Aspects of Instruction Interpretation:
•The Cycle: This occurs during the Decode phase of the fetch-
decode-execute cycle. The control unit breaks down the
instruction in the instruction register (IR) to understand the
operation and required operands.
•Instruction Format: The layout of bits (opcode, addressing
mode, operands) is analyzed to determine how to retrieve
necessary data from registers or memory.
•Execution: Based on the interpretation, the control unit
sends signals to the Arithmetic Logic Unit (ALU) or registers
to execute the command (e.g., ADD, LOAD, STORE).
Basic
Operati
ng
PROGRAM
Principl
Address ADDR : Instruction
Bus e of: 81h (Opcode)
1050
External Memory
simple
1051 : 72h (Opcode)
RD 1052 containing prog for
CPU: 02h (Data) average of two nos.
1053 :76h (Opcode)
WR
Data Bus
System Bus
MAR IR Accumulator
R2
1050 81h E.g. R1
PC ID
1051 (To select 81st ALU
microprog.)
M/C cycle
Encoder Control signals like
ER1,ER2,EADD etc.
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Machine Cycle and Instruction Cycle
Machine cycle refers to basic operational steps that CPU performs to
execute an instruction.
The CPU is driven by internal clock. One machine cycle may take one or more
clock cycles.
One instruction cycle(Time taken to execute one instruction) needs
number of machine cycles.
Module 4 : Control Unit Design
• Implementation of Hardwired Control Unit
State Table Method: Every Microoperation block is associated with a state in a
state table. This state table contains entries like
STATE Input Instruction Code Combination
I1 I2 ………… Im
S1 S11 Z11 S12 Z12 S1m Z1m Sij: Next State to be triggered
S21 Z21 S2m Z2m
S2 S22 Z22 Zij: Control Signal to be generated
. when CU is in state of Si and
.
. instruction code initiated by
Sn
Sn1 Zn1
Sn2 Zn2
Snm Znm decoder is Ij
Amaya Pethe
Module 4 : Control Unit Design
• Implementation of Hardwired Control Unit
State Table Method
Advantages:
• Fast operation due to direct hardware implementation
• Efficient for simple instruction sets
Disadvantages:
• In modern processors, there is a vast number of instruction sets. Therefore, the
circuit becomes complicated to design
• If we make any modifications to the state table, then the large parts of the circuit
need to be changed.
• The state table hides useful information like loops and repeated patterns. Thus,
two states with the same behaviour may require different hardware.
• The final control unit implemented using minimized table and original state table
do not have one to one mapping so even expert designer also can not repair it
Amaya Pethe
Module 4 : Control Unit Design
• Implementation of Hardwired Control Unit
Delay Element Method
• Here the control unit behaviour is represented in the form of a flowchart.
• Each step in the flowchart represents a control signal that needs to be
produced for processing the instructions.
• If all the steps of the instructions are performed, this means the instruction is
executed completely.
• Control signals perform micro-operations, and each micro-operation
requires one T-state.
• For the micro-operations which are independent, they are required to be
performed in different T-state. Therefore, for every consecutive control
signal an exactly 1-state delay is required, which can be produced with the
help of D FF.
• Therefore. D Flip-Flops are inserted between every two consecutive control
signals. Amaya Pethe
Module 4 : Control Unit Design
Delay Element Method
[Link] Control Signals must provide time seperation using Delay
Element-D FF
Amaya Pethe
Module 4 : Control Unit Design
Delay Element Method
[Link] of Control Lines merging together will be implemented using
multi-input OR gate
Amaya Pethe
Module 4 : Control Unit Design
Delay Element Method
3. Decision Box of HDL flow chart is implemented using a pair of AND gate
Amaya Pethe
Module 4 : Control Unit Design
Delay Element Method
Advantage –
• This method has a logical approach ,since there is one to one mapping between
original HDL flowchart and implemented control units, debugging and repairing is
easy
• For the common control signals which need to be generated in every instruction,
for them only one circuitry can be designed .
• Easy implementation using only elements like AND gate OR gate and D FF
Drawback –
• As the number of instructions increases , the number of D FF for generating delay is
increased, so overall circuit complexity and cost increases.
• It does not have supervisory control signals to define when its operation should
start or STOP
• It does not provides precise control information like how long it should be in
enabled codition
Amaya Pethe
C1 Pick up Door
C2 Orient Door
Check Margin
No No
Check Drill
Yes Yes
Tighten Screw C3 C4 C5 Put Reject Tag
Drill &Tighten Screw
C6
Rotate Conveyor Belt
Amaya Pethe
Amaya Pethe
Module 4 : Control Unit Design
Sequence Counter Method
Amaya Pethe