COMPUTER ORGANIZATION AND DESIGN

The Hardware/Software Interface

Chapter 1

Understanding computer
performance
 §1.6 Performance
Defining Performance
◼ Which airplane has the best performance?

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Response Time and Throughput
◼ Response time
◼ How long it takes to do a task
◼ Throughput
◼ Total work done per unit time
◼ e.g., tasks/transactions/… per hour

◼ Example: How are response time and throughput

affected by
◼ Replacing the processor with a faster version?
◼ Adding more processors?

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Relative Performance
◼ Define Performance = 1/Execution Time
◼ “X is n time faster than Y”
Performance X Performance Y
= Execution time Y Execution time X = n

◼ Example: time taken to run a program

◼ 10s on A, 15s on B
◼ Execution TimeB / Execution TimeA
= 15s / 10s = 1.5
◼ So A is 1.5 times faster than B
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Measuring Execution Time
◼ Elapsed time
◼ Total response time, including all aspects
◼ Processing, I/O, OS overhead, idle time
◼ Determines system performance
◼ CPU time
◼ Time spent processing a given job
◼ Discounts I/O time, other jobs’ shares
◼ Comprises user CPU time and system CPU
time
◼ Different programs are affected differently by
CPU and system performance
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CPU Clocking
◼ Operation of digital hardware governed by a
constant-rate clock
Clock period

Clock (cycles)

Data transfer
and computation
Update state

◼ Clock period: duration of a clock cycle

◼ e.g., 250ps = 0.25ns = 250×10–12s
◼ Clock frequency (rate): cycles per second
◼ e.g., 4.0GHz = 4000MHz = 4.0×109Hz
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CPU Time
CPU Time = CPU Clock Cycles Clock Cycle Time
CPU Clock Cycles
=
Clock Rate
◼ Performance improved by
◼ Reducing number of clock cycles
◼ Increasing clock rate
◼ Hardware designer must often trade off clock
rate against cycle count

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CPU Time Example
◼ Computer A: 2GHz clock, 10s CPU time
◼ Designing Computer B
◼ Aim for 6s CPU time
◼ Can do faster clock, but causes 1.2 × clock cycles
◼ How fast must Computer B clock be?
Clock CyclesB 1.2  Clock CyclesA
Clock RateB = =
CPU Time B 6s
Clock CyclesA = CPU Time A  Clock Rate A
= 10s  2GHz = 20  10 9
1.2  20  10 9 24  10 9
Clock RateB = = = 4GHz
6s 6s
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Instruction Count and CPI
Clock Cycles = Instruction Count  Cycles per Instruction
CPU Time = Instruction Count  CPI  Clock Cycle Time
Instruction Count  CPI
=
Clock Rate
◼ Instruction Count for a program
◼ Determined by program, ISA and compiler
◼ Average cycles per instruction
◼ Determined by CPU hardware
◼ If different instructions have different CPI
◼ Average CPI affected by instruction mix

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CPI Example
◼ Computer A: Cycle Time = 250ps, CPI = 2.0
◼ Computer B: Cycle Time = 500ps, CPI = 1.2
◼ Same ISA
◼ Which is faster, and by how much?
CPU Time = Instruction Count  CPI  Cycle Time
A A A
= I  2.0  250ps = I  500ps A is faster…
CPU Time = Instruction Count  CPI  Cycle Time
B B B
= I  1.2  500ps = I  600ps
CPU Time
B = I  600ps = 1.2
…by this much
CPU Time I  500ps
A
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CPI in More Detail
◼ If different instruction classes take different
numbers of cycles
n
Clock Cycles =  (CPIi  Instruction Counti )
i=1

◼ Weighted average CPI

n
Clock Cycles Instruction Count i
CPI = = ෍ CPIi ×
Instruction Count Instruction Count
i=1

Relative frequency

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CPI Example
◼ Alternative compiled code sequences using
instructions in classes A, B, C

Class A B C
CPI for class 1 2 3
IC in sequence 1 2 1 2
IC in sequence 2 4 1 1

◼ Sequence 1: IC = 5 ◼ Sequence 2: IC = 6
◼ Clock Cycles ◼ Clock Cycles
= 2×1 + 1×2 + 2×3 = 4×1 + 1×2 + 1×3
= 10 =9
◼ Avg. CPI = 10/5 = 2.0 ◼ Avg. CPI = 9/6 = 1.5
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CPI Example

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More Examples
Consider three different processors P1, P2, and P3 executing
the same instruction set. P1 has a 3 GHz clock rate and a
CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3
has a 4.0 GHz clock rate and has a CPI of 2.2.
❑ Which processor has the highest performance expressed in
instructions per second?

❑ If the processors each execute a program in 10 seconds, find

the number of cycles and the number of instructions.

❑ We are trying to reduce the execution time by 30% but this

leads to an increase of 20% in the CPI. What clock rate should
we have to get this time reduction?

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More Examples
Consider three different processors P1, P2, and P3 executing
the same instruction set. P1 has a 3 GHz clock rate and a
CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3
has a 4.0 GHz clock rate and has a CPI of 2.2.
❑ Which processor has the highest performance expressed in
instructions per second?

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More Examples
Consider three different processors P1, P2, and P3 executing
the same instruction set. P1 has a 3 GHz clock rate and a
CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3
has a 4.0 GHz clock rate and has a CPI of 2.2.

❑ If the processors each execute a program in 10 seconds, find

the number of cycles and the number of instructions.

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More Examples
Consider three different processors P1, P2, and P3 executing
the same instruction set. P1 has a 3 GHz clock rate and a
CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3
has a 4.0 GHz clock rate and has a CPI of 2.2.
❑ We are trying to reduce the execution time by 30% but this
leads to an increase of 20% in the CPI. What clock rate should
we have to get this time reduction?

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More Examples
Consider two different implementations of the same instruction
set architecture. The instructions can be divided into four
classes according to their CPI (class A, B, C, and D). P1 with a
clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 3, and P2 with a
clock rate of 3 GHz and CPIs of 2, 2, 2, and 2.
Given a program with a dynamic instruction count of 1x10^6
instructions divided into classes as follows: 10% class A, 20%
class B, 50% class C, and 20% class D.

❑ which implementation is faster?

❑ What is the global CPI for each implementation?

❑ Find the clock cycles required in both cases.

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More Examples
Consider two different implementations of the same instruction
set architecture. The instructions can be divided into four
classes according to their CPI (class A, B, C, and D). P1 with a
clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 3, and P2 with a
clock rate of 3 GHz and CPIs of 2, 2, 2, and 2.
Given a program with a dynamic instruction count of 1x10^6
instructions divided into classes as follows: 10% class A, 20%
class B, 50% class C, and 20% class D.

❑ which implementation is faster?

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More Examples
Consider two different implementations of the same instruction
set architecture. The instructions can be divided into four
classes according to their CPI (class A, B, C, and D). P1 with a
clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 3, and P2 with a
clock rate of 3 GHz and CPIs of 2, 2, 2, and 2.
Given a program with a dynamic instruction count of 1x10^6
instructions divided into classes as follows: 10% class A, 20%
class B, 50% class C, and 20% class D.

❑ What is the global CPI for each implementation?

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More Examples
Consider two different implementations of the same instruction
set architecture. The instructions can be divided into four
classes according to their CPI (class A, B, C, and D). P1 with a
clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 3, and P2 with a
clock rate of 3 GHz and CPIs of 2, 2, 2, and 2.
Given a program with a dynamic instruction count of 1x10^6
instructions divided into classes as follows: 10% class A, 20%
class B, 50% class C, and 20% class D.

❑ Find the clock cycles required in both cases.

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More Examples
Compilers can have a profound impact on the performance of an
application. Assume that for a program, compiler A results in a dynamic
instruction count of 1x10^9 and has an execution time of 1.1 s, while
compiler B results in a dynamic instruction count of 1.2x10^9 and an
execution time of 1.5 s.
1) Find the average CPI for each program given that the processor has a
clock cycle time of 1 ns.

2) Assume the compiled programs run on two different processors. If the

execution times on the two processors are the same, how much faster is
the clock of the processor running compiler A’s code versus the clock of
the processor running compiler B’s code?

3) A new compiler is developed that uses only 6x10^8 instructions and

has an average CPI of 1.1. What is the speedup of using this new
compiler versus using compiler A or B on the original processor?

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More Examples
Compilers can have a profound impact on the performance of an
application. Assume that for a program, compiler A results in a dynamic
instruction count of 1x10^9 and has an execution time of 1.1 s, while
compiler B results in a dynamic instruction count of 1.2x10^9 and an
execution time of 1.5 s.
1) Find the average CPI for each program given that the processor has a
clock cycle time of 1 ns.

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More Examples
Compilers can have a profound impact on the performance of an
application. Assume that for a program, compiler A results in a dynamic
instruction count of 1x10^9 and has an execution time of 1.1 s, while
compiler B results in a dynamic instruction count of 1.2x10^9 and an
execution time of 1.5 s.

2) Assume the compiled programs run on two different processors. If the

execution times on the two processors are the same, how much faster is
the clock of the processor running compiler A’s code versus the clock of
the processor running compiler B’s code?

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More Examples
Compilers can have a profound impact on the performance of an
application. Assume that for a program, compiler A results in a dynamic
instruction count of 1x10^9 and has an execution time of 1.1 s, while
compiler B results in a dynamic instruction count of 1.2x10^9 and an
execution time of 1.5 s.

3) A new compiler is developed that uses only 6x10^8 instructions and

has an average CPI of 1.1. What is the speedup of using this new
compiler versus using compiler A or B on the original processor?

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Performance Summary
The BIG Picture

Instructions Clock cycles Seconds

CPU Time =  
Program Instruction Clock cycle

◼ Performance depends on
◼ Algorithm: affects IC, possibly CPI
◼ Programming language: affects IC, CPI
◼ Compiler: affects IC, CPI
◼ Instruction set architecture: affects IC, CPI, Tc

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 §1.12 Concluding Remarks
Concluding Remarks
◼ Cost/performance is improving
◼ Due to underlying technology development
◼ Hierarchical layers of abstraction
◼ In both hardware and software
◼ Instruction set architecture
◼ The hardware/software interface
◼ Execution time: the best performance
measure
◼ Power is a limiting factor
◼ Use parallelism to improve performance
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