85 · 8086 · 8051
CONTENTS
UNIT I — 8085 Architecture, 8086 Architecture & Segmentation
UNIT II — 8086 Design, Addressing, Interrupts, Multiprogramming
EXTRA — Min/Max Mode, Bus Architecture, Multiprocessor Configs
LABS — All 11 Experiment Programs with Comments
UNIT I — 12 Hours
1. BASICS OF 8085 MICROPROCESSOR
Architecture Overview
The Intel 8085 is an 8-bit microprocessor with a 16-bit address bus (64 KB addressable memory) and an 8-bit data bus. It
operates at up to 3 MHz and requires a single +5V supply.
Key Registers
Register Purpose
Accumulator (A) 8-bit; primary register for all ALU operations
B, C, D, E, H, L General purpose 8-bit registers; pair as BC, DE, HL
PC (Program Counter) 16-bit; holds address of next instruction
SP (Stack Pointer) 16-bit; points to top of stack
Flags Register 5 flags: S, Z, AC, P, CY
PIN Description (key pins)
Pin Description
AD0–AD7 Multiplexed lower address / data bus
A8–A15 Higher address bus (not multiplexed)
ALE Address Latch Enable — HIGH = address on AD0-AD7
RD / WR Read / Write control (active LOW)
RESET IN Resets PC to 0000H
INTR Maskable interrupt request
TRAP Non-maskable, highest priority interrupt
RST 5.5/6.5/7.5 Vectored maskable interrupts
HOLD / HLDA DMA request / acknowledge
SID / SOD Serial input / output data
Instruction Set Categories
Category Instructions
Data Transfer MOV, MVI, LDA, STA, LHLD, SHLD, LDAX, STAX, XCHG
Arithmetic ADD, ADC, ADI, ACI, SUB, SBB, SUI, SBI, INR, DCR, DAD
Logical ANA, ORA, XRA, CMP, ANI, ORI, XRI, CPI, RLC, RRC, RAL, RAR
Branch JMP, JC, JNC, JZ, JNZ, CALL, RET, RST n, PCHL
Machine Control HLT, NOP, DI, EI, RIM, SIM
Addressing Modes (8085)
Mode Example
Immediate Operand in instruction itself → MVI A, 05H
Register Data in register → MOV A, B
Direct 16-bit address in instruction → LDA 2000H
Register Indirect HL pair holds memory address → MOV A, M
Implicit Operand implied by opcode → RLC, HLT
Interrupts in 8085
Interrupt Details
TRAP Non-maskable, highest priority, vector 0024H, edge+level triggered
RST 7.5 Maskable, vector 003CH, edge triggered
RST 6.5 Maskable, vector 0034H, level triggered
RST 5.5 Maskable, vector 002CH, level triggered
INTR Maskable, lowest priority, no fixed vector
■■ IMPORTANT: Priority order: TRAP > RST7.5 > RST6.5 > RST5.5 > INTR
2. INTRODUCTION TO 8086 MICROPROCESSOR
Architecture Overview
The Intel 8086 is a 16-bit microprocessor with a 20-bit address bus (1 MB addressable memory) and 16-bit data bus. It
has two internal units: BIU (Bus Interface Unit) — handles all bus operations, address generation, instruction queue; and EU
(Execution Unit) — decodes and executes instructions. This pipelining allows fetch and execute to overlap.
Registers of 8086
Register Purpose
AX (AH+AL) Accumulator — used in I/O, multiply, divide
BX (BH+BL) Base register — used in memory addressing
CX (CH+CL) Count register — loop counter, shift count
DX (DH+DL) Data register — I/O port address, MUL/DIV overflow
SI Source Index — string source address
DI Destination Index — string destination address
BP Base Pointer — stack frame access
SP Stack Pointer — top of stack
IP Instruction Pointer — next instruction offset
CS/DS/SS/ES Segment registers — base of each segment
FLAGS 16-bit status + control flags
Physical Address Calculation
8086 uses a segmented memory model. Since registers are 16-bit but address bus is 20-bit, a 20-bit physical address is
formed as:
Physical Address = Segment Register × 10H + Offset
Example: DS = 15A1H, Offset = 0100H
Physical = 15A10H + 0100H = 15B10H
Memory Segmentation
Segment Role
CS — Code Segment Holds program code; IP gives offset; used during instruction fetch
DS — Data Segment Holds program data; SI/BX/DI give offset
SS — Stack Segment Holds stack; SP and BP give offset
ES — Extra Segment Extra data segment; used by string instructions for destination
■ TIP: Each segment can be up to 64 KB. Segments can overlap.
8086 System Bus Architecture
The 8086 has three buses: (1) Address Bus — 20-bit, unidirectional, carries memory/IO addresses; (2) Data Bus — 16-bit,
bidirectional, carries data; (3) Control Bus — includes RD, WR, ALE, BHE (Bus High Enable), M/IO, DT/R, DEN, HOLD,
HLDA.
UNIT II — 10 Hours
3. 8086 ADDRESSING MODES & INSTRUCTION SET
Addressing Modes (8086)
Mode Example
Immediate MOV AX, 1234H — data in instruction
Register MOV AX, BX — data between registers
Direct MOV AX, [2000H] — address in instruction
Register Indirect MOV AX, [BX] — address in register
Based MOV AX, [BX+10H] — base reg + displacement
Indexed MOV AX, [SI+10H] — index reg + displacement
Based Indexed MOV AX, [BX+SI] — base + index
Based Indexed + Disp MOV AX, [BX+SI+10H] — base + index + offset
Important Instructions
Instruction Action
MOV dst, src Copy data
ADD dst, src dst = dst + src
SUB dst, src dst = dst – src
MUL src AX = AL × src (8-bit); DX:AX = AX × src (16-bit)
DIV src AL = AX / src, AH = remainder (8-bit)
INC / DEC Increment / Decrement by 1
CMP dst, src Subtract without storing; sets flags
JMP / Jxx Unconditional / conditional jump
LOOP label Decrement CX; jump if CX ≠ 0
PUSH / POP Save / restore 16-bit register to/from stack
CALL / RET Call subroutine / return
INT n Software interrupt
MOV AX,0x4C00 / INT 21H DOS exit program
LEA reg, mem Load effective address into register
MOVSB / MOVSW Move string byte/word DS:SI → ES:DI, auto-adjust SI, DI
REP Repeat string instruction CX times
XCHG dst, src Swap two operands
4. ASSEMBLER DIRECTIVES
Assembler directives are pseudo-instructions — they guide the assembler but generate no machine code.
Directive Meaning
ORG addr Set the origin (starting address) of code
DB / DW / DD Define Byte / Word / Double-word data
EQU Assign a constant name (COUNT EQU 10)
SEGMENT/ENDS Define a segment block
ASSUME Tell assembler which segment register maps to which segment
PROC/ENDP Define a procedure (subroutine)
END Mark end of source file
PUBLIC/EXTRN Declare symbols visible to/from other modules
5. INTERRUPTS IN 8086 & ISR
Interrupt/Instruction Description
INTR Maskable hardware interrupt; can be disabled by CLI
NMI Non-maskable; always responded; highest priority
INT n (0–255) Software interrupts; vector table at 0000:0000–0000:03FF
INTO Interrupt on overflow
IRET Return from interrupt service routine
CLI / STI Clear / Set Interrupt Flag (disable / enable maskable)
ISR (Interrupt Service Routine): When an interrupt occurs, the CPU pushes FLAGS, CS, IP onto stack, loads CS:IP from
interrupt vector table, executes ISR, then executes IRET to restore the original context.
6. BYTE AND STRING MANIPULATION
Instruction Action
MOVSB Move byte: [ES:DI] ← [DS:SI]; SI++, DI++ (or -- if DF=1)
MOVSW Move word: 2 bytes; SI+=2, DI+=2
REP MOVSB Repeat MOVSB CX times — block copy
CMPSB Compare bytes at DS:SI and ES:DI; set flags
SCASB Scan string: AL vs [ES:DI]
LODSB Load AL from DS:SI; SI++
STOSB Store AL to ES:DI; DI++
CLD / STD Clear/Set Direction Flag (DF=0 → forward, DF=1 → backward)
7. SYSTEM DESIGN — I/O, MULTIPROGRAMMING & MULTIPROCESSOR
I/O Programming
Method Detail
IN AL, port Read byte from I/O port (8-bit address)
IN AX, port Read word from I/O port
OUT port, AL Write byte to I/O port
IN AL, DX Read from port addressed by DX (16-bit port address)
Memory-mapped I/O I/O devices treated as memory locations; no IN/OUT needed
Multiprogramming Introduction
Multiprogramming allows multiple programs to reside in memory simultaneously. The CPU switches between them,
maximising utilisation. The 8086 supports this via its segmented memory (each program in its own segments) and the use of
hardware interrupts for context switching.
8. MINIMUM MODE vs MAXIMUM MODE ■
The 8086 operates in two modes selected by pin MN/MX:
Feature Minimum Mode vs Maximum Mode
MN/MX pin tied to VCC (+5V) → Minimum Mode | GND → Maximum Mode
System size Small, single-processor | Large, multi-processor
Bus control 8086 itself generates all bus control signals
External 8288 Bus Controller generates bus signals
Control pins M/IO, RD, WR, INTA, ALE, DEN, DT/R, HOLD, HLDA generated by 8086
S0,S1,S2 status pins sent to 8288; QS0,QS1 for queue status
Use case Stand-alone systems, simple designs
Multiprocessor systems with 8087 (FPU), 8089 (IOP)
Minimum Mode Signals (generated by 8086 itself)
Signal Description
M/IO HIGH = memory access, LOW = I/O access
RD Read signal (active LOW)
WR Write signal (active LOW)
ALE Address Latch Enable — demultiplexes address from AD0–AD15
DEN Data Enable — enables data bus transceiver
DT/R Data Transmit/Receive — direction of data bus transceiver
HOLD DMA request input
HLDA Hold Acknowledge output
INTA Interrupt Acknowledge output
Maximum Mode Signals
Signal Description
S0, S1, S2 Status signals sent to 8288 Bus Controller
QS0, QS1 Queue Status — tracks instruction queue activity
LOCK Bus lock — prevents other bus masters from accessing bus
RQ/GT0, RQ/GT1 Request/Grant for DMA with co-processors
8288 Bus Controller Decodes S0–S2 to generate MRDC, MWTC, IORC, IOWC, INTA, ALE, DEN, DT/R
■■ IMPORTANT: Key exam point: In MIN mode, 8086 directly controls the bus. In MAX mode, 8288 Bus Controller takes
over bus control using S0/S1/S2 status signals.
9. MULTIPROCESSOR CONFIGURATIONS
In maximum mode, 8086 can work with co-processors:
Component Role
8087 (Numeric Co-processor / FPU) Handles floating point arithmetic; shares bus with 8086
8089 (I/O Processor) Dedicated I/O processor; offloads I/O tasks from 8086
Tightly Coupled Co-processors share bus and memory with 8086
Loosely Coupled Multiple processors with separate buses; communicate via shared memory
8086 in multiprocessor Uses LOCK prefix to ensure atomic bus access; RQ/GT pins for bus arbitration
10. FLAGS REGISTER (Complete)
Flag Meaning
CF — Carry Flag Set if carry out of MSB (addition) or borrow into MSB (subtraction)
PF — Parity Flag Set if low byte of result has even number of 1-bits
AF — Auxiliary Carry Carry from bit 3 to bit 4; used in BCD arithmetic (DAA/DAS)
ZF — Zero Flag Set if result = 0
SF — Sign Flag Set if MSB of result = 1 (negative number)
TF — Trap Flag Set → single-step mode for debugging (INT 1 after each instruction)
IF — Interrupt Flag Set → maskable interrupts enabled (STI); Clear → disabled (CLI)
DF — Direction Flag 0 = string ops auto-increment SI/DI; 1 = auto-decrement
OF — Overflow Flag Set if signed arithmetic result too large for destination
LAB EXPERIMENTS — All 11 Programs
Exp 1: Addition of Two 8-bit Numbers (8085)
Procedure: Load both numbers into registers, ADD them, store result.
MVI A, 25H ; Load first number into Accumulator
MVI B, 15H ; Load second number into B
ADD B ; A = A + B
STA 3000H ; Store result at memory 3000H
HLT ; Stop
Exp 2: Addition of Two 16-bit Numbers (8085)
Procedure: Use HL and DE register pairs. Add using DAD instruction.
LXI H, 2A3BH ; HL = first 16-bit number
LXI D, 1C4EH ; DE = second 16-bit number
DAD D ; HL = HL + DE
SHLD 3000H ; Store 16-bit result at 3000H-3001H
HLT
Exp 3: Transfer 10 Bytes: 2000H → 2100H (8085)
Procedure: Use LXI to load source/destination, loop 10 times using DCR and JNZ.
LXI H, 2000H ; HL = source address
LXI D, 2100H ; DE = destination address
MVI C, 0AH ; Counter = 10
LOOP:
MOV A, M ; Load byte from [HL]
STAX D ; Store byte to [DE]
INX H ; HL++
INX D ; DE++
DCR C ; Counter--
JNZ LOOP ; Repeat if C != 0
HLT
Exp 4: Sum 1 to 10 (8086) — Store at 0000:1000H
Procedure: Program at 15A1:0100. Use LOOP instruction. Result in AX stored at 0000:1000H.
MOV AX, 0000H
MOV DS, AX ; DS = 0000H (result segment)
MOV AX, 0000H ; AX = running sum
MOV CX, 000AH ; CX = 10 (loop counter)
MOV BX, 000AH ; BX = current number (start from 10, down)
SUM_LOOP:
ADD AX, BX ; AX = AX + BX
DEC BX ; BX--
LOOP SUM_LOOP ; CX--; jump if CX != 0
MOV [1000H], AX ; Store result at DS:1000H = 0000:1000H
MOV AX, 4C00H
INT 21H ; Exit
Exp 5: Multiply Two 16-bit Numbers (8086)
Procedure: Use MUL instruction. 16×16 = 32-bit result in DX:AX.
MOV AX, 1234H ; First operand in AX
MOV BX, 0005H ; Second operand in BX
MUL BX ; DX:AX = AX * BX (32-bit result)
; DX = high 16 bits, AX = low 16 bits
MOV [3000H], AX ; Store low word
MOV [3002H], DX ; Store high word
HLT
Exp 6: Divide Two Numbers (8086)
Procedure: Use DIV instruction. Dividend in DX:AX, divisor in BX. Quotient in AX, remainder in DX.
MOV DX, 0000H ; Clear DX (high word of dividend)
MOV AX, 0064H ; AX = 100 (dividend)
MOV BX, 0007H ; BX = 7 (divisor)
DIV BX ; AX = quotient (14), DX = remainder (2)
MOV [3000H], AX ; Store quotient
MOV [3002H], DX ; Store remainder
HLT
Exp 7: Sort 16-bit Numbers — Ascending & Descending (8086)
Procedure: Bubble sort using nested loops. Compare with CMP and XCHG to swap.
; Data assumed at DS:2000H, count = 5
MOV CX, 0005H ; Total elements
DEC CX ; Outer loop = N-1
OUTER:
PUSH CX
MOV SI, 2000H ; SI = start of array
INNER:
MOV AX, [SI]
MOV BX, [SI+2]
CMP AX, BX
JLE NO_SWAP ; For ascending: skip if AX <= BX
XCHG AX, BX ; Swap
MOV [SI], AX
MOV [SI+2], BX
NO_SWAP:
ADD SI, 2 ; Move to next element
LOOP INNER
POP CX
LOOP OUTER
; For DESCENDING: change JLE to JGE
HLT
Exp 8: Block Data Transfer (8086)
Procedure: Move block of data using MOVSW/MOVSB with REP prefix. DS:SI = source, ES:DI = destination.
MOV AX, 1000H
MOV DS, AX ; DS = 1000H (source segment)
MOV AX, 2000H
MOV ES, AX ; ES = 2000H (destination segment)
MOV SI, 0000H ; Source offset
MOV DI, 0000H ; Destination offset
MOV CX, 000AH ; 10 bytes to transfer
CLD ; DF=0, auto-increment SI and DI
REP MOVSB ; Move CX bytes from DS:SI to ES:DI
HLT
Exp 9: Addition & Subtraction — Store at 3012H (8051)
Procedure: Load operands in R0/R1, add using ADD instruction, store using MOVX.
MOV R0, #25H ; First number
MOV R1, #10H ; Second number
; ADDITION
MOV A, R0
ADD A, R1 ; A = R0 + R1
MOV DPTR, #3012H
MOVX @DPTR, A ; Store sum at 3012H
; SUBTRACTION
MOV A, R0
CLR C ; Clear carry before subtract
SUBB A, R1 ; A = R0 - R1
INC DPTR ; DPTR = 3013H
MOVX @DPTR, A ; Store difference
SJMP $ ; Loop forever (stop)
Exp 10: Multiplication — Store at 3012H (8051)
Procedure: Use MUL AB instruction. A = low byte, B = high byte of result.
MOV A, #0CH ; A = 12 (multiplicand)
MOV B, #05H ; B = 5 (multiplier)
MUL AB ; B:A = A * B (16-bit result)
; A = low byte, B = high byte
MOV DPTR, #3012H
MOVX @DPTR, A ; Store low byte at 3012H
INC DPTR
MOV A, B
MOVX @DPTR, A ; Store high byte at 3013H
SJMP $
Exp 11: Division — Store at 3012H (8051)
Procedure: Use DIV AB. A = quotient, B = remainder.
MOV A, #64H ; A = 100 (dividend)
MOV B, #07H ; B = 7 (divisor)
DIV AB ; A = quotient (14), B = remainder (2)
MOV DPTR, #3012H
MOVX @DPTR, A ; Store quotient at 3012H
INC DPTR
MOV A, B
MOVX @DPTR, A ; Store remainder at 3013H
SJMP $
QUICK REVISION CARD — Common Exam Points
8085 memory 64 KB | 8086 memory: 1 MB
8085 data bus 8-bit | 8086 data bus: 16-bit
Physical address Segment × 10H + Offset
TRAP Non-maskable, highest priority in 8085
NMI Non-maskable in 8086
MN/MX = VCC Minimum mode (single processor)
MN/MX = GND Maximum mode (multiprocessor, 8288 Bus Controller)
MUL BX (8086) DX:AX = AX × BX
DIV BX (8086) AX = quotient, DX = remainder
MUL AB (8051) B:A = A × B
DIV AB (8051) A = quotient, B = remainder
MOVX (8051) Access external RAM
MOV (8051) Access internal RAM / SFRs
REP MOVSB Block transfer, CX times, DS:SI → ES:DI
CLD DF=0, string ops go forward (increment)
STD DF=1, string ops go backward (decrement)
Bubble sort swap Use XCHG; JLE for ascending, JGE for descending
DAD D (8085) HL = HL + DE (16-bit addition)
Stack (8085/6) SP decrements by 2 on PUSH, increments by 2 on POP
IRET (8086) Pops IP, CS, FLAGS — returns from ISR
All the best for your Viva! You've got this. ■