MODULE I-POWER

POWER SEMICONDUCTOR DEVICES

Introduction to Power Electronics

Refer Class notes

SCR (Silicon Controlled Rectifier) : Generally Thyristor

• An SCR is so called because silicon is used for its construction and its operation as a
rectifier can be controlled.

• Unlike the diode, a thyristor blocks the current flow from anode to cathode until it is
triggered into conduction by a proper gate signal between gate and cathode terminal.

Q1: Explain the basic construction of an SCR.

Four layer, three junction, p-n--p-n semiconductor switching device

4 layers of alternate p-type
type and nn-type
type silicon semiconductors forming three junctions J1, J2
and J3

3 terminals
The terminal connected to outer p region is called the Anode
The terminal connected to outer n region is called the Cathode
The terminal connected to inner p region is called Gate
Mounted onto heat sinks (via Threaded stud) for cooling
 Q2: Explain the static V-II characteristics of a thyristor.

An elementary circuit diagram for obtaining static V

V-I characteristics:

A thyristor has three basic modes of operation

operation:

Reverse blocking mode

Forward blocking mode (off state)

Forward conduction mode (on state)

Reverse blocking mode

When cathode is made +ve w.r.t anode (switch S open, ie, Ig=0),
Junction J2 is forward biased, J1 and J3 are reverse biased.

A small leakage current of the order of a few milli

milli-amperes flows.

If the reverse voltage is increased, above reverse breakdown voltage VBR, an avalanche
occur at J1 and J3

Reverse current increases rapidly

Forward blocking mode

When anode is +ve w.r.t cathode,

J1 and J3 are forward biased
biased;
J2 is reverse biased

A small current called forward leakage current flows

Thyristor
hyristor acts as an open switch
Forward conduction mode

When anode to cathode forward voltage is increased above a voltage called forward
break-over
over voltage VBO (with gate circuit open),

Reverse
everse biased junction J2 will have an avalanche breakdown

Thyristor gets turned on (operating point shifts from M to N)

NK represents the forward conduction mode

In conduction mode, the SCR offers very low impedance and very low on state voltage
(1-2 V)

When a positive gate pulse Ig1 applied between gate and cathode,
Operating point shifts from forward blocking to conduction state (Thyristor
hyristor tuns on) at a
smaller break over voltage VBO1

Q3: Explain the turn on (Triggering) methods of an SCR.

1. Forward voltage triggering

When forward voltage applied between anode and cathode (gategate circuit open),
open
Junction
unction J2 is reverse biased
biased, depletion layer formed across J2
 The width of this layer decreases with an increase in anode - cathode voltage

If forward voltage across anode-cathode is gradually increased, above a voltage called

forward break-over voltage,
• Depletion layer across J2 vanishes by avalanche breakdown.
• As other junction J1, J3 are already forward biased, breakdown of junction J2
allows free movement of carriers across three junctions
• A large forward anode current flows; Thyristor starts conduction.

2. Gate triggering

Most common, simple and efficient method of triggering an SCR

When turn of a thyristor required, a +ve gate voltage between gate and cathode is applied.
Inner p layer (where Gate is connected) is flooded with electrons from the cathode.

As the thyristor is forward biased, some of these electrons reaches junction J2

As a result width of the depletion layer near junction J2 is reduced

Junction J2 to break down at an applied voltage lower than the forward break-over
voltage VBO and the SCR starts conduction.

If the gate current removed before the anode current attains a value, called latching
current the device will turn off again.

3. dv/dt triggering

With forward voltage across anode and cathode, the junction is J2 reverse biased

Due to space charge existing in the depletion region, J2 behaves like a capacitance

( )
Charging Current = = = + .

As the junction capacitance is almost constant, is zero

Thus =

If the rise of forward voltage is high, the charging current would be more

Thus, if forward voltage is suddenly applied, a charging current through junction

capacitance will turn on the SCR.
4. Temperature triggering (Thermal triggering)

During forward blocking, most of the applied voltage appears across reverse biased
junction J2

This voltage across J2, associated with leakage current, would rise the temperature of
this junction
With increase in temperature, width of depletion layer decreases

This further leads to more leakage current and therefore more junction temperature

With this cumulative process at some high temperature, depletion layer of reverse
biased junction vanishes and the device gets turned on

5. Light triggering

For light triggered SCR, a recess is made in the inner p layer

When a niche is made to incident on this recess, free charge carriers are generated just
like when gate signal is applied between gate and cathode.

The pulse of light of appropriate wavelength is guided by optical fibers

Such a thyristor is known as light activated SCR (LASCR)

Q4: Explain the terms Latching current and Holding Current of an SCR.

Once the thyristor starts conduction by gate triggering, if the gate current is removed, the
conduction of current from anode to cathode is unaffected.

However if the gate current removed, before rising the anode current attains a value,
called latching current the device will turn off again.

The latching current may be defined as the minimum value of anode current which it must
attain during turn on process to maintain conduction when gate signal is removed

Once the thyristor is conducting, gate loses control

The thyristor can be turned off only if the forward current falls below a low level current
called holding current

The holding current may be defined as the minimum value of anode current below which it
must fall for turning off the thyristor
 The latching current is higher than holding current (2 to 3 times)

The latching current is associated with the turn on process and holding current with
turn off process

Q5: Explain the Two transistor analogy of an SCR.

(First two triggering methods in next question may be added if asked for 10 marks)
Two-transistor model is obtained by bisecting the two middle layers of the SCR in to
two separate halves.

Junction J1-J2 and J2-J3 can be considered to constitute pnp and npn transistors
separately

For transistor Q1:

Emitter current = ; Collector current =

= +
For transistor Q2:
Emitter current = ; Collector current =

= +

= +
=( + ) +( + )

But, = +
 ! "#$% ! "#$
Substituting, =
%&( % ! )

For a silicon transistor, current gain α is very small at low emitter current

With an increase in emitter current, α build up rapidly

With gate Ig=0 and with thyristor forward biased, (α1 + α2) is very small

If by some means the emitter current of two component transistors can be increased
so that α1 + α2 approaches 1,
Anode current tends to become infinity (As per equation for Ia), thereby turning on
the device

Q6: Explain triggering methods of SCR based on two transistor analogy.

(May be asked separately or combined)

In two transistor model, the SCR is proposed as a combination of a pnp and npn
transistor.

! "#$% ! "#$
Anode current, = Where and are the common base
%&( % ! )
current gains of the two transistors proposed.
All triggering methods are the methods of making ( + ) approach unity.

(i) Gate triggering

With forward voltage across anode and cathode and with gate current Ig=0, anode
current equal to the forward leakage current ( + ) ( forward blocking state)
 Now a sufficient gate current is applied

This gate current = the base current and emitter current of transistor Q2, Ig = IB2 = Ik

With the establishment of emitter current Ik of Q2 current gain α2 of Q2 increases and

causes the existence of collector current Ic2=β2IB2 = β2Ig

IC2 serves as the base current IB1 of transistor Q1

With the flow of IB1, collector current IC1 of Q1 comes into existence.

Emitter current Ia of Q1 establishes and this causes current gain α1 to rise

Now current Ig+Ic1 act as the base current of Q2 and therefore its emitter current rises.

Current gain α2 eventually rises further

This regenerative or positive feedback effect causes α1 + α2 to grow towards unity

As a consequence, anode current begins to grow towards a larger value.

When regeneration has grown sufficiently, gate current can be withdrawn.

(ii) Forward voltage triggering

If the forward anode to cathode voltage is increased the VCE of both the transistors are
also increased

As a result the leakage current at the middle junction J2 (which are also the collector
current of Q2 and Q1) increases

With increase in collector currents Ic1 and Ic2, emitter currents of the two transistors
also increases causing α1 + α2 to approaches unity

This leads to the conduction of the device due to regenerative action

(iii) dv/dt Triggering

The reverse biased junction J2 behaves like a capacitor because of the space charge
present there

Let the capacitance of the junction be Cj

Then charging current across the junction is given by i=Cj*(dVa/dt)

 This charging current across junction J2 is the collector current of Q2 and Q1

Currents Ic2 and Ic1 will induce emitter current in Q2, Q1

If dVa/dt is large, the emitter current will be large and as a result α1 + α2 will
approaches unity

Anode current begins to grow towards larger value Thyristor starts conduction.

(iv) Temperature triggering

At high temperature, the forward leakage current across junction J2 rises

This leakage current serves as the collector junction current of the component transistors
Q1 and Q2

Therefore an increase in leakage current Ic1, Ic2 leads to an increase in the emitter
currents of Q1, Q2

As a result α1 + α2 approaches unity

Anode current begins to grow towards a larger value and Thyristor starts conduction.

(v) Light triggering

When light is thrown on silicon, the electron hole pairs increases

In the forward biased thyristor, leakage current across J2 increases which eventually
increases α1 + α2 to unity

As a consequence, anode current begins to grow towards a larger value.

Thyristor starts conduction.

Q7: Explain the switching characteristics (Dynamic Chara) of an SCR during turn on.

The turn on time of an SCR is defined as the time interval during which it changes from
forward blocking state to final on state.

Can be divided into three intervals

 Delay time td

Rise time tr

Spread time tp

Delay time td

It is the time interval during which anode current rises from forward leakage current
to 0.1Ia, (where
where Ia is the final value of anode current
current)
Or
The
he time during which anode voltage falls from Va to 0.9 Va (where Va is the initial
value of anode voltage)

During delay time anode current flows in a narrow region near the gate.
 Rise time

Is the time taken by the anode current to rise from 0.1Ia to 0.9 Ia
Or
Time required for the forward blocking off state voltage to fall from 0.9 to 0.1 of its
initial value.

During rise time, turn on losses in the thyristor are the highest due to high anode
voltage and large anode current occurring together.

Spread time

Time taken by the anode current to rise from 0.9Ia to Ia

Or
Time for the forward blocking voltage to fall from 0.1 of its initial value of its on state
voltage drop (1 to 1.5 V)

During this time conduction spreads over entire cross section of the cathode of SCR

Total turn on time ( ≈ 1 to 4μ sec) of an SCR is equal to the sum of delay time, rise time
and spread time.

Q7: Explain the switching characteristics (Dynamic Chara) of an SCR during turn off.

The dynamic transition process of SCR from conduction state to forward blocking
state is called commutation process or turn off process

The turn of time tq of a thyristor is defined as the time between the instant anode
current become zero and the instant SCR regains forward blocking capability

The turn off time is divided into two interval

Reverse recovery time trr

Gate recovery time tgr

tq=trr+tgr
 Reverse recovery time (t1-t3)

At instant t1, anode current becomes zero

After t1, anode current build up in the reverse direction

This reverse recovery current removes excess carriers from the end junction J1 and J3

At instant t2, when about 60% of the stored charges are removed and reverse recovery
current also starts decaying

The fast decay of the recovery current causes a reverse voltage across the device due
to the circuit inductance

At instant t3, end junction

ons J1 and J3 recover.

Gate recovery time (t3--t4)

At the end of reverse recovery period (t1-t3), the middle junction J2 still has trapped
charges which cannot flow to the external circuit
circuit.

The time (t3 -t4) for recombination of these ccharges

harges is called gate recovery time tgr

At instant t4, junction J2 also recovers and thyristor regains forward blocking capacity.
Q8: Explain the dv/dt and di/dt protection of an SCR.

di/dt protection
When a thyristor is turned on by a gate pulse, conduction of anode current gradually
spreads across the cross section of the Cathode.
If the rate of rise of anode current i.e., di/dt is large as compared to the spread velocity
of carriers, local hot spot will be formed near the gate junction and destroy the
thyristor.
Therefore the rate of rise of anode current at the time of turn on must be kept below the
specified limiting value (20 – 500 A/ μ sec)
The value of di/dt can be maintained below acceptable limit by using a suitable
inductor in series with the anode circuit.
dv/dt protection
If rate of rise of suddenly applied voltage across thyristor is high, the device may get
turned on (False turn on)
For controllable operation of the thyristor, the rate of rise of anode to cathode voltage
dVa/dt must be kept below the specified limit (20 – 500 V / μ sec)
Can be prevented by using a Snubber circuit in parallel with the device
Consist of a series combination of resistance Rs and capacitance Cs in parallel with the
thyristor.

When switch S is closed, a sudden voltage appear across the circuit

Capacitor Cs behaves like a short circuit, therefore voltage across SCR is zero
 Voltage across Cs builds up at a slow rate such that dv/dt across Cs and therefore
across SCR is less than the specified maximum dv/dt rating of the device
When the SCR is turned on, capacitor discharges through the SCR.
To limit the magnitude of discharge current, resistance Rs is inserted in series with Cs
Q9: Explain the Snubber circuit for an SCR.
dv/dt Protection in Q.8

Q10: Design of Snubber circuit.

Refer Class Notes

Q11: What is the need of Series and parallel operation of SCRs? What is String
efficiency and Derating Factor?

When system voltage is more than the voltage rating of a single thyristor, SCRs are
connected in series as a string.
When current demanded by the load is more than the current rating of a single
thyristor, SCRs are connected in parallel.
+ , - ./- 0/ ,2203 2 43 /5 6 243
String efficiency, * = (73
4.4 , - ./- 0/ ,2203 2 43 )(8/./5 9 :6)

Due to the inherent difference in V-I characteristics of the SCRs, voltage/current

sharing between the SCRs will be lower than its normal rating. So, * is less than 1.
Derating Factor, DRF=1- string efficiency

Q12: Explain Series Operation of SCRs.

When system voltage is more than the voltage rating of a single thyristor, SCRs are
connected in series as a string.

Consider two SCRs with their V-I characteristics as close as possible

 Let, SCR1 has leakage
resistance a bit high (=V1/Io)

For SCR2 it is low (V2/Io)

For the same leakage current Io in the series connected SCRs, SCR1 support rated
voltage whereas SCR2 support voltage V2<V1
Two SCR can support a maximum voltage of V1+V2 and not the rated blocking
voltage 2V1
; !;
Here, the ratio is termed as string efficiency (<1)
;
+ , - ./- 02 43 /5 6 243
In General, string efficiency, * = (73
4.4 , - ./- 02 43 )(8/./5
/5 9 :6)

Q13: Explain the Static Equalization ccircuit for series connected SCR string.
In a series string of SCRs, voltage sharing may unequal due to the inherent difference in
V-II characteristics of the SCRs.
So string efficiency is less than 1.
A more uniform voltage distribution and hence better string efficiency can be achieved
by connecting suitable shunt resistance across each SCR.

For derivation,, refer class notes. (Need to write derivation only if asked)
asked
Q14: Explain the Dynamic Equalization ccircuit for series connected SCR string.

During turn on and turn off, Self Capacitance of SCRs may differ.

So when connected in series, voltage distribution among these SCRs also will be unequal.

Dynamic Equalization circuit is designed to maintain uniform voltage distribution during

transient (turn on and turn off) condition.

Shunt capacitors remove the inequalities

in SCR self capacitances

Shunt Resistor limit the discharge

current of capacitor.

For derivation,, refer class notes. (Need to write derivation only if asked)
asked

Q15: Design Problem on Equalization Circuit

Refer Class Notes

Q16: How the current sharing between parallel connected SCRs can be made uniform?

i. Connecting series Resistance:

Suitable External resistance is connected in series

with each SCR.

An external resistance Rn is connected to nth SCR of

dynamic resistance RTn such that,
RT1+R1= RT2+R2=…..= RTn+Rn
[Link] point Reactor

If current through SCRs are same, flux produced by two

halves of the reactor cancels out.

If current through SCRs are unequal, say I1>I2,

I
Voltage induced in L1 opposes the flow of I1 ;
Voltage induced in L2 aids the flow of I2

Thus, currents are brought to same value.

iii. Common Heat Sink

If junction temperature of one SCR increases, it increases the current shared by that and
this increases the temperature further.

This cumulative action may destroy the device

device.

To ensure same temperature rise among the SCRs, they are mounted in common heat
h sinks.

iv. Symmetrical arrangement

Unequal current distribution caused by inductive

effect of current carrying conductors can be
avoided by mounting SCRs symmetrically on the
heat sink.(fig. b)

v. Simultanious Turn on

Q17: Explain the construction, V

V-II characteristics and switching characteristics of a
Power MOSFET
Metal-Oxide-Semiconductor
Semiconductor Field
Field-Effect Transistor (MOSFET)
The Conventional planar MOSFET has the restriction of handling the high power.
In high power applications,
ions, the Double
Double-diffused
diffused vertical MOSFET or VMOS is used
which is simply known as Power MOSFET.
 The Power MOSFET is a three terminal (Gate, Drain and Source), four layer unipolar
semiconductor device.
Symbol:

For n-channel MOSFET, the arrow is inward.

For p-channel MOSFET, the arrow is outward.
(indicates the direction of current flow)

Structure:

The Power MOSFET has a vertically oriented four layer structure of alternating P and N type
(n+ p n- n+) layers.
The P type middle layer is called as body of MOSFET. In this region, the channel is formed
between source and drain.
The n- layer is called as drift region, which determines the breakdown voltage of the device.
The Gate terminal is isolated from body by silicon dioxide layer.
When the positive Gate voltage is applied with respect to source, the n-type channel is
formed between Source to Drain.
As shown in the figure, there is a parasitic npn BJT between Source and Drain. There is
a parasitic diode which is formed between drain to source terminals.
 The V-I characteristics of n-channel
channel enhancement mode MOSFET.

Switching (Dynamic) Characteristics:

The turn on time td(on) is the time that is required to charge the input capacitance to the
threshold voltage level.
The rise time tr is the gate charging time from this threshold level to the full gate
voltage VGSp .
The turn off delay time td(off) is the time required for the input capacitance to discharge
from overdriving the voltage V1 to the pinch off region.
The fall time tf iss the time required for the input capacitance to discharge from pinch
off region to the threshold voltage.
Q18: Explain the construction, V
V-II characteristics and relative merits of an IGBT.
IGBT is a three terminal power semiconductor switch
The combination of BJT and MOSFET monolithically leads to a new device called
Insulated Gate Bipolar Transistor.
 Symbol:

Construction:

The generic n-channel IGBT structure is shown in the above figure.

This structure is similar to the structure of MOSFET except the presence of p+ layer(
which is connected to the drain terminal).
The lower p-n junction is forward biased when the device is on and injects holes into
the n- layer enhancing its conductivity.
The doping levels of each IGBT layers are similar to the doping levels of each layer of
MOSFET except the body region.
 V-I Characteristics:

Advantages:
Good Power handling capabilities
Low forward conduction voltage drop of 2V to 3V, which is higher than for a BJT but
lower than for a MOSFET of similar rating.
High speed switching capability.

Q19: Explain the construction, V

V-I characteristics and
d applications of Triac.

TRIAC – bidirectional thyristor with three terminals

Extensively used for the control of power in ac circuits (residential lamp dimmers,
heater control, speed control of small single phase series and IInduction
nduction Motor)
TRIAC= TRIode + AC
Equivalent
quivalent to two SCRs connected in anti
anti-parallel
Three terminals-
MT1 – Main Terminal 1
MT2 – Main Terminal 2
G- Gate
The gate G is near terminal MT1
G is connected to N3 and P2
MT1 is connected to P2 and N2
MT2 is connected to P1 and N4
 The Triac blocks both +ve and –ve
ve half cycles of the ac voltage applied, until it exceeds
breakover voltage, VBO

When Gate signal is applied, it will conduct for both half cycles ( First and Third
Quadrant V-I operation)

Q20:
20: Explain the operating modes (Turn on modes) of TRIAC.

4 modes of operation based on possible electrode potential combinations as given below

Mode – 1 (MT2 is +ve w.r.t MT1, G +ve w.r.t MT1)

• When MT2 is +ve w.r.t MT1 –

o Junction P1N1, P2N2 are forward biased;

o Junction N1P2 reverse biased

• Gate current injects sufficient charges into P2 layer

layer;
Reverse biased junction N1P2 breaks down

• As a result TRIAC starts conducting through - P1N1P2N2

• TRIAC operates in the first quadrant (V and I positive)

Mode – 2 (MT2 is +ve w.r.t MT1, G -ve w.r.t MT1)

• When G is –ve
ve w.r.t MT1, gate current flows through P2N3

• P1N1-Forward biased; N1P2 and P2N3

P2N3– forward biased by Gate current
• Conduction through – P1N1P2N3

• Voltage across P2N3 rises towards MT2

• Left hand region of P2 at higher potential than right hand region

• Current (shown in dotted line) establishes

• Right hand portion P1N1P2N2 begins to conduct

• Less sensitive First quadrant operation.

Mode 3 (MT2 is -ve w.r.t MT1, G -ve w.r.t MT1)

• Gate current flows from P2 to N3

• Reverse biased junction N1P1 is broken

• Finally P2N1P1N4 is turned on completely

• More sensitive 3rd quadrant operation (V and I –ve)

Mode 4 (MT2 is -ve w.r.t MT1, G +ve w.r.t MT1)

• Gate current forward biases junction – P2N2

• N2 inject electrons into P2 layer (shown by dotted arrows)

• As a result reverse biased junction

• N1P1 breaks down

• The structure P2N1P1N4 is completely turned on

• Less sensitive 3rd quadrant operation.

Q 21: Power Diode
Refer Assignment

Q22: Problem on power diode characteristics

Refer Class Notes

Q23: GTO
Refer Assignment

Q24: Compare Power BJT, Power MOSFET, IGBT and GTO

Refer Class notes

Prepared and compiled by:

Sreekanth P
Asst. Prof, Dept. of EEE
College of Engineering Trikaripur