Scribd
Upload
4 views2 pages

Mem Array Assignment

The assignment focuses on creating a SystemVerilog memory module and its verification through a testbench. It involves converting an existing memory module to SystemVerilog, designing a testbench with dynamic and packed arrays, and implementing at least four test cases to validate memory operations. The tasks include observing data outputs, comparing results, and printing outcomes during simulation.

Uploaded by

Sarvajith Ravilochana Kumar
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
4 views2 pages

Mem Array Assignment

The assignment focuses on creating a SystemVerilog memory module and its verification through a testbench. It involves converting an existing memory module to SystemVerilog, designing a testbench with dynamic and packed arrays, and implementing at least four test cases to validate memory operations. The tasks include observing data outputs, comparing results, and printing outcomes during simulation.

Uploaded by

Sarvajith Ravilochana Kumar
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Assignment: SystemVerilog Memory Module

Verification
Objective
 Understand and practice using dynamic and packed arrays in SystemVerilog.
 Write a SystemVerilog testbench to verify the memory module with at least 4 testcases
covering all basic operations.

Memory Module Overview


You are provided with a 32x8 memory module with the following ports:

Port Direction Description


datain Input Data to write to memory
dataout Output Data read from memory
add Input Address of memory location
rd Input Read enable
w Input Write enable
clk Input Clock signal
rst Input Reset memory
Operation Modes:

rd w Description
0 1 Write only
1 0 Read only
Read & write simultaneously(read
1 1
first, write next)
0 0 Invalid operation (dataout = x)

Assignment Tasks
1. Convert to SystemVerilog:
 Create [Link] from mem.v.

 Use logic types and SystemVerilog conventions.

2. Testbench Design:
 Create a SystemVerilog top_tb.sv file to verify the module.
 Use dynamic arrays for input data and addresses.
 Use packed arrays for storing vectors if needed.
 Generate a clock and apply reset initially.
3. Testcases (minimum 4):
 Write only: rd = 0, w = 1

 Read only: rd = 1, w = 0

 Read & Write simultaneously: rd = 1, w = 1

 Invalid operation: rd = 0, w = 0

4. Verification:
 Observe the dataout values for each testcase.

 Compare actual and expected results.


 Print results in the simulation .

Hints
 Use for-loops to simplify writing/reading multiple addresses.
 Dynamic arrays are ideal for input patterns and address storage.
 Packed arrays help store multiple vectors compactly.
 Apply reset at the start to clear memory contents.

You might also like