ADC and DAC Microprocessor Interfacing Programs

Laboratory Reference Document

Based on the lab manual and notes provided, here is a comprehensive breakdown of the ADC
and DAC microprocessor interfacing programs.
These programs rely on the 8255 Programmable Peripheral Interface (PPI) to bridge the 8085
microprocessor with the analog-to-digital (ADC) and digital-to-analog (DAC) converters. Let’s
break down the algorithms, working principles, and line-by-line assembly codes for both exper-
iments.

Principles of 8255 Control Word Configuration

The 8255 Programmable Peripheral Interface has an 8-bit Control Register that dictates the
operational mode and data direction (Input or Output) of its three ports (Port A, Port B, and
Port C). When the most significant bit (D7 ) is set to 1, the 8255 operates in I/O Mode. The bit-
by-bit configuration logic is as follows:

• D7 (Mode Set Flag): 1 = Active I/O Mode, 0 = BSR (Bit Set/Reset) Mode.
• D6 , D5 (Group A Mode): 00 = Mode 0 (Basic I/O), 01 = Mode 1, 1X = Mode 2.
• D4 (Port A Direction): 1 = Input, 0 = Output.
• D3 (Port C Upper Direction, P C4 − P C7 ): 1 = Input, 0 = Output.
• D2 (Group B Mode): 0 = Mode 0, 1 = Mode 1.
• D1 (Port B Direction): 1 = Input, 0 = Output.
• D0 (Port C Lower Direction, P C0 − P C3 ): 1 = Input, 0 = Output.

Part 1: ADC 0809 Interfacing Program

Working Principle & Algorithm

The ADC 0809 uses the Successive Approximation algorithm to convert analog signals to 8-bit
digital data. Because the ADC cannot directly dump data onto the microprocessor’s data bus
without synchronization, we use the 8255 PPI to handle the “handshaking” control signals.
The algorithm follows these sequential steps:

1
 1. Select the Channel: The ADC 0809 has 8 analog input channels. We select one using the
A, B, and C selection lines.

2. Latch the Channel: A high pulse on the ALE (Address Latch Enable) pin locks in the se-
lected channel.

3. Start Conversion: A high pulse on the SOC (Start of Conversion) pin tells the ADC to begin
sampling the analog voltage.

4. Wait for Conversion: The microprocessor continuously polls the EOC (End of Conversion)
pin. The ADC pulls this pin low during conversion and pushes it high when the 8-bit data
is ready.

5. Read Data: The microprocessor sends a high signal to the OE (Output Enable) pin, allowing
the ADC to push the digital data to Port A of the 8255, where the microprocessor can read
it.

8255 Configuration (Control Word = 98H)

For the ADC, we need basic I/O (Mode 0) to handle data and control signals. Applying the control
word logic:

• D7 = 1: I/O Mode active.

• D6 , D5 = 00: Group A in Mode 0.

• D4 = 1: Port A as Input (to receive 8-bit digital data from ADC).

• D3 = 1: Port C Upper as Input (to read the EOC status signal on P C4 ).

• D2 = 0: Group B in Mode 0.

• D1 = 0: Port B as Output (to send 3-bit channel selection to ADC).

• D0 = 0: Port C Lower as Output (to send ALE, SOC, and OE pulses to ADC).

Binary sequence: 1001 1000 → 98H. This value is sent to the 8255 Control Register (Port 03H).

Line-by-Line Code Explanation

; --- INITIALIZATION ---

2000 MVI A, 98H ; Load Control Word (98H) into Accumulator .
2002 OUT 03H ; Send Control Word to 8255 Control Register (03H).

; --- CHANNEL SELECTION ---

2004 MVI A, 00H ; Load 00H to select Channel -0 (A=0, B=0, C=0).
2006 OUT 01H ; Send selection data to Port B (01H).

; --- START CONVERSION (ALE & SOC PULSES ) ---

LOOP1:
2008 MVI A, 01H ; Set Port C bit 0 high (ALE = 1).
200A OUT 02H ; Send to Port C (02H).
200C MVI A, 00H ; Set Port C bit 0 low (ALE = 0) -> latch pulse.
200E OUT 02H
2010 MVI A, 03H ; Set Port C bits 0 and 1 high (ALE =1, SOC =1).

2
2012 OUT 02H ; Send to Port C.
2014 MVI A, 00H ; Set all Port C bits low (SOC = 0) -> start pulse.
2016 OUT 02H

; --- POLLING FOR END OF CONVERSION ---

LOOP2:
2018 IN 02H ; Read the status of Port C.
201A ANI 10H ; Mask all bits except bit 4 (PC4 connected to EOC).
201C JZ LOOP2 ; If Zero (EOC is low), jump back to LOOP2.

; --- READ AND DISPLAY DATA ---

201F MVI A, 04H ; Set Port C bit 2 high ( Output Enable , OE = 1).
2021 OUT 02H ; Send to Port C to enable ADC output buffers .
2023 IN 00H ; Read the 8-bit digital data from Port A (00H).
2025 STA 27 F6H ; Store converted data into memory location 27 F6H.
2028 CALL 0347H ; Call subroutine to display data on 7- segment .
202B LXI D, 0000H ; Load dummy value into DE register for delay.
202E CALL 03 BCH ; Call Delay subroutine .
2031 CALL 06 FAH ; Call subroutine to clear display / refresh .
2034 LXI D, 0000H ; Load dummy value for delay again.
2037 CALL 03 BCH ; Call Delay subroutine .
203A JMP LOOP1 ; Jump back to LOOP1 to continuously scan.

Part 2: DAC 0800/0808 Interfacing Program (Staircase Waveform)

Working Principle & Algorithm

The Digital-to-Analog Converter (DAC) takes an 8-bit digital word and converts it into an equiv-
alent analog current or voltage. The theoretical analog voltage is calculated using the formula:

Van. = Vref. (a0 · 2−1 + a1 · 2−2 + · · · + a7 · 2−8 )

To generate a staircase waveform, we do not rely on an external analog sensor. Instead, the
microprocessor feeds a predefined array of progressively increasing digital hex values to the
DAC. The DAC converts each hex value into a discrete voltage step. By introducing a delay be-
tween each value, the voltage holds steady for a short duration, creating the horizontal “tread”
of the staircase before jumping to the next value.

8255 Configuration (Control Word = 80H)

To act as a pure transmitter to the DAC, all ports on the 8255 must be configured as basic Mode
0 outputs.

• D7 = 1: I/O Mode active.

• D6 , D5 = 00: Group A in Mode 0.

• D4 = 0: Port A as Output (to send digital data to X-OUT).

3
 • D3 = 0: Port C Upper as Output.

• D2 = 0: Group B in Mode 0.

• D1 = 0: Port B as Output (to send digital data to Y-OUT).

• D0 = 0: Port C Lower as Output.

Binary sequence: 1000 0000 → 80H.

Line-by-Line Code Explanation

; --- INITIALIZATION ---

2000 MVI A, 80H ; Load the Control Word (80H) into Accumulator .
2002 OUT 03H ; Send Control Word to 8255 Control Register (03H).
2004 LXI H, 2028H ; Init HL register to point to memory address 2028H.
2007 MVI C, 0BH ; Init register C as a counter with 0BH (11 steps).

; --- DATA TRANSMISSION LOOP ---

LOOP2:
2009 MOV A, M ; Load first data byte from memory to Accumulator .
200A OUT 00H ; Send data out to X-OUT via Port A (00H).
200C OUT 01H ; Send identical data out to Y-OUT via Port B (01H).
200E PUSH H ; Save the current HL pointer onto the stack.
200F PUSH B ; Save the current BC counter onto the stack.
2010 LXI D, 0020H ; Load delay count into DE pair (step width).
2013 CALL 03 BCH ; Call the Delay subroutine .
2016 POP B ; Retrieve the BC counter from the stack.
2017 POP H ; Retrieve the HL pointer from the stack.
2018 INX H ; Increment HL pair to point to next data byte.
2019 DCR C ; Decrement the step counter in register C.
201A JNZ LOOP2 ; If counter != 0, jump back to LOOP2.
201D JMP 2004H ; If done , jump back to 2004H to restart wave.

; --- LOOKUP TABLE (DATA ARRAY) ---

; These values dictate the voltage heights of the 11 staircase steps.
2028 DFB 00H ; Step 1: 00000000
2029 DFB 19H ; Step 2: 00011001
202A DFB 33H ; Step 3: 00110011
202B DFB 4CH ; Step 4: 01001100
202C DFB 66H ; Step 5: 01100110
202D DFB 7FH ; Step 6: 01111111
202E DFB 99H ; Step 7: 10011001
202F DFB B3H ; Step 8: 10110011
2030 DFB CCH ; Step 9: 11001100
2031 DFB E5H ; Step 10: 11100101
2032 DFB FFH ; Step 11: 11111111 (Max Voltage )

Note on Frequency: As asked in your lab manual document, the frequency of this generated
waveform can be varied by altering the delay count loaded into the DE register pair at address
2010H. Decreasing the delay count will increase the frequency of the staircase wave, and vice
versa.

4
 Study of Vectored Interrupts in 8085 Microprocessor

Objective
The goal of this program is to study vectored interrupts in the 8085 microprocessor by building
a 2-digit BCD (Binary Coded Decimal) counter.

• The main program continuously counts and displays the BCD values.

• The microprocessor is connected to a ”Vectored Interrupt Key” via the RST 7.5 interrupt pin.

• When the interrupt key is pressed, the main program halts, and an Interrupt Service Routine
(ISR) located at address 20CE H is triggered.

• The ISR briefly displays ”FF” on the screen, waits for a delay, and then returns execution to the
main program so the counter can resume exactly where it left off.

Working Principle
An interrupt is a special condition that forces the microprocessor to temporarily pause its cur-
rent task and execute a specific subroutine known as an Interrupt Service Routine (ISR).

• The Interrupt Process: When the RST 7.5 interrupt occurs, the 8085 finishes its current in-
struction. It pushes the Program Counter (PC) contents onto the stack to remember its place,
resets the Interrupt Enable (INTE) flip-flop to ignore further interrupts, and jumps to the ISR.

• RST 7.5 Characteristics: RST 7.5 is a maskable hardware interrupt. It is positive edge-triggered,
meaning it responds to a transition from low to high voltage. Its fixed vector address is 003C
H.

• Masking and Enabling:

– To enable RST 7.5, the program uses the SIM (Set Interrupt Mask) instruction.
– The required control word loaded into the Accumulator before calling SIM is 0B H (which
is 0000 1011 in binary).
– In this control word: Bit 3 (Mask Set Enable) is 1, Bit 2 (RST 7.5 Mask) is 0 to unmask/enable
it, while Bit 1 and Bit 0 are 1 to mask/disable RST 6.5 and RST 5.5 respectively.
– Finally, the EI (Enable Interrupts) instruction is used to set the INTE flip-flop, allowing the
microprocessor to recognize unmasked interrupts.

1
Algorithm
Main Program Algorithm
1. Initialize the Stack Pointer to a designated memory location to safely store data during
subroutines and interrupts.

2. Enable the interrupt system globally using the EI instruction.

3. Load the control word 0B H into the Accumulator and execute SIM to unmask the RST 7.5
interrupt.

4. Initialize the Accumulator to 00 H to start the BCD counter.

5. Loop Starts: Save the current state of the Accumulator and flags by pushing the Program
Status Word (PSW) onto the stack.

6. Call the Display subroutine to show the current count.

7. Load a delay value into the DE register pair and call the Delay subroutine.

8. Restore the Accumulator and flags by popping the PSW from the stack.

9. Increment the Accumulator.

10. Use the DAA instruction to adjust the hexadecimal sum back to a valid BCD number.

11. If there is no carry (meaning the count hasn’t exceeded 99), jump back to step 5.

12. If there is a carry, clear the Accumulator using XRA A to reset the count to 00, then jump
back to step 5.

Interrupt Service Routine (ISR) Algorithm

1. When RST 7.5 is triggered, immediately save the main program’s Accumulator and flags
by pushing PSW to the stack.

2. Load FF H into the Accumulator.

3. Call the Display subroutine to show ”FF” on the screen.

4. Load a delay value into the DE register pair and call the Delay subroutine.

5. Restore the main program’s Accumulator and flags by popping PSW from the stack.

6. Re-enable interrupts using EI (since they are automatically disabled when an interrupt is
recognized).

7. Return to the main program using RET.

2
Code Explanation
1. Main Program (BCD Counter)
2. Interrupt Service Routine (RST 7.5)
Note: This ISR resides at 20CE H. When RST 7.5 is triggered, the processor automatically jumps to
003C H. For this code to work, an unconditional jump (JMP 20CE H) must be pre-programmed at the
003C H vector location.

3
Label Opcode & Operand Comments & Explanation

LXI SP, 1200 H Load Stack Pointer: Initializes the stack pointer to memory ad-
dress 1200 H to hold return addresses and pushed register con-
tents.
EI Enable Interrupts: Sets the INTE flip-flop, allowing the 8085 to
accept maskable hardware interrupts.
MVI A, 0B H Move Immediate: Loads the control word 0B H (0000 1011 bi-
nary) into the Accumulator in preparation for the SIM instruction.
SIM Set Interrupt Mask: Reads the accumulator and applies the
mask, enabling RST 7.5 while keeping RST 6.5 and RST 5.5
masked/disabled.
MVI A, 00 H Move Immediate: Initializes the counter by setting the Accumu-
lator to 00 H.
LOOP: PUSH PSW Push Program Status Word: Saves the current value of the Ac-
cumulator (the counter) and flags onto the stack before modify-
ing registers.
CALL 036E H Call Subroutine: Jumps to the Display subroutine located at 036E
H to output the current value.
LXI D, FFFF H Load Register Pair: Loads the maximum 16-bit value (FFFF H)
into the DE register pair to set the length of the delay.
CALL 05F1 H Call Subroutine: Jumps to the Delay subroutine at 05F1 H so the
displayed number remains visible long enough for a human to
read.
POP PSW Pop Program Status Word: Retrieves the counter value and
flags from the stack back into the Accumulator and Flag regis-
ter.
INR A Increment: Increases the value in the Accumulator by 1.
DAA Decimal Adjust Accumulator: Corrects the binary addition per-
formed by INR A so the result stays in valid BCD format (e.g.,
changes 0A to 10).
JNC LOOP Jump on No Carry: If the counter hasn’t overflowed past 99 (no
carry flag), jump back to the LOOP label to display and increment
again.
XRA A Exclusive OR: XORs the Accumulator with itself. This efficiently
clears the Accumulator back to 00 H when a carry occurs.
JMP LOOP Unconditional Jump: Jumps back to restart the counting se-
quence from 00.

4
Label Opcode & Operand Comments & Explanation

PUSH PSW Push Program Status Word: The very first step of the ISR is to
save the main program’s counter value so it isn’t destroyed by
the ISR’s operations.
MVI A, FF H Move Immediate: Loads the specific interrupt notification code
(FF H) into the Accumulator.
CALL 036E H Call Subroutine: Calls the Display subroutine to output ”FF”, vi-
sually indicating to the user that an interrupt has occurred.
LXI D, FFFF H Load Register Pair: Loads the delay count into the DE register
pair.
CALL 05F1 H Call Subroutine: Calls the Delay subroutine so the ”FF” message
is held on the screen.
POP PSW Pop Program Status Word: The ISR is finishing, so it restores
the original counter value back into the Accumulator and resets
the flags.
EI Enable Interrupts: Re-enables the interrupt system. The micro-
processor automatically disables interrupts upon acknowledg-
ing an interrupt to prevent nesting issues.
RET Return: Pops the original Program Counter value off the stack,
seamlessly returning execution to the exact instruction in the
main program where it was interrupted.

5
 Stepper Motor Control using 8085 Microprocessor

1 Working Principle of the Stepper Motor

Stepper motors translate digital control pulses into precise angular movements. Unlike con-
ventional motors, their speed is controlled by the frequency of switching pulses rather than the
supply voltage. In a standard two-phase bifilar configuration, the motor achieves a precise step
angle of 1.8◦ per step.
The motor shaft moves one step per input pulse based on a sequential excitation of its coils.
When the pulses stop, the motor locks into its final position electromagnetically, granting it a
static holding torque.

2 8255 Programmable Peripheral Interface (PPI) & Control Word Con-

figuration
To control a stepper motor using an 8085 microprocessor, you need an intermediary device
because the microprocessor cannot supply the necessary current or directly hold the state of
the motor coils. This is where the 8255 Programmable Peripheral Interface (PPI) comes in. It
acts as a bridge, providing parallel I/O ports that can be configured through software.
To make the 8255 work for your specific application, you must configure its internal registers
by sending a specific 8-bit byte called the Control Word to its Control Word Register (CWR).

2.1 The Structure of the 8255 Control Word (I/O Mode)

The 8255 has three 8-bit ports: Port A, Port B, and Port C (which can be split into Upper and
Lower). The Control Word determines whether these ports act as inputs (reading data) or out-
puts (sending data), and in what operating mode.
When the most significant bit (D7) is set to 1, the 8255 operates in I/O Mode. The remaining
7 bits dictate the configuration:
- D7 (Mode Set Flag): Must be 1 to configure ports for Input/Output operations. (A 0 here
enters Bit Set/Reset mode for Port C, which isn’t used for basic motor control).
- Group A Control (Port A & Port C Upper)
- D6 & D5 (Mode Selection):
- 00 = Mode 0 (Simple I/O) - Used for stepper motors.
- 01 = Mode 1 (Strobed I/O)
- 1x = Mode 2 (Bidirectional I/O)
- D4 (Port A Direction): 1 = Input, 0 = Output.
- D3 (Port C Upper Direction): 1 = Input, 0 = Output.
- Group B Control (Port B & Port C Lower)
- D2 (Mode Selection): 0 = Mode 0, 1 = Mode 1.
- D1 (Port B Direction): 1 = Input, 0 = Output.
- D0 (Port C Lower Direction): 1 = Input, 0 = Output.

1
2.2 Constructing the Control Word for Stepper Motor Control
In a typical stepper motor setup, the motor driver inputs are connected to Port A. To drive the
motor, the microprocessor needs to send high and low signals to these coils. Therefore, Port A
must be configured as an Output port operating in simple Mode 0.
Let’s build the binary control word for this requirement:

1. D7 = 1: We are setting I/O mode.

2. D6 = 0, D5 = 0: Group A operates in simple Mode 0.

3. D4 = 0: Port A is configured as an Output.

4. D3 = 0: Port C Upper configured as Output (unused, so default to 0).

5. D2 = 0: Group B operates in Mode 0.

6. D1 = 0: Port B configured as Output (unused, so default to 0).

7. D0 = 0: Port C Lower configured as Output (unused, so default to 0).

Combining these bits gives us: 1000 0000 in binary. Converting 1000 0000 binary to hex-
adecimal gives us 80H.

2.3 The Initialization Code

This explains the very first two lines of any 8085 stepper motor program:

MVI A, 80H ; Move the Control Word (1000 0000) into the Accumulator
OUT 03H ; Send the contents of the Accumulator to the CWR address (03H)

Once this instruction executes, the 8255 locks Port A into output mode. Any subsequent OUT 00H
commands (sending data to Port A) will successfully pass through the 8255, trigger the driver
transistors, and energize the stepper motor coils.

3 Interfacing and System Algorithm

1. Initialization: The Control Word Register (CWR) of the 8255 (Address 03H) is loaded with
80H to configure Port A (Address 00H) as an output port.

2. Coil Excitation: The four windings of the motor are connected to Port A pins PA0 through
PA3 via a driver circuit. Specific hexadecimal values are sent to Port A to turn specific
transistors (Q1 to Q4) on or off, energizing the respective coils.

3. Delay: A subroutine creates a time gap between consecutive steps. Altering this delay
duration directly controls the motor’s rotational speed.

4 Lab Manual Problem Solutions

4.1 Problem 1: Operate the Stepper Motor in Two-Phase (Anti-Clockwise)
In two-phase excitation, two coils are energized simultaneously to maximize torque. The Anti-
Clockwise (CCW) switching sequence provided in the manual is FAH, F6H, F5H, F9H.

2
Address Opcode Mnemonic Comments
2000 3E 80 MVI A, 80H ; Load Accumulator with Control Word 80H
2002 D3 03 OUT 03H ; Send 80H to CWR to set Port A as Output
2004 3E FA LOOP: MVI A, 0FAH; Load hex FAH (1111 1010) to set PA1 & PA3 high
2006 D3 00 OUT 00H ; Send the value to Port A to excite coils
2008 CD 23 20 CALL DELAY1 ; Call delay routine to hold the step
200B 3E F6 MVI A, 0F6H ; Load hex F6H (1111 0110) to set PA1 & PA2 high
200D D3 00 OUT 00H ; Send the value to Port A
200F CD 23 20 CALL DELAY1 ; Call delay routine
2012 3E F5 MVI A, 0F5H ; Load hex F5H (1111 0101) to set PA0 & PA2 high
2014 D3 00 OUT 00H ; Send the value to Port A
2016 CD 23 20 CALL DELAY1 ; Call delay routine
2019 3E F9 MVI A, 0F9H ; Load hex F9H (1111 1001) to set PA0 & PA3 high
201B D3 00 OUT 00H ; Send the value to Port A
201D CD 23 20 CALL DELAY1 ; Call delay routine
2020 C3 04 20 JMP LOOP ; Jump back to start of sequence for rotation

; DELAY SUBROUTINE (Hardware specific implementation)

2023 11 00 00 DELAY1: LXI D, 0000H ; Initialize delay parameter
2026 CD BC 03 CALL 03BCH ; Call kit-specific monitor delay routine
2029 C9 RET ; Return to main program

4.2 Problem 2: Reverse the Direction of Rotation (Clockwise)

To reverse the motor, the step sequence is simply read backward (upward in the truth table).
The sequence changes from FA, F6, F5, F9 to F9, F5, F6, FA.

Address Mnemonic Comments

2000 MVI A, 80H ; Configure Port A as output
2002 OUT 03H
2004 LOOP: MVI A, 0F9H; 1st Step: Set PA0 & PA3 high (Reverse of CCW step 4)
2006 OUT 00H
2008 CALL DELAY1
200B MVI A, 0F5H ; 2nd Step: Set PA0 & PA2 high
200D OUT 00H
200F CALL DELAY1
2012 MVI A, 0F6H ; 3rd Step: Set PA1 & PA2 high
2014 OUT 00H
2016 CALL DELAY1
2019 MVI A, 0FAH ; 4th Step: Set PA1 & PA3 high (Reverse of CCW step 1)
201B OUT 00H
201D CALL DELAY1
2020 JMP LOOP ; Continue clockwise rotation
; (Delay routine remains identical)

4.3 Problem 3: Operate the Stepper Motor with Increasing Speed

When a motor starts, its speed is limited by load torque and inertia; instantly applying high-
frequency pulses causes it to lose synchronism. Acceleration requires gradually increasing the
switching step rate by decreasing the delay parameter over time.

3
 Note: Since the manual utilizes a black-box kit-specific delay (CALL 03BCH), the standard approach
to programmatic acceleration involves managing a custom delay counter in register pairs (e.g., B and
C) and decrementing the master count after each full revolution.
Algorithm for Acceleration:

1. Initialize the CWR for output.

2. Load a high initial value into a register (e.g., Register D) to represent a slow starting speed.

3. Output the 4-step sequence. For every step, call a custom software delay loop utilizing the
value in Register D.

4. After completing one full 4-step rotation cycle, decrement Register D.

5. Check if Register D has reached a minimum threshold (maximum speed constraint). If not,
loop back and run the 4-step sequence again with the newly shortened delay.

4.4 Problem 4: Operate the Stepper Motor in a Single Phase

In single-phase (wave drive) operation, only one winding is energized at any given time. By
analyzing the provided switching table, the CCW single-phase sequence requires energizing
Q3, then Q2, then Q1, then Q4.
Mapping this to Port A outputs:

- Step 1: PA1 high → F2H (1111 0010)

- Step 2: PA2 high → F4H (1111 0100)

- Step 3: PA0 high → F1H (1111 0001)

- Step 4: PA3 high → F8H (1111 1000)

Address Mnemonic Comments

2000 MVI A, 80H ; Configure Port A as output
2002 OUT 03H
2004 LOOP: MVI A, 0F2H; Set PA1 high (Coil 3 energized)
2006 OUT 00H
2008 CALL DELAY1
200B MVI A, 0F4H ; Set PA2 high (Coil 2 energized)
200D OUT 00H
200F CALL DELAY1
2012 MVI A, 0F1H ; Set PA0 high (Coil 1 energized)
2014 OUT 00H
2016 CALL DELAY1
2019 MVI A, 0F8H ; Set PA3 high (Coil 4 energized)
201B OUT 00H
201D CALL DELAY1
2020 JMP LOOP ; Continue single-phase CCW rotation
; (Delay routine remains identical)