Faculty of Computer Science and Engineering Department of Computer Engineering
Ho Chi Minh City University of Technology LOGIC DESGIN WITH HDL
Faculty of Computer Science and Engineering Practical session - Semester 242
WEEK 3
Sequential Logic Circuit
1 Introduction
1.1 Aims
• Practice in designing sequential logic circuits using Verilog HDL behavioral model.
• Understand the blocking/non-blocking assignment to design a combinational/sequential circuit.
• Understand finite state machine models and practice in model FSMs using Verilog HDL.
1.2 Preparation
• Read the laboratory materials before class.
• Review chapter 5-6 about Behavioral Model and Finite State Machine.
• Each group prepares at least one laptop with Vivado software installed.
1.3 Report requirements
• Lab exercises will be reviewed directly in class.
• Write report (with circuit/simulation screenshots inserted) in pdf.
• Must have group ID, group member’s names and student IDs in the report.
• Compress the report with code files (only .v files) in only one .zip file, name the .zip the group ID
(for example: [Link]).
• Submit on BK-elearning by deadline.
2 Exercises
2.1 Exercise 1
Clock Frequency Divider
Police Siren: Design a circuit that generate a 1 Hz output signal using Behavioral Model. This
signal is connected to 2 RGB LEDs (1 displays the blue color, 1 display the red color) on Arty-Z7 FPGA
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Faculty of Computer Science and Engineering Department of Computer Engineering
Board to make it blink interleave with each other (turn on for 0.5s - turn off for 0.5s). Know that the
input clock frequency is 125 MHz.
Write test benches to simulate the circuits.
Test the circuits on FPGA board using LEDs and RGB LED.
2.2 Exercise 2
Use Verilog behavioral model to implement a 4-bit counter with a synchronous reset signal:
• Counter operates as a MOD-16 up counter (count up from 0 to 15 and back to 0).
• The reset signal is synchronous, active high.
Write a test bench to simulate the counter.
Test the counter on FPGA board using buttons (KEY), LEDs or 7-seg LEDs. Students can generate
a low frequency clock to check the behavior of the circuit on board.
2.3 Exercise 3
Design and implement a 4-bit counter:
• module counter(input clk, reset, mode, output rco, output [3:0] count);
• The reset signal is asynchronous, active low.
• rco = 1 if the count value = 4b0000. Otherwise, rco = 0.
• When mode = 0, the module counts up while it counts down if mode = 1
Write a test bench to simulate the counter.
Test the counter on FPGA board using buttons (KEY), LEDs or 7-seg LEDs. Students can generate
a low frequency clock to check the behavior of the circuit on board.
2.4 Exercise 4
Edge Detection circuit.
a. Design a Rising Edge Detection circuit. This circuit will use at least 2 flip-flops. The behavior of
the circuit is similar to the waveform in Figure 1. Assume that the in signal’s HIGH levels last equal to or
longer than a clock cycle.
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Faculty of Computer Science and Engineering Department of Computer Engineering
clk
in
1 cycle
out
Figure 1: Rising Edge Detector behavior
The output is active HIGH in 1 cycle of clock when a rising edge occurs in input signal. Delay is within
0-2 clock cycles.
Write RTL code and test benches to simulate the circuit.
NOTICE: This circuit is very important. Please complete it regardless of whether you can do it by
deadline or not.
b. Write a 4-bit binary counter that counts up 1 unit when a button is pushed. Use the edge detection
circuit to generate an enable signal for the counter when pushing the button. Test the design on FPGA
board.
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