Introduction to Electronics

Part 4: Digital Electronics

L05: Latches and Flip-Flops

Dr. Rik Dey

ASSISTANT PROFESSOR,
ELECTRICAL ENGINEERING, IIT KANPUR

2023-24 SEM-II ESC201A INTRODUCTION TO ELECTRONICS CIRCUITS

1
 Digital System Design Flow
x y z f
System Description 0 0 0 0
0 0 1 1
0 1 0 0
Truth Table 0 1 1 1
1 0 0 0
x 1 0 1 1
y 1 1 0 0
system f
1 1 1 1
z

Boolean Expression f = x .y . z + x . y . z + x . y . z + x . y . z

Minimized ⇒ f=𝑧
Boolean Expression

Gate Netlist
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 Modular Approach
System
Sub-system-1
Sub-system 3:

System Sub-system-3 Sub-Sub-systems

Sub-system-2

There are certain sub-systems or blocks that are used quite often such as :
1. Adder/Subtractors, Multipliers
2. Comparators
3. Multiplexers, Decoder or Demultiplexers
4. Encoders, Priority Encoder
5. Parity Generators
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 Gate Delays and Timing Diagram

Digital signal:

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 Ideal Logic Circuits

0 -> 1
0 -> 1 1 -> 1
1 -> 0 No change

• Ideal situation if all gate delays are zero

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 Glitch and Usefulness of Definition

• Glitch occurs when different paths from input to output experience different delays
• However, by definition, the delay of the block is 3 unit

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 Combinational Circuit
• How to make sure that the desired circuit will work properly?

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 Combinational Circuit: Definition

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 Recall: Combinational 4-bit Adder Circuit
C3 C2 C1
• Ripple carry adder
A 3 A 2 A 1A 0
S1 B 3 B 2 B 1B 0
S3 S2
C 4 S 3 S 2 S 1S 0

C4 C3 C2 C1 0
FA FA FA FA

A3 B3 A2 B2 A1 B1 A0 B0

• Disadvantage: gates have finite (non-zero) delay

• Each FA must wait for the carry bit to be calculated from the previous FA
• In practice, other architectures are used

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 Is there a better way of doing addition?

• Consider adding 6 numbers on your calculator

• What if we can add one bit at a time? (need one full adder)

• Some notion of “timing” (clock)

• “Remembering” transient inputs (memory)

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 Sequential Operation

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 Sequential Circuits

• Sequential logic circuits:

uses memory and combinational circuit
• Calculation divided into steps
• Each step is triggered by a clock
• Constructive use of the gate delay if needed
• At each step:
• the output is based on the current values of inputs
and past values of inputs/outputs as well.
• Requires memory
• Random Access Memory (RAM), Hard-Disks, USB drives,
NAND Flash (SD cards), Solid State Drive (SSD)

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 Clocks
• Process the input after all inputs have settled

• Process at discrete intervals

• concept of clock
• clock speed

• Sequential (one by one) processing

• sequential circuits

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 How to Generate Clock Signal?
• Recall: Op-Amp based Astable Multivibrator

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 Memory Abstraction
• A 1-bit memory element
• Remembers input when store is high
(Like a camera that records input
when the user presses the button)
• The recorded value is visible at dout

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 Memory with Set/Reset Knob

Two memory states are possible:

1. Q1=Q3=0 (Low), Q2=1 (High)
2. Q1=Q3= 1 (High), Q2= 0 (Low) We need at least 2 i/p logic gates
➢ NOR gate behave like INV if one i/p is 0
But how will one change the state? ➢ NAND behaves like INV if one i/p is 1

R 𝐒തS
Q Q

Q ഥR Q
S 𝐑
NOR-based SR Latch NAND-based SR Latch
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 Set-Reset (SR) Latch: Set State
Reset

R 1
0 Q
0
Q = 1; Q = 0 Set State

Q = 0; Q = 1 Re set State
1 Q
S 0

Set
S R Q Q State
1+𝑄 =0
1 0 1 0 SET

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 Set-Reset (SR) Latch: Reset State
Reset

R 0
1 Q Q = 1; Q = 0 Set State

1 Q = 0; Q = 1 Re set State
0 0 Q
S

Set
S R Q Q State
1 + 𝑄ത = 0 SET
1 0 1 0

0 1 0 1 RESET

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 SR Latch: ‘Hold’ (memory)

R 1 1
R 0 0
0 Q Q
0

1
0 Q 0 Q
S 0 0 S 1
S R Q Q State S R Q Q State
1 0 1 0 SET 1 0 1 0 SET

0 0 1 0 HOLD 0 0 1 0 HOLD

0 1 0 1 RESET
0 0 0 1 HOLD
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 SR Latch: Invalid Input
R 0 Q
1 Both the outputs are well defined and 0. The first
problem is that we do not get complementary output.

0
1 Q
S

A serious problem occurs when we switch the latch to the hold state by changing SR from 11 → 00.
Suppose the inputs do not change simultaneously and we get the situation 11 → 10* → 00
1 0 0
R 0 Q R 1 Q R 1 Q

S
1 Q
S
1 0
Q
S
0 0
Q
0
Q=1
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 SR Latch: Invalid Input
1 0 0 0
R
Q
R 1 R 1 Q
Q

0 0 0
1 Q 1 Q 0 Q
S S S

Q=1
Suppose the inputs change as SR = 11 → 01* → 00
1 1 0 0
R 0 Q
R
Q
R 0 Q

0 1 1
S
1 Q
S
0 Q
S
0 Q

Q=0
So although output is well defined when we apply SR = 11, it becomes unpredictable once we switch the latch
to hold state by applying SR = 00. That is why SR = 11 is not used as an input combination.
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 SR Latch: Invalid Input and Gate Delays
R
1 0 R
0 0 0
1 Q 1 Q R 1
0 1 Q

1 2 Q 0 2 Q 0
S 0 S 0 0 2 Q
S

Suppose gate-1 is faster Q=1

On the other hand suppose that gate-2 is faster.

R
1 0 R
0 0 0
1 Q 1 Q R 0
1 Q

0
1 2 Q 0 2 Q 1
S 0 S 0 0 2 Q
S

Again the output is unpredictable in general

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 NOR-based vs NAND-based SR Latch
R 𝐒തS
Q Q

Q Q
S ഥR
𝐑

S R Q Q State 𝐒ത ഥ
𝐑 Q Q State

1 0 1 0 SET 0 1 1 0 SET

0 1 0 1 RESET 1 0 0 1 RESET
0 0 Q Q HOLD 1 1 Q Q HOLD
1 1 0 0 INVALID 0 0 1 1 INVALID

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 NAND-based SR Latch with Enable
S 1
Q

EN Hold State
0
Enable S R Q Q State
1 Q
R 0 x x Q Q Hold

1 1 0 1 0 Set
S S
Q 1 0 1 0 1 Reset

1 0 0 Q Q Hold
EN
1 1 1 1 0 0 Invalid
Q
R
R

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 D Latch
1 1 1
S Q D S Q
EN 1 EN
0
R Q 0 R Q

Enable 𝐃
S R Q Q State
0 x x Q Q Hold D Q
1 1 0 1 0 Set

1 0 1 0 1 Reset
EN Q
1 0 0 Q Q Hold

1 1 1 0 0 Invalid

If EN = 1 then Q = D otherwise the latch is in Hold state

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 D Latch: Timing Diagram
EN D Q Description
0 X Q Hold
1 1 1 Set
1 0 0 Reset
Transparent when EN is high

D Q

EN Q

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 D Latch: MUX based Implementation
D Q EN D Q Description
0 X Q Hold
1 1 1 Set
clk EN Q 1 0 0 Reset
Transparent when EN is high

I0

I0
Y0
Q
D I1
I1
clkS

clk

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 D Latch in a Sequential Circuit
1
zn
➢ Circuits are designed with the idea that there would be a
1
single change in output or state in a single clock cycle.
D Q yn ➢ However, we can see that there are multiple changes as long
clk as clock is high considering propagation delay in the D latch.

clk

y
❑ How to overcome this?
z

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 What we want: Edge-Triggered Flip Flop
D Q D Q

clk clk

Clock Clock

D D

Positive edge triggered flipflop Negative edge triggered flipflop

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 Master-slave D flip-flop
D D D Q

master slave
EN EN Q

clk

Clock

Looks at D when clock is high Master

Looks at Master when clock is low Slave

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 Other ways of edge triggering?
• Use a very small width pulse at the EN

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 Other ways of edge triggering?
• Exploit gate delays (the glitch phenomenon)

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 Edge-Triggered SR Flip Flop

invalid invalid

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 JK Flip Flop
J Q

clk

Characteristic table:
Inputs J K Q(t+1) Characteristic equation:
0 0 Q(t)
Q(t + 1) = JQ (t ) + K Q(t )
0 1 0
1 0 1
1 1 Q(t)

• No invalid states (unlike SR FF)

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 D Flip Flop
D Q

clk

Characteristic table:

Inputs (D) Q(t+1) Characteristic equation:

0 0 𝑄(𝑡 + 1) = 𝐷
1 1

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 Toggle or T Flip Flop

T Q
Characteristic table:
clk
Inputs (T) Q(t+1) T Q(t) Q(t+1)
0 Q(t) 0 0 0
1 Q(t) 0 1 1
1 0 1
Characteristic equation: 1 1 0
𝑄(𝑡 + 1) = 𝑇 ⊕ 𝑄(𝑡)

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 Characteristic Table vs Excitation Table
• What inputs are required for a particular state change?

Excitation table: T Q
Inputs
Q(t) Q(t+1) T clk

0 0 0
0 1 1
1 0
Characteristic table:
1
1 1 0 Inputs (T) Q(t+1) T Q(t) Q(t+1)
0 Q(t) 0 0 0
1 Q(t) 0 1 1
1 0 1
1 1 0
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 Excitation Table: Examples
J Q J K Q(t+1)
D Q D Q(t+1)
clk 0 0 Q(t)
clk 0 0
0 1 0
K 1 1
1 0 1
1 1 Q(t) Excitation table: Q D Q(t+1)
Inputs
0 0 0
Excitation table: Inputs Q J K Q(t+1) Q(t) Q(t+1) D 0 1 1
0 0 0 0 0 0 0
Q(t) Q(t+1) J K 1 0 0
0 0 1 0 0 1 1
0 0 0 X
0 1 0 1 1 0 0 1 1 1
0 1 1 X
0 1 1 1 1 1 1
1 0 X 1
1 0 0 1
1 1 X 0
1 0 1 0
1 1 0 1
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 Implementing a T Flip Flop using D Flip Flop
• Suppose D flip flop is given, how do we design a T flip-flop?
At current instant, we have T and Q
D Q How do we get D from signals we have

clk Q\T 0 1
ത 𝑄 𝑡 + 𝑇𝑄(𝑡)
𝐷 = 𝑇.
0 1
1 1

D 𝐷 = 𝑇 ⊕ 𝑄(𝑡)
T Q(t) Q(t+1)
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0
Truth table of what Excitation
we desire to make table of what
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 D Flip Flop to JK Flip Flop
At current instant, we have J,K and Q
D Q D from signals we have
J Expanded Excitation
CC clk Form table of what JK
K we have Q 00 01 11 10
0 0 0 1 1
J K Q Q(t+1) D
0 0 0 0 0 1 1 0 0 1
J K Q(t+1) D
0 0 1 1 1
0 0 Q(t) Q(t)
0 1 0 0 0 D = Q.J + Q.K
0 1 0 0
1 0 1 1
0 1 1 0 0
1 1 Q(t) Q(t)
1 0 0 1 1
1 0 1 1 1
Truth table of what 1 1 0 1 1
we desire to make
1 1 1 0 0
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