Computer Architecture and

Organization
Sample Questions and Answers
Part-A
(3*7 = 21 Marks)
Instruction (s): This section will have seven (7) questions. Of which all are to be
answered.
1) What is meant by PnP in computer architecture? State any two (2) primary factors for its
implementation.
Answer:
i. PnP Bios
ii. Extended System Configuration Data (ESCD)
iii. PnP Operating System

2) Bring out any four types of internal memories apart from the RAM and ROM.
Answer:
i. Cache Memory:
ii. Virtual memory
iii. Bobble Memory:
iv. Register:
v. Address:

3) State and write briefly on any three (3) Interrupts: Mechanism by which other modules may
interrupt the typical processing sequence.
Answer:
i. Program (overflow, division by zero)
ii. Timer (Generated by internal processor timer, used in pre-emptive
multitasking).
iii. I/O (from I/O controller).
iv. Hardware failure (memory parity error).

4) List any three (3) types of random access memories

Answer:
Static Random Access Memory (SRAM)
Dramatic Random Access Memory (DRAM)
SDRAM Synchronous Dynamic Random Access Memory (SDRAM)

5) What is meant by BUS Abstraction? State any two (2) prominent examples.
 Answer:
 Bus arbitration is the process of shifting control of a bus from one processor unit to
another. Arbitration controls how devices obtain access to the bus.

Examples:
i. Centralised arbitration relies on a single controller, whereas.
ii. Distributed arbitration allows devices to request access directly.

6) List any three (3) tasks for PnP automation.

Answer:
i. Interrupt Request (IRQ)
ii. Direct memory access (DMA)
iii. Memory addresses
iv. Input / Output (I/O) configuration

7) What are data paths used for? State the two (2) types of data path design approaches.
Answer:
Data paths implement internal circuitry and enhance data processing and exchange.
i. Single Data Path (Clock Cycle Per Instruction)
ii. Multiple Cycle
8) Give a brief description of a Bus interconnection pathway and state any two (2) examples
of it.
Answer:
 A Bus interconnection pathway is a connection pathway connecting two or more
devices using a broadcast signal
 Possible BUS int. A bus connection will include single and multiple BUS structures.
Examples: I. Control/Address/Data bus (PC) ii. Uni-bus (DEC-PDP).

9) What are Control Lines/control buses used for? Give any two (2) primary functions of it.
Answer:
 Control lines/control oversee and coordinate component operations by controlling
data flow and ensuring device synchronisation.

Some of their Major functions will include:

i. II Controlling Access
ii. Command Propagation from CPU to I/O
iii. Transfer Management/regulate data flow as per desired need
iv. Device Synchronizing Operations
10) What is meant by a Random/Direct Access Memory? Support your answer with an
illustration.
Answer:
11) In not more than two sentences, describe Random Access Memory Organisation.
Answer:
 RAM Organization
i. At its heart is a storage unit composed of many addressable locations (2n), each of
which stores a w-bit (word).
ii. In RAM, individual bits are not directly accessible unless w=1.

12) In brief, write on any two of the following memory characteristics: Access time (tA), Cycle
time (tM), and Data Transfer Rate/bandwidth (bM).
Answer:
 Access time (tA): The time between receiving a read request signaled by a memory and
delivering the requested information to output terminals.
 Cycle time (tM): The elapsed time between the start of two consecutive access operations.
This is also known as the time interval between the beginning of one cycle and the start of
the next.
 Data Transfer Rate/bandwidth (bM): The maximum amount of data/information that can be
transferred to or from the memory per unit of time. This is measured in bits or words per
second.

13) State and write on any three (3) major Elements of Bus Design based on types.
Answer:
i. Dedicated Design: Designated to a specific function (e.g. address bus) or a physical
subset of components (e.g. I/O bus connecting I/O modules).
ii. Multiplexed Design: Used for both addresses and data, where a valid control line is
required to identify whether the data is an address or data.
iii. Parallel and Serial Design: They transmit data simultaneously on multiple wires.
iv. Synchronous Design: Use a clock signal to synchronize data transfer, and
asynchronous buses rely on handshaking signals to manage data flow.

14) State the four (4) stages through which a pipeline processor executes an
instruction.
Answer:
- Fetch - Decode - Execute - Write

15) State any three (3) CPU Module Interconnection/Transfer functions

Answer:
  Reads and sends instructions and data from various models
 Writes out data (after processing/execution of an operation)
 Sends control signals to other units for proper system coordination.
 Receives (& acts on) interrupts as the case may require.

Part-B
(10*2 = 20 Marks)
Instruction: This section will include four (4) questions—two (2) questions to be answered.

16) Describe the system interconnection structure and write briefly about the memory module
interconnection/transfer backup with an illustration.
Answer:
This is a collection of paths connecting various modules or components of the Bus
Interface in the Microprocessor:
 This consists of components such as CPU, memory, I/O device, etc.
 They communicate with each other to perform a specified task. The interconnection
module/structure is used, which depends on the exchange of data between different
devices or modules.
 With this connection, different types of data transfer are formed
Memory Module Interconnection/Transfer: Receives and sends data, receives
addresses (of locations), receives control signals, and consists of N words of equal
length.
i. Read operation –collecting input from the peripheral device.
ii. Write operation – to transfer/store in memory or storage medium.
iii. Timing – electrical pulses generated for reading and writing from devices to
synchronise

17) The efficiency of Direct Access Memory is based on certain structural and logical
principles. Write about any four (4) principles of these implementation procedures,
including any two advantages and disadvantages. ……………………………………….
10-Marks.

Answer:
 i. Indexing or Address Mapping: -Systems frequently keep a map or index that
connects logical records to physical memory locations (such as B-trees or hash maps
in databases).
ii. Fixed-Length Records: - Direct access systems typically utilise fixed-size blocks,
making it simple to calculate the physical address using formulas such as Base +
(Record Number × Block Size).
iii. Address Calculation Logic: - Each place, particularly in RAM, has a unique address
determined by the CPU and routed to memory via address buses.
iv. Storage Medium Support: - Disc scheduling techniques and sector-based addressing
enable direct access to data tracks and sectors on media such as hard discs.
 Advantages:
i. Sequential files and fast direct access.
ii. Efficient for applications requiring frequent searches and occasional insertions (such
as banking and payroll).
iii. It supports both range queries and random access.

 Disadvantages/Limitations:
i. Additional storage is required for index and overflow locations.
ii. Performance can suffer if the overflow area grows too large, forcing reorganisations.
iii. In highly dynamic contexts, not as efficient as pure indexed systems (such as B+
trees).

18) Pipeline organisation design takes two folds, (Instruction and Arithmetic Pipeline). Briefly
describe the backup illustration depicting the operation of a Multiplexer and an Adder.
Answer:
i. The instruction Pipeline: An instruction pipeline accepts sequential instructions from
memory and executes them in other areas. Both the data and instruction streams show
evidence of pipeline processing.
ii. Arithmetic Pipeline - An arithmetic pipeline divides an arithmetic problem into sub-
problems that can be processed in independent pipeline segments. It is used for various
calculations, including multiplication and floating-point operations.
 The above figure depicts the registers R1, R2, R3, and R4, with the output of a segment's
combinational circuit used as an input register for the next segment.

 Inputs: inputs are received (Ai, Bi and Ci) and were stored in R1, R2, and R4
 Multiplication Operation:
values in R1 and R2 are sent to a Multiplier and
- Compute Ai*Bi and store result in R3
 Addition Operation: values from R3 (i.e., Ai*Bi) and R4 (I.e., Ci) are fed into Adder
- Adder operation (Ai*Bi) + C and then stored to R5.
- Final Output: R5 contains the computed result which is:
R5 = (Ai * Bi) + Ci

19) Write in brief on the Data Path – Instruction Fetch with specifics to obtaining instructions
backup with an illustration, and state any two (2) R-type instructions requirements in MIPS
Answer:
All program execution starts with fetching sets of instructions from main memory and then
incrementing the program counter to point to the next instruction.
Hence, to obtain instructions, you must first:
 Instructions are kept in memory.
 A program counter (PC) holds the location of the current/next instruction.
 An adder increments the PC to the address of the next instruction.

 R-type instructions requirement in MIPS

i. I register a file for storing register contents
ii. ALU to process read register values

20) Bring out the Block diagram of Babbage’s Proposed Analytical Engine and write on the
following:
i. Arithmetic Logical Unit (the Mill)
ii. Operation Control (I/O)
iii. Instruction pool (Operation Card and Variable card).
 Answer:

i. Arithmetic Logical Unit (the Mill) – designed to perform the basic arithmetic
operations.
ii. Operation Control (I/O) – punch cards and printers were proposed.
iii. Instruction pool – the analytical engine was composed of two sequences of punch
cards:
- Operation Card – used for operations executed in the mill.
- Variable card – used to specify the location for the output.
 Part – C
(18 * 1 = 18 Marks)
Compulsory Question
21) Disputes between devices seeking memory are resolved through abstraction using DMA
controllers and other controllers or CPUs. Based on the above, write on the following:
i. Synchronous Timing Bus Abstraction and Asynchronous Timing – Read and Write
Abstraction. …………………………………………..… 6 –Marks
Answer:
Synchronous Timing Bus Abstraction:
 Events are synchronised/coordinated in time.
 Synchronous data transmission is used to quickly send large amounts of data
from one location to another.
 Synchronous – the clock determines the occurrence of events, the processor
reads from memory and writes to memory

Asynchronous Timing – Read and Write Abstraction:

 Read - Asynchronous Timing - (no clock) The Interval between A and B is
not the same as in B and C. The processor reads from memory.
 Write - Asynchronous Timing - Asynchronous - (no clock) The Interval
between A and B is not the same as between B and C. The Processor writes
to memory.

ii. Depict the high-speed bus Architecture and state any two (2) advantages and
disadvantages…………………………………………………….... 6 – Marks
Answer:

Advantages of High-Speed Bus Architecture

- Provides connection to high-speed LAN
- Uses expansion slot
Disadvantages of High-Speed Bus Architecture
- Independent of the processor, hence integrates high device demand
- Changes in CPU design do not affect it.
iii. Give an illustration of the I/O-Module System Architecture and write on, “System
Buses and Links to Peripheral Devices”…… 6 - Marks
Answer:

 Links to Peripheral devices:

 Receive and send data from the computer to the peripheral,
 Receive addresses from PC (e.g. port number to identify peripheral) and send
interrupt signals.
 System Bus – a communication system that transfers data/information between
components in the computer system.
 Address lines- Address lines in computer architecture are physical connections that
transmit address signals from the CPU to memory or other devices, representing binary
digits (0 or 1).
 Data Lines – Data lines, part of the data bus, transmit binary information between the
CPU, memory, and input/output devices, with the width determining simultaneous data
transfer efficiency.
 Control lines - transmit timing and command signals to manage data and address lines
shared by all components, ensuring proper coordination and synchronisation of system
operations.