5 4 3 2 1

REV Description Date

V1.0 First Release 2016-7-12

D D

AX7010 Schematics
黑金ZYNQ硬件平台
C C

Page Number Description

Page01 Cover Page

B
Page02 Block Diagram B

Page03 Zynq-7000 JTAG & Bank0

Page04 Zynq-7000 MIO Config
Page05 Zynq-7000 Bank13-34-35
Page06 Zynq-7000 Bank502
Page07 Zynq-7000 Power
Page08 DDR3
Page09 GPHY
Page10 USB OTG
Page11 FLASH, RTC, EEPROM
A
Page12 LED, KEY A

Page13 UART, SD
Page14 HDMI
Page15 EXTEND IO Title
Zynq-7000 Cover Page
Page16 POWER Size Document Number Rev
AX7010 开发板原理图 1.0

Date: Thursday, April 12, 2018 Sheet 1 of 16

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Title
Zynq-7000 Block diagram
Size Document Number Rev
AX7010 开发板原理图 1.0

Date: Thursday, April 12, 2018 Sheet 2 of 16

5 4 3 2 1
 5 4 3 2 1

U1A
M9
DXP_0 M10
DXN_0 K9
VP_0 L10
VN_0
F9 FPGA_TCK
TCK_0 J6 FPGA_TMS
D TMS_0 F6 FPGA_TDO VCC3V3 VCC1V8 AVCC VCC1V8 D
TDO_0 G6 FPGA_TDI
TDI_0
L1
R10 R1 4.7K
INIT_B_0 L6 R2 4.7K
PROGRAM_B_0 M6
CFGBVS_0 R11 FPGA_DONE 120OHM@100Mhz
BANK0 DONE_0 FPGA_DONE 4
C1 C2
K10 AGND 470nF 0.1uF
VREFN_0 L9
VREFP_0 AGND AGND
F11 VCC3V3
VCCBATT_0 J9
VCCADC_0
T6
RSVDVCC1 R6
RSVDVCC2 N6
RSVDVCC3
F10
RSVDGND J10 L2 120OHM@100Mhz
GNDADC_0

Zynq7010/7020
AGND

AGND

C C
VPLL +3P3V

VPHY
USB_5V

C4

12
24
46
U2

3
8
0.1uF
USB_5V 40

VPHY
VPLL

VCCIO1
VCCIO2
VCCIO3
+3P3OUTV VREGIN

39 13 R4 33R FPGA_TCK
J1 C7 C8 0.1uF 38 VCCD ADBUS0/TCK 14 R5 33R FPGA_TDI
10uF C9 0.1uF 37 VCCCORE ADBUS1/TDI 15 R135 33R FPGA_TDO
1 VCCA ADBUS2/TDO 16 R6 33R FPGA_TMS
VCC 2 6 ADBUS3/TMS 17
D- 3 7 DM ADBUS4 18
D+ 4 DP ADBUS5 19
ID 5 R7 10K 34 ADBUS6 20
+3P3V
SH1
SH2
SH3
SH4

GND R8 12.1K 1% 5 RESET ADBUS7

REF
MINI_USB C10 21
6
7
8
9

0.1uF EECS 45 ACBUS0 25

EECLK 44 EECS ACBUS1 26
EEDATA 43 EECLK ACBUS2 27
C13 27pF EEDATA ACBUS3 28
ACBUS4 29
1 ACBUS5 30
B XCSI ACBUS6 31 B

Y1 2 ACBUS7 32
XCSO ACBUS8 33
12Mhz ACBUS9
42

AGND1
AGND2
AGND3
TEST

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
C14 27pF
FT232HL

4
9
41

10
11
22
23
35
36
47
48
+3P3OUTV VPLL +3P3OUTV VPHY
+3P3V +3P3OUTV +3P3V L3 120OHM@100Mhz L4 120OHM@100Mhz
L5 120OHM@100Mhz

+3P3V R10 R11 R12 C15 C21 C22 C23

10K 10K 10K C16 C17 C18 C19 C20 0.1uF 0.1uF 0.1uF 0.1uF
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
U6
8 1 EECS
7 VCC CS 2 EECLK
C24 6 NC1 CLK 3 EEDATA
0.1uF 5 NC2 DI 4 R13 2K
A A
VSS DO

93LC56BISN

Title
Zynq-7000 JTAG & Bank0
Size Document Number Rev
AX7010 开发板原理图 1.0

Date: Thursday, April 12, 2018 Sheet 3 of 16

5 4 3 2 1
 5 4 3 2 1

U1B
VCC3V3

E6 MIO0_LED 12
PS_MIO0_500 A7 QSPI_CS MIO0_LED
D
VCC3V3
BOOT OPTION PS_MIO1_500
PS_MIO2_500
B8
D6
QSPI_D0 QSPI_CS
QSPI_D0
11
11
D
QSPI_D1 11
PS_MIO3_500 B7 QSPI_D2 QSPI_D1
PS_MIO4_500 QSPI_D2 11
A6 QSPI_D3 11
R15 20K PS_MIO8 PS_MIO5_500 A5 R14 33R QSPI_SCK QSPI_D3
MIO[8] =1 ----MIO bank1 voltage=1.8V PS_MIO6_500 QSPI_SCK 11
R16 20K QSPI_D0 MIO[2] =0 ----cascaded JTAG D8 PS_MIO7
R17 20K QSPI_D1 MIO[3] =0 ----JTAG/NAND/Quad-SPI/SD BANK500 PS_MIO7_500
PS_MIO8_500
D5 PS_MIO8 PS_MIO7
PS_MIO8
15
15
R18 20K QSPI_SCK MIO[6] =0 ----PLL used B5 PS_MIO9 15
R19 20K PS_MIO7 PS_MIO9_500 E9 PS_MIO10 PS_MIO9
MIO[7] =0 ----MIO bank0 voltage=3.3V PS_MIO10_500 PS_MIO10 15
C6 PS_MIO11 15
PS_MIO11_500 D9 PS_MIO12 PS_MIO11
PS_MIO12_500 PS_MIO12 15
E8 MIO13_LED 12
PS_MIO13_500 C5 PS_MIO14 MIO13_LED
PS_MIO14_500 PS_MIO14 15
C8 PS_MIO15 15
PS_MIO15_500 PS_MIO15
C7 PS_POR_B 9 VCC3V3
VCC3V3 PS_POR_B_500 PS_POR_B X1
E7 R20 33R 3 4
PS_CLK_500 OUT VDD
MIO[5] MIO[4]
R22 Boot Mode
J13 (QSPI_D3) (QSPI_D2 ) 2 1
1K GND OE C25
JTAG 0 0 Zynq7010/7020
33.333333Mhz 0.1uF
1 R24 20K QSPI_D3
NAND 0 1
JTAG

2
QSPI

3 R23 20K QSPI_D2 QSPI-FLASH 1

4 0
SD

VCC3V3
SD Card 1 1
R21
C 4 HEADER C
10K

VCC1V8

U1C
VCC1V8 R25
1K 1%

E11
POWER ON RESET PS_MIO_VREF_501
A19 ETH_TXCK 10
PS_MIO16_501 E14 ETH_TXD0 ETH_TXCK R26 C26
VCC3V3 VCC3V3 PS_MIO17_501 ETH_TXD0 10
B18 ETH_TXD1 10 1K 1% 0.01uF
PS_MIO18_501 D10 ETH_TXD2 ETH_TXD1
PS_MIO19_501 ETH_TXD2 10
A17 ETH_TXD3 10
PS_MIO20_501 F14 ETH_TXCTL ETH_TXD3
PS_MIO21_501 ETH_TXCTL 10
B17 ETH_RXCK 10
PS_MIO22_501 D11 ETH_RXD0 ETH_RXCK
KEY1 PS_MIO23_501 ETH_RXD0 10
C27 A16 ETH_RXD1 10
U7 0.1uF R27 PS_MIO24_501 F15 ETH_RXD2 ETH_RXD1
PS_MIO25_501 ETH_RXD2 10
1 2 3 4 NC A15 ETH_RXD3 10
P1 P2 #MR VDD PS_MIO26_501 D13 ETH_RXCTL ETH_RXD3
PS_MIO27_501 ETH_RXCTL 10
C16 OTG_DATA4 10
Button 1 2 PS_POR_B PS_MIO28_501 C13 OTG_DIR OTG_DATA4
GND #RESET PS_MIO29_501 OTG_DIR 10
C15 OTG_STP 10
TCM811TERCTR PS_MIO30_501 E16 OTG_NXT OTG_STP
B BANK501 PS_MIO31_501
PS_MIO32_501
A14 OTG_DATA0 OTG_NXT
OTG_DATA0
10
10
B
D15 OTG_DATA1 10
PS_MIO33_501 A12 OTG_DATA2 OTG_DATA1
PS_MIO34_501 OTG_DATA2 10
F12 OTG_DATA3 10
PS_MIO35_501 A11 OTG_CLK OTG_DATA3
PS_MIO36_501 OTG_CLK 10
A10 OTG_DATA5 10
PS_MIO37_501 E13 OTG_DATA6 OTG_DATA5
PS_MIO38_501 OTG_DATA6 10
C18 OTG_DATA7 10
PS_MIO39_501 D14 R87 40.2 1% OTG_DATA7
SD_CLK
PS_MIO40_501 SD_CLK 10
C17 SD_CMD 10
PS_MIO41_501 E12 SD_D0 SD_CMD
PS_MIO42_501 SD_D0 10
A9 SD_D1 10
VCC1V8 PS_MIO43_501 F13 SD_D2 SD_D1
PS_MIO44_501 SD_D2 10
B15 SD_D3 10
PS_MIO45_501 D16 OTG_RESETN SD_D3
PS_MIO46_501 OTG_RESETN 10
B14 SD_CD 10
R28 PS_MIO47_501 B12 UART_TX SD_CD
PS_MIO48_501 UART_TX 10
10K C12 UART_RX 10
R0603 PS_MIO49_501 B13 MIO_KEY1 UART_RX
PS_MIO50_501 MIO_KEY1 10
B9 MIO_KEY2 10
PS_MIO51_501 C10 ETH_MDC MIO_KEY2
PS_MIO52_501 ETH_MDC 10
PS_SRST_B C11 ETH_MDIO 10
PS_MIO53_501 ETH_MDIO
B10 PS_SRST_B
PS_SRST_B_501

Zynq7010/7020

A A

Title
Zynq-7000 PS MIO
Size Document Number Rev
AX7010 开发板原理图 1.0

Date: Thursday, April 12, 2018 Sheet 4 of 16

5 4 3 2 1
 5 4 3 2 1

VCC3V3
X3
4 3 33R R158 PL_GCLK
VDD OUT
U1F VCC3V3
1 2
C238 OE GND BANK34
0.1uF 50Mhz
11 RTC_I2C_SCL R19 U14 15
D
T19 IO_0_34 IO_L11P_T1_SRCC_34 U15 IO1_7P D
11 EEPROM_I2C_SCL IO_25_34 IO_L11N_T1_SRCC_34 IO1_7N 15
15 T11 U18 PL_GCLK
IO1_15P T10 IO_L1P_T0_34 IO_L12P_T1_MRCC_34 U19
15 IO1_15N IO_L1N_T0_34 IO_L12N_T1_MRCC_34
15 T12 N18 14
IO1_14P U12 IO_L2P_T0_34 IO_L13P_T2_MRCC_34 P19 HDMI_CLK_P
15 IO1_14N IO_L2N_T0_34 IO_L13N_T2_MRCC_34 HDMI_CLK_N 14
15 U13 N20 14
IO1_12P IO_L3P_T0_DQS_PUDC_B_34 IO_L14P_T2_SRCC_34 HDMI_D2_P
15 V13 P20 14
IO1_12N IO_L3N_T0_DQS_34 IO_L14N_T2_SRCC_34 HDMI_D2_N
15 V12 T20 14
IO1_12P IO1_13P W13 IO_L4P_T0_34 IO_L15P_T2_DQS_34 U20 HDMI_D1_P
15 IO1_13N IO_L4N_T0_34 IO_L15N_T2_DQS_34 HDMI_D1_N 14
15 T14 V20 14
R29 IO1_11P T15 IO_L5P_T0_34 IO_L16P_T2_34 W20 HDMI_D0_P
15 IO1_11N IO_L5N_T0_34 IO_L16N_T2_34 HDMI_D0_N 14
1K 15 P14 Y18 14
IO1_2P IO_L6P_T0_34 IO_L17P_T2_34 HDMI_CEC
15 R14 Y19 14
IO1_2N IO_L6N_T0_VREF_34 IO_L17N_T2_34 HDMI_HPD
15 Y16 V16 14
IO1_3P IO_L7P_T1_34 IO_L18P_T2_34 HDMI_OUT_EN
15 Y17 W16
IO1_3N W14 IO_L7N_T1_34 IO_L18N_T2_34 R16 EEPROM_I2C_SDA 11
15 IO1_5P IO_L8P_T1_34 IO_L19P_T2_34 HDMI_SDA 14
15 Y14 R17 12
IO1_5N T16 IO_L8N_T1_34 IO_L19N_T3_VREF_34 T17 KEY4
15 IO1_9P IO_L9P_T1_DQS_34 IO_L20P_T3_34 KEY3 12
15 U17 R18 14
IO1_9N IO_L9N_T1_DQS_34 IO_L20N_T3_34 HDMI_SCL
15 V15 V17 15
IO1_4P W15 IO_L10P_T1_34 IO_L21P_T3_DQS_34 V18 IO1_10P
15 IO1_4N IO_L10N_T1_34 IO_L21N_T3_DQS_34 IO1_10N 15
W18 15
IO_L22P_T3_34 W19 IO1_1P
IO_L22N_T3_34 IO1_1N 15
N17 15
IO_L23P_T3_34 P18 IO1_6P
IO_L23N_T3_34 IO1_6N 15
P15 15
IO_L24P_T3_34 P16 IO1_8P
IO_L24N_T3_34 IO1_8N 15

C Zynq7010/7020 C

U1G VCCIO
U1E VCC3V3 BANK35

BANK13 L16 15
G14 IO_L11P_T1_SRCC_35 L17 IO2_10P
(Z7020 Only) J15 IO_0_35 IO_L11N_T1_SRCC_35 K17 IO2_10N 15
IO_25_35 IO_L12P_T1_MRCC_35 IO2_7P 15
V5 15 C20 K18 15
U7 IO_L6N_T0_VREF_13 IO1_17P B20 IO_L1P_T0_AD0P_35 IO_L12N_T1_MRCC_35 H16 IO2_7N
IO_L11P_T1_SRCC_13 15 IO1_17N IO_L1N_T0_AD0N_35 IO_L13P_T2_MRCC_35 IO2_15P 15
V7 15 B19 H17 15
T9 IO_L11N_T1_SRCC_13 IO1_16P A20 IO_L2P_T0_AD8P_35 IO_L13N_T2_MRCC_35 J18 IO2_15N
IO_L12P_T1_MRCC_13 15 IO1_16N IO_L2N_T0_AD8N_35 IO_L14P_T2_AD4P_SRCC_35 IO2_4P 15
U10 E17 H18 15
Y7 IO_L12N_T1_MRCC_13 D18 IO_L3P_T0_DQS_AD1P_35 IO_L14N_T2_AD4N_SRCC_35 F19 IO2_4N
IO_L13P_T2_MRCC_13 IO_L3N_T0_DQS_AD1N_35 IO_L15P_T2_DQS_AD12P_35 IO2_2P 15
Y6 15 D19 F20 15
IO_L13N_T2_MRCC_13 IO2_12P IO_L4P_T0_35 IO_L15N_T2_DQS_AD12N_35 IO2_2N
Y9 15 D20 G17 15
B IO_L14P_T2_SRCC_13 IO2_12N IO_L4N_T0_35 IO_L16P_T2_35 IO2_14P B
Y8 15 E18 G18 15
V8 IO_L14N_T2_SRCC_13 IO2_13P E19 IO_L5P_T0_AD9P_35 IO_L16N_T2_35 J20 IO2_14N
IO_L15P_T2_DQS_13 15 IO2_13N IO_L5N_T0_AD9N_35 IO_L17P_T2_AD5P_35 IO2_9P 15
W8 15 F16 H20 15
W10 IO_L15N_T2_DQS_13 IO2_1P F17 IO_L6P_T0_35 IO_L17N_T2_AD5N_35 G19 IO2_9N
IO_L16P_T2_13 15 IO2_1N IO_L6N_T0_VREF_35 IO_L18P_T2_AD13P_35 IO2_3P 15
W9 15 M19 G20 15
U9 IO_L16N_T2_13 IO2_6P M20 IO_L7P_T1_AD2P_35 IO_L18N_T2_AD13N_35 H15 IO2_3N
IO_L17P_T2_13 15 IO2_6N IO_L7N_T1_AD2N_35 IO_L19P_T3_35 IO2_16P 15
U8 15 M17 G15 15
W11 IO_L17N_T2_13 IO2_11P M18 IO_L8P_T1_AD10P_35 IO_L19N_T3_VREF_35 K14 IO2_16N
IO_L18P_T2_13 15 IO2_11N IO_L8N_T1_AD10N_35 IO_L20P_T3_AD6P_35 IO2_17P 15
Y11 15 L19 J14 15
T5 IO_L18N_T2_13 IO2_5P L20 IO_L9P_T1_DQS_AD3P_35 IO_L20N_T3_AD6N_35 N15 IO2_17N
IO_L19P_T3_13 15 IO2_5N IO_L9N_T1_DQS_AD3N_35 IO_L21P_T3_DQS_AD14P_35 KEY1 12
U5 15 K19 N16 12
Y12 IO_L19N_T3_VREF_13 IO2_8P J19 IO_L10P_T1_AD11P_35 IO_L21N_T3_DQS_AD14N_35 L14 KEY2
IO_L20P_T3_13 15 IO2_8N IO_L10N_T1_AD11N_35 IO_L22P_T3_AD7P_35 RTC_I2C_SDA 11
Y13 L15 11
V11 IO_L20N_T3_13 IO_L22N_T3_AD7N_35 M14 RTC_RESET
IO_L21P_T3_DQS_13 IO_L23P_T3_35 LED1 12
V10 M15 12
V6 IO_L21N_T3_DQS_13 IO_L23N_T3_35 K16 LED2
IO_L22P_T3_13 IO_L24P_T3_AD15P_35 LED3 12
W6 J16 12
IO_L22N_T3_13 IO_L24N_T3_AD15N_35 LED4

Zynq7010/7020
Zynq7010/7020

A A

Title
Zynq-7000 Bank13 & 34 & 35
Size Document Number Rev
AX7010 开发板原理图 1.0

Date: Thursday, April 12, 2018 Sheet 5 of 16

5 4 3 2 1
 5 4 3 2 1

D D

U1D

8 DDR3_D0
DDR3_D0 C3
PS_DDR_DQ0_502
BANK502 PS_DDR_A0_502
N2 DDR3_A0
DDR3_A0 8
8 DDR3_D1 B3 K2 DDR3_A1 8
DDR3_D1 PS_DDR_DQ1_502 PS_DDR_A1_502 DDR3_A1
8 DDR3_D2 A2 M3 DDR3_A2 8
DDR3_D2 PS_DDR_DQ2_502 PS_DDR_A2_502 DDR3_A2
8 DDR3_D3 A4 K3 DDR3_A3 8
DDR3_D3 PS_DDR_DQ3_502 PS_DDR_A3_502 DDR3_A3
8 DDR3_D4 D3 M4 DDR3_A4 8
DDR3_D4 PS_DDR_DQ4_502 PS_DDR_A4_502 DDR3_A4
8 DDR3_D5 D1 L1 DDR3_A5 8
DDR3_D5 PS_DDR_DQ5_502 PS_DDR_A5_502 DDR3_A5
8 DDR3_D6 C1 L4 DDR3_A6 8
DDR3_D6 PS_DDR_DQ6_502 PS_DDR_A6_502 DDR3_A6
8 DDR3_D7 E1 K4 DDR3_A7 8
DDR3_D7 PS_DDR_DQ7_502 PS_DDR_A7_502 DDR3_A7
8 DDR3_D8 E2 K1 DDR3_A8 8
DDR3_D8 PS_DDR_DQ8_502 PS_DDR_A8_502 DDR3_A8
8 DDR3_D9 E3 J4 DDR3_A9 8
DDR3_D9 PS_DDR_DQ9_502 PS_DDR_A9_502 DDR3_A9
8 DDR3_D10 G3 F5 DDR3_A10 8
DDR3_D10 PS_DDR_DQ10_502 PS_DDR_A10_502 DDR3_A10
8 DDR3_D11 H3 G4 DDR3_A11 8
DDR3_D11 PS_DDR_DQ11_502 PS_DDR_A11_502 DDR3_A11
8 DDR3_D12 J3 E4 DDR3_A12 8
DDR3_D12 PS_DDR_DQ12_502 PS_DDR_A12_502 DDR3_A12
8 DDR3_D13 H2 D4 DDR3_A13 8
DDR3_D13 PS_DDR_DQ13_502 PS_DDR_A13_502 DDR3_A13
8 DDR3_D14 H1 F4 DDR3_A14 8
DDR3_D14 PS_DDR_DQ14_502 PS_DDR_A14_502 DDR3_A14
8 DDR3_D15 J1
DDR3_D15 DDR3_D16 P1 PS_DDR_DQ15_502 L5 DDR3_BA0
C 8 8 C
DDR3_D16 PS_DDR_DQ16_502 PS_DDR_BA0_502 DDR3_BA0
8 DDR3_D17 P3 R4 DDR3_BA1 8
DDR3_D17 PS_DDR_DQ17_502 PS_DDR_BA1_502 DDR3_BA1
8 DDR3_D18 R3 J5 DDR3_BA2 8
DDR3_D18 PS_DDR_DQ18_502 PS_DDR_BA2_502 DDR3_BA2
8 DDR3_D19 R1
DDR3_D19 DDR3_D20 T4 PS_DDR_DQ19_502 A1 DDR3_DM0
8 DDR3_D20 PS_DDR_DQ20_502 PS_DDR_DM0_502 DDR3_DM0 8
8 DDR3_D21 U4 F1 DDR3_DM1 8
DDR3_D21 PS_DDR_DQ21_502 PS_DDR_DM1_502 DDR3_DM1
8 DDR3_D22 U2 T1 DDR3_DM2 8
DDR3_D22 PS_DDR_DQ22_502 PS_DDR_DM2_502 DDR3_DM2
8 DDR3_D23 U3 Y1 DDR3_DM3 8
DDR3_D23 PS_DDR_DQ23_502 PS_DDR_DM3_502 DDR3_DM3
8 DDR3_D24 V1
DDR3_D24 DDR3_D25 Y3 PS_DDR_DQ24_502 L2 DDR3_CLK0_P VCC1V5
8 DDR3_D25 PS_DDR_DQ25_502 PS_DDR_CKP_502 DDR3_CLK0_P 8
8 DDR3_D26 W1 M2 DDR3_CLK0_N 8
DDR3_D26 PS_DDR_DQ26_502 PS_DDR_CKN_502 DDR3_CLK0_N
8 DDR3_D27 Y4
DDR3_D27 DDR3_D28 Y2 PS_DDR_DQ27_502 H5 DDR3_VRP R30 80.6R 1%
8 DDR3_D28 PS_DDR_DQ28_502 PS_DDR_VRP_502
8 DDR3_D29 W3 G5 DDR3_VRN R31 80.6R 1%
DDR3_D29 DDR3_D30 V2 PS_DDR_DQ29_502 PS_DDR_VRN_502
8 DDR3_D30 PS_DDR_DQ30_502
8 DDR3_D31 V3
DDR3_D31 PS_DDR_DQ31_502 N1 DDR3_S0
PS_DDR_CS_B_502 DDR3_S0 8
8 DDR3_DQS0_P C2 M5 DDR3_WE 8
DDR3_DQS0_P PS_DDR_DQS_P0_502 PS_DDR_WE_B_502 DDR3_WE
8 DDR3_DQS0_N B2 P5 DDR3_CAS 8
DDR3_DQS0_N PS_DDR_DQS_N0_502 PS_DDR_CAS_B_502 DDR3_CAS
8 DDR3_DQS1_P G2 P4 DDR3_RAS 8
DDR3_DQS1_P PS_DDR_DQS_P1_502 PS_DDR_RAS_B_502 DDR3_RAS
8 DDR3_DQS1_N F2 N3 DDR3_CKE 8
DDR3_DQS1_N PS_DDR_DQS_N1_502 PS_DDR_CKE_502 DDR3_CKE
8 DDR3_DQS2_P R2 N5 DDR3_ODT 8
DDR3_DQS2_P PS_DDR_DQS_P2_502 PS_DDR_ODT_502 DDR3_ODT
8 DDR3_DQS2_N T2
DDR3_DQS2_N DDR3_DQS3_P W5 PS_DDR_DQS_N2_502 B4 DDR3_RESET
8 DDR3_DQS3_P PS_DDR_DQS_P3_502 PS_DDR_DRST_B_502 DDR3_RESET 8
8 DDR3_DQS3_N W4
DDR3_DQS3_N PS_DDR_DQS_N3_502

Zynq7010/7020

B B

A A

Title
Zynq-7000 Bank502
Size Document Number Rev
AX7010 开发板原理图 1.0

Date: Thursday, April 12, 2018 Sheet 6 of 16

5 4 3 2 1
 5 4 3 2 1

VCC3V3 VCC1V0
VCC3V3
VCCINT
VCCO_13 C28
47uF U1H
C33 C42 C43 C46 C47 C51
D D
C34 C35 C36 C38 C39 C29 C40 K6 IO POWER/CORE POWER 470nF 470nF 470nF 4.7uF 4.7uF 100uF
100uF 4.7uF 4.7uF 470nF 470nF 470nF 470nF VCC3V3 VCCO_0 VCC1V0

T8 R13
U11 VCCO_13_1 VCCINT_1 P12
W7 VCCO_13_2 VCCINT_2 N13 VCC1V8
VCC3V3 VCC3V3 Y10 VCCO_13_3 VCCINT_3 M12
VCCO_13_4 VCCINT_4 L13
VCC_AUX
VCCO_34 N19 VCCINT_5 K12
R15 VCCO_34_1 VCCINT_6 J13
T18 VCCO_34_2 VCCINT_7 H12 C58 C59 C60 C63
C52 C53 C54 C55 C56 C57 C61 C62 C30 V14 VCCO_34_3 VCCINT_8 G13 47uF 4.7uF 470nF 470nF
100uF 4.7uF 4.7uF 4.7uF 470nF 470nF 470nF 470nF 470nF W17 VCCO_34_4 VCCINT_9 VCC1V8
VCCIO_35 Y20 VCCO_34_5 VCC1V8
VCCO_34_6 VCC_PAUX
C19 N11
F18 VCCO_35_1 VCCAUX_1 R9
VCCIO_35 H14 VCCO_35_2 VCCAUX_2 P10 C64 C65 C66 C67 C68 C69
J17 VCCO_35_3 VCCAUX_3 N9 100uF 4.7uF 4.7uF 470nF 470nF 470nF
K20 VCCO_35_4 VCCAUX_4 L11
VCCO_35 VCC1V5 M16 VCCO_35_5 VCCAUX_5 J11
VCCO_35_6 VCCAUX_6 VCC1V8
A3 VCC1V0
C70 C71 C72 C73 C74 C75 C76 C77 C78 D2 VCCO_DDR_502_1 M8
100uF 4.7uF 4.7uF 4.7uF 470nF 470nF 470nF 470nF 470nF E5 VCCO_DDR_502_2 VCCPAUX_1 K8
VCC_BRAM
G1 VCCO_DDR_502_3 VCCPAUX_2 H8
H4 VCCO_DDR_502_4 VCCPAUX_3 F8
L3 VCCO_DDR_502_5 VCCPAUX_4 G9 VCC1V0 C79 C80 C82 C83
P2 VCCO_DDR_502_6 VCCPAUX_5 47uF 4.7uF 470nF 470nF
VCC1V5 R5 VCCO_DDR_502_7 H10
C C
U1 VCCO_DDR_502_8 VCCBRAM_1 G11
V4 VCCO_DDR_502_9 VCCBRAM_2
VCCO_DDR_502 VCC3V3 VCCO_DDR_502_10 VCC1V0
VCC1V0
B6
VCCPINT
C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 D7 VCCO_MIO0_500_1 R7
100uF 100uF 4.7uF 4.7uF 4.7uF 470nF 470nF 470nF 470nF 470nF 470nF 470nF VCC1V8 VCCO_MIO0_500_2 VCCPINT_1 P8
A13 VCCPINT_2 N7 C97 C98 C99 C100 C101 C102 C103 C104 C202 C105
B16 VCCO_MIO1_501_1 VCCPINT_3 L7 470nF 470nF 470nF 470nF 470nF 4.7uF 4.7uF 4.7uF 4.7uF 100uF
D12 VCCO_MIO1_501_2 VCCPINT_4 J7
VTTREF E15 VCCO_MIO1_501_3 VCCPINT_5 G7
VCC3V3 VCC1V8 VCCO_MIO1_501_4 VCCPINT_6 VCC1V8
H6 L6 120OHM@100Mhz
VCCO_MIO0_500 VCCO_MIO1_501 P6 PS_DDR_VREF0_502_1 G8 1 2
PS_DDR_VREF0_502_2 VCCPLL

C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117
100uF 4.7uF 470nF 470nF 100uF 4.7uF 4.7uF 470nF 470nF 470nF 10uF 470nF
C118 C119 Zynq7010/7020
0.01uF 0.1uF

B B

G16
G12
G10
D17

C14
E20
E10

K11

B11

A18
C4

B1

A8

F7
F3
U1I
GND59
GND58
GND57
GND56
GND55
GND54
GND53
GND52
GND51
GND50
GND49
GND48
GND47
GND46
GND45
T13 H19
U6 GND1 GND44 H13
U16 GND2 GND43 H11
V9 GND3 GND42 H9
V19 GND4 GND41 H7
W2 GND5 GND40 L12
W12 GND6 GND39 L8
Y5 GND7 GND38 K15
Y15 GND8 DIGITAL GND GND37 K13
R8 GND9 GND36 C9
R12 GND10 GND35 K7
R20 GND11 GND34 K5
T3 GND12 GND33 J12
T7 GND13 GND32 J8
GND14 GND31 J2
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29

GND30
P7
P9
P11
P13
P17
L18
M1
M7
M11
M13
N4
N8
N10
N12
N14

Zynq7010/7020

A A

Title
Zynq-7000 Cover Page
Size Document Number Rev
AX7010 开发板原理图 1.0

Date: Thursday, April 12, 2018 Sheet 7 of 16

5 4 3 2 1
 5 4 3 2 1

DDRVTT

C272 C271 C270 C268 C273 C274 C275 VCC1V5 VTTREF VCC1V5
4.7uF 4.7uF 4.7uF 0.1uF 0.1uF 0.01uF 0.01uF VCC1V5 VTTREF VCC1V5
C120
0.01uF C121
0.01uF

C122
C276 C277 C278 C279 C280 0.01uF C123

M8

G7
H1

C1
C9
D2

H2
H9

D9

N1
N9
R1
R9
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF

A1
A8

E9

B2

K2
K8
F1

M8

G7
H1

C1
C9
D2

H2
H9

D9

N1
N9
R1
R9
U8

A1
A8

E9

B2

K2
K8
F1
U9

VREFDQ
VREFCA

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
D D

VREFDQ
VREFCA

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
DDR3_A0 N3 E3 DDR3_D6 6
DDRVTT A0 DQ0 DDR3_D6
DDR3_A1 P7 F7 DDR3_D7 6 6 DDR3_A0 N3 E3 DDR3_D18 6
A1 DQ1 DDR3_D7 DDR3_A0 A0 DQ0 DDR3_D18
DDR3_A2 P3 F2 DDR3_D1 6 6 DDR3_A1 P7 F7 DDR3_D23 6
A2 DQ2 DDR3_D1 DDR3_A1 A1 DQ1 DDR3_D23
DDR3_A3 N2 F8 DDR3_D4 6 6 DDR3_A2 P3 F2 DDR3_D19 6
A3 DQ3 DDR3_D4 DDR3_A2 A2 DQ2 DDR3_D19
R157 40.2 1% DDR3_A4 P8 H3 DDR3_D3 6 6 DDR3_A3 N2 F8 DDR3_D21 6
A4 DQ4 DDR3_D3 DDR3_A3 A3 DQ3 DDR3_D21
DDR3_A0 DDR3_A5 P2 H8 DDR3_D0 6 6 DDR3_A4 P8 H3 DDR3_D16 6
A5 DQ5 DDR3_D0 DDR3_A4 A4 DQ4 DDR3_D16
R32 40.2 1% DDR3_A6 R8 G2 DDR3_D2 6 6 DDR3_A5 P2 H8 DDR3_D20 6
A6 DQ6 DDR3_D2 DDR3_A5 A5 DQ5 DDR3_D20
DDR3_A1 DDR3_A7 R2 H7 DDR3_D5 6 6 DDR3_A6 R8 G2 DDR3_D17 6
A7 DQ7 DDR3_D5 DDR3_A6 A6 DQ6 DDR3_D17
R33 40.2 1% DDR3_A8 T8 D7 DDR3_D14 6 6 DDR3_A7 R2 H7 DDR3_D22 6
A8 DQ8 DDR3_D14 DDR3_A7 A7 DQ7 DDR3_D22
DDR3_A2 DDR3_A9 R3 C3 DDR3_D8 6 6 DDR3_A8 T8 D7 DDR3_D28 6
A9 DQ9 DDR3_D8 DDR3_A8 A8 DQ8 DDR3_D28
R138 40.2 1% DDR3_A10 L7 C8 DDR3_D15 6 6 DDR3_A9 R3 C3 DDR3_D29 6
A10/AP DQ10 DDR3_D15 DDR3_A9 A9 DQ9 DDR3_D29
DDR3_A3 DDR3_A11 R7 C2 DDR3_D9 6 6 DDR3_A10 L7 C8 DDR3_D27 6
A11 DQ11 DDR3_D9 DDR3_A10 A10/AP DQ10 DDR3_D27
R136 40.2 1% DDR3_A12 N7 A7 DDR3_D13 6 6 DDR3_A11 R7 C2 DDR3_D24 6
A12/BC# DQ12 DDR3_D13 DDR3_A11 A11 DQ11 DDR3_D24
DDR3_A4 DDR3_A13 T3 A2 DDR3_D11 6 6 DDR3_A12 N7 A7 DDR3_D26 6
A13 DQ13 DDR3_D11 DDR3_A12 A12/BC# DQ12 DDR3_D26
R137 40.2 1% DDR3_A14 T7 B8 DDR3_D12 6 6 DDR3_A13 T3 A2 DDR3_D31 6
A14 DQ14 DDR3_D12 DDR3_A13 A13 DQ13 DDR3_D31
DDR3_A5 A3 DDR3_D10 6 6 DDR3_A14 T7 B8 DDR3_D25 6
DQ15 DDR3_D10 DDR3_A14 A14 DQ14 DDR3_D25
R144 40.2 1% DDR3_BA0 M2 A3 DDR3_D30 6
BA0 DQ15 DDR3_D30
DDR3_A6 DDR3_BA1 N8 F3 DDR3_DQS0_P 6 6 DDR3_BA0 M2
BA1 LDQS DDR3_DQS0_P DDR3_BA0 BA0
R139 40.2 1% DDR3_BA2 M3 G3 DDR3_DQS0_N 6 6 DDR3_BA1 N8 F3 DDR3_DQS2_P 6
BA2 LDQS DDR3_DQS0_N DDR3_BA1 BA1 LDQS DDR3_DQS2_P
DDR3_A7 6 DDR3_BA2 M3 G3 DDR3_DQS2_N 6
DDR3_BA2 BA2 LDQS DDR3_DQS2_N
R140 40.2 1% C7 DDR3_DQS1_P 6
UDQS DDR3_DQS1_P
DDR3_A8 DDR3_CLK0_P J7 B7 DDR3_DQS1_N 6 C7 DDR3_DQS3_P 6
CLK_P UDQS DDR3_DQS1_N UDQS DDR3_DQS3_P
R143 40.2 1% DDR3_CLK0_N K7 6 DDR3_CLK0_P J7 B7 DDR3_DQS3_N 6
CLK_N DDR3_CLK0_P CLK_P UDQS DDR3_DQS3_N
DDR3_A9 DDR3_CKE K9 E7 DDR3_DM0 6 6 DDR3_CLK0_N K7
CKE LDM DDR3_DM0 DDR3_CLK0_N CLK_N
R141 40.2 1% D3 DDR3_DM1 6 6 DDR3_CKE K9 E7 DDR3_DM2 6
UDM DDR3_DM1 DDR3_CKE CKE LDM DDR3_DM2
DDR3_A10 DDR3_S0 L2 D3 DDR3_DM3 6
CS UDM DDR3_DM3
R142 40.2 1% DDR3_RAS J3 L8 6 DDR3_S0 L2
RAS ZQ DDR3_S0 CS
DDR3_A11 DDR3_CAS K3 6 DDR3_RAS J3 L8
CAS DDR3_RAS RAS ZQ
C R150 40.2 1% DDR3_WE L3 J1 6 DDR3_CAS K3 C
WE NC1 DDR3_CAS CAS
DDR3_A12 J9 6 DDR3_WE L3 J1
NC2 DDR3_WE WE NC1
R145 40.2 1% DDR3_ODT K1 L1 J9
DDR3_A13 ODT NC3 L9 DDR3_ODT K1 NC2 L1
NC4 6 DDR3_ODT ODT NC3
R156 40.2 1% DDR3_RESET T2 M7 L9
DDR3_A14 RESET# NC5 R36 DDR3_RESET T2 NC4 M7
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
6

VSS10
VSS11
VSS12
DDR3_RESET RESET# NC5

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
R146 40.2 1% R35 240 1% R37

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSS10
VSS11
VSS12
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
DDR3_BA0 4.7K 240 1%
R149 40.2 1%
DDR3_BA1 H5TQ2G63FFR-PBC
B1
B9
D1
D8
E2
E8
F9
G1
G9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
R147 40.2 1% H5TQ2G63FFR-PBC

B1
B9
D1
D8
E2
E8
F9
G1
G9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DDR3_BA2
R148 40.2 1%
DDR3_S0
R153 40.2 1%
DDR3_RAS
R151 40.2 1%
DDR3_CAS
R152 40.2 1%
DDR3_WE
R154 40.2 1%
DDR3_ODT
R155 40.2 1%
DDR3_CKE VCC1V5

C128 C129 C130 C131

47uF 4.7uF 470nF 470nF
B B

VCC1V5
DDR3_CLK0_P

R34
80.6R 1% C148 C149 C150 C151 C152 C153 C154 C155 C156 C157 C158 C159 C160 C161 C162 C163
47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF

DDR3_CLK0_N

VCC1V5

DDR POWER For VTT/VREF C124 C125 C126 C127

47uF 4.7uF 470nF 470nF
VCC3V3 VTTREF
DDRVTT VCC1V5

R213 10K 1% C236

C263 U32 4.7uF
0.01uF VCC1V5
R214 10K 1% 1 10
2 REFIN VIN 9 R216 100K
3 VLDOIN PGOOD 8
A A
4 VO GND 7 C132 C133 C134 C135 C136 C137 C138 C139 C140 C141 C142 C143 C144 C145 C146 C147
PWRGND

C267 C269 5 PGND EN 6 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF
C264 C234 10uF 10uF VOSNS REFOUT C262 C237
10uF 100uF C235 0.1uF 4.7uF
4.7uF
11

TPS51200DRCR
Title
Zynq-7000 DDR
Size Document Number Rev
AX7010 开发板原理图 1.0

Date: Thursday, April 12, 2018 Sheet 8 of 16

5 4 3 2 1
 5 4 3 2 1

VCC3V3 VCC3V3 VCC1V8

REGOUT L7 R38 0R ADVDD10

Place near VDDREG 2.2uH
C164
22uF C169 C170 C171 C172
C165 C166 C167 C168 C173 C174 C175 C176 0.1uF 0.1uF 0.1uF 0.1uF
22uF 0.1uF 22uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

D D
DVDD10

VCC3V3 VCC1V8 C177 C178

ADVDD10
0.1uF 0.1uF

DVDD10
REGOUT
48
45
44

41

37
15
21

28
36

40
6

9
3
C179 18pF U10

Ethernet Port

REG_OUT

AVDD33_1
AVDD33_2
VDDREG1
VDDREG2

DVDD33_1
DVDD33_2
DVDD33_3

DVDD10_1
DVDD10_2

AVDD10_1
AVDD10_2
AVDD10_3
Y2 42
43 CKXTAL1
25Mhz CKXTAL2
34 PHY_AD0/LED0 R40 1 330R 2 R39
46 LED0/PHY_AD0 35 PHY_AD1/LED1 R41 1 330R 2 VCC3V3
CLK125 LED1/PHY_AD1 0R
C180 18pF 32 RXDLY
LED2/RXDLY

P10
1

1
4 ETH_TXCK 22 11 PHY_MDI3_N C181 C182
ETH_TXCK TXC MDI[3]-
4 ETH_TXCTL 27 10 PHY_MDI3_P J2
ETH_TXCTL TXCTL MDI[3]+ 0.1uF 0.1uF
ETH_TXD3 26 13
RTL8211E

CASE
4 ETH_TXD3

2
ETH_TXD2 25 TXD3 8 PHY_MDI2_N 14 LD2_K Yellow
4 ETH_TXD2 TXD2 MDI[2]- LD2_A
4 ETH_TXD1 24 7 PHY_MDI2_P 12
ETH_TXD1 TXD1 MDI[2]+ LD1_K Green
4 ETH_TXD0 23 EPAD to GND 11
ETH_TXD0 TXD0 LD1_A
C 5 PHY_MDI1_N C
ETH_RXCK 19 MDI[1]- 4 PHY_MDI1_P P9 8
4 ETH_RXCK RXCLK MDI[1]+ TRD3-
4 ETH_RXCTL 13
ETH_RXCTL ETH_RXD3 18 RXCTL/PHY_AD2 2 PHY_MDI0_N P8 7
4 ETH_RXD3 RXD3/AN1 MDI[0]- TRD3+
4 ETH_RXD2 17 1 PHY_MDI0_P
ETH_RXD2 ETH_RXD1 16 RXD2/AN0 MDI[0]+ P6 5
4 ETH_RXD1 RXD1/TXDLY TRD2-
4 ETH_RXD0 14
ETH_RXD0 RXD0/SELRGV 38 ENSWREG P5 4
ENSWREG 20 INTB TRD2+
ETH_MDC 30 INTB 33 PMEB P1
4 ETH_MDC MDC PMEB CT
4 ETH_MDIO 31 39 RSET
ETH_MDIO MDIO RSET
VCC1V8 R42 1.5K
EGND

PS_POR_B 29 12
GND

4 PS_POR_B PHYRSTB NC P7 6
R43 TRD1-
RTL8211E-VL 2.49K 1% P4 3
47

49

TRD1+
P3 2
TRD0-
P2 1
TRD0+

M5
M4

M2
M1
1

1
C183 C184 HR911130A

18
17

16
15
GE_RJ45
0.1uF 1uF

2
VCC3V3 VCC1V8 VCC3V3

B B

R44 R45 R47 R48 R49 R50

RGMII clock timing control 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
VCC3V3

RXDLY

ETH_RXD1
R51 R52 R53
4.7K 4.7K 0R

PHY_AD0/LED0

PHY_AD1/LED1 PMEB

ETH_RXCTL INTB

PHY Address is 001 ENSWREG

ETH_RXD0
Pull up for RGMII 1.8V
R54 R55 ETH_RXD2
4.7K 4.7K

ETH_RXD3

A Nway, Advertise all capabilities A

Title
Zynq-7000 Gigibit PHY
Size Document Number Rev
AX7010 开发板原理图 1.0

Date: Thursday, April 12, 2018 Sheet 9 of 16

5 4 3 2 1
 5 4 3 2 1

VCC3V3 VCC1V8

C185 C186 C187 C188 C189

D D
2.2uF 0.1uF 0.1uF 0.1uF 0.1uF

VCC1V8

R56
1.5K
J3
OTG_RESETN 4
USB2_5V 1
2 VCC
VCC1V8 VCC3V3 VCC1V8 C190 3 D-

SH2
SH1
10uF 4 D+
U11 GND

5
6
32 27 USB TYPEA
VDDIO RESETB USB_TYPEA
4 OTG_STP 29 21
OTG_STP STP VBAT
4 OTG_NXT 2 20 4.7uF C191
OTG_NXT NXT VDD33
4 OTG_DIR 31
OTG_DIR DIR 30
R57 33R 1 VDD18_1 28
4 OTG_CLK CLKOUT VDD18_2
OTG_DATA0 3 22 USB_VBUS J4
4 OTG_DATA0 DATA0 VBUS
C 4 OTG_DATA1 4 17 VUSB_V_EN C
OTG_DATA1 OTG_DATA2 5 DATA1 CPEN USB2_5V 1
4 OTG_DATA2 DATA2 VCC
4 OTG_DATA3 6 19 OTG_D_N 2
OTG_DATA3 OTG_DATA4 7 DATA3 DM 18 OTG_D_P 3 D-
4 OTG_DATA4 DATA4 DP D+
4 OTG_DATA5 9 4
OTG_DATA5 OTG_DATA6 10 DATA5 23 OTG_ID 5 ID
4

SH4
SH3
SH2
SH1
OTG_DATA6 OTG_DATA7 13 DATA6 ID GND
4 OTG_DATA7 DATA7 15 C214 18pF
SPL_L 16 MINI_USB

9
8
7
6
SPK_R
26
24 REFCLK 25 R88 Y4
RBIAS XO 1M 24Mhz
12 8
R58 NC REFSEL0 11
33 REFSEL1 14
8K06 GND REFSEL2 VCC1V8
C209 18pF

USB3320C USB2.0 OTG PORT

B B

USB_VBUS R60 1K USB2_5V

1
J6

1
J5
VCC3V3
VCC5V 2-Jumper
J28/J29 Connect: Host Mode

2
2
2-Jumper
R61 + C195 C196
J28/J29 Not Connect: Slave/OTG Mode
C193 U12 100K C194 100uF 4.7uF
0.1uF 22uF
5 1
VUSB_V_EN 4 IN OUT
2 EN 3
GND /OC
R62 TPS2051BDBV
10K

A A

Title
Zynq-7000 OTG USB
Size Document Number Rev
AX7010 开发板原理图 1.0

Date: Thursday, April 12, 2018 Sheet 10 of 16

5 4 3 2 1
 5 4 3 2 1

VCC3V3 VCC3V3

R63 R64
4.7K 4.7K C197
D D
0.1uF
U13
8 1
7 VCC A0 2
EEPROM_I2C_SCL 6 /WP A1 3
5 EEPROM_I2C_SCL SCL A2
5 EEPROM_I2C_SDA 5 4
EEPROM_I2C_SDA SDA GND
24LC04
R65
0R

EEPROM

VCC3V3
BT1
C C
VBAT_IN

C198
0.1uF
VCC3V3

U14

1
8
BATTERY
Y3 6

VCC1
VCC2
2 I/O
R66 R68 R67 3 X1
32.768Khz 7 X2
4.7K 4.7K 4.7K SCLK
5

GND
/RST

DS1302

4
5 RTC_I2C_SCL
RTC_I2C_SCL

5 RTC_RESET
RTC_RESET

5 RTC_I2C_SDA
RTC_I2C_SDA

B
RTC B

VCC3V3 VCC3V3

R69
470R
R0603 C199
0.1uF
C0402
U15
4 QSPI_CS 1 8
QSPI_CS QSPI_D1 2 /CS VCC 7 QSPI_D3
4 QSPI_D1 DO(IO1) /HOLD(IO3) QSPI_D3 4
4 QSPI_D2 3 6 QSPI_SCK 4
QSPI_D2 4 /WP(IO2) CLK 5 QSPI_D0 QSPI_SCK
TP

GND DI(IO0) QSPI_D0 4

W25Q256FVEI
9

QSPI FLASH
A A

Title
Zynq-7000 QSPI & RTC & EEPROM
Size Document Number Rev
AX7010 开发板原理图 1.0

Date: Thursday, April 12, 2018 Sheet 11 of 16

5 4 3 2 1
 5 4 3 2 1

VCC3V3

VCC3V3
R72
330R
LED2
POWER
D
VCC1V8 Power LED D
FPGA_DONE
FPGA_DONE 4
LED1
R71 DONE
R89 390R
FPGA DONE LED
10K

3
R70
16 PW_GOOD 1 Q8 200R
PW_GOOD
MMBT3904LT1G

3
PW_GOOD 1 Q9
MMBT3904LT1G

2
VCC1V8 VCC1V8

R73 R74
10k 10K

PS LED1 VCC3V3 PS LED2 VCC3V3

KEY2 KEY3
LED3 LED4
C C
4 R75 390R 4 R76 390R 4 1 2 4 1 2
MIO0_LED MIO13_LED MIO_KEY1 P1 P2 MIO_KEY2 P1 P2
RED RED
Button Button

VCCIO_35 VCCIO_35 VCCIO_35 VCCIO_35

LED5 LED6 LED7 LED8

5 R77 330R 5 R78 330R 5 R79 330R 5 R80 330R

LED1 LED2 LED3 LED4

RED RED RED RED

B B
VCCIO_35 VCCIO_35 VCC3V3 VCC3V3

R81 R82 R83 R84

10K 10K 10K 10K

KEY4 KEY5 KEY6 KEY7

5 1 2 5 1 2 5 1 2 5 1 2
KEY1 P1 P2 KEY2 P1 P2 KEY3 P1 P2 KEY4 P1 P2

Button Button Button Button

A A

Title
Zynq-7000 LED & KEY
Size Document Number Rev
AX7010 开发板原理图 1.0

Date: Thursday, April 12, 2018 Sheet 12 of 16

5 4 3 2 1
 5 4 3 2 1

USB Uart

R159
10K

18
19
20
21
22
U16
VCC3V3

NC7
NC8
NC9
NC10
NC11
D VCC1V8 D
6
9 VDD
RST

C239 C240 C201 C200

0.1uF 0.1uF 1uF 10uF
U27
23 3
3 7 24 CTS GND
5 VCCA VCCB 8 26 RTS
2 UART_RX 4 A1 B1 1 25 TXD
2 UART_TX 1K A2 B2 RXD VCC5V
VCC1V8 R160 6
OE GND
2

TXS0102DCU J7
R85 NC
28 8
12 DTR VBUS 7 R86 0R 1
11 SUSPEND REGIN 5 2 VCC
2 SUSPEND D- 4 3 D-
1 RI D+ 4 D+
27 DCD 5 ID

NC6
NC5
NC4
NC3
NC2
NC1

SH4
SH3
SH2
SH1
DSR GND

CP2102-GM MINI_USB

17
16
15
14
13
10

9
8
7
6
C C

VCC3V3
SD Card Connector
VCC1V8 VCC3V3 C203 C204
10uF 0.1uF

R92 R93
C205 C206 NC 4.7K
0.1uF U17 0.1uF
5 21
VCCA VCCB0 J8

4 6 18
SD_D0 7 DAT0A DAT0B0 16 1
4 SD_D1 DAT1A DAT1B0 DAT2
4 1 23 2
SD_D2 3 DAT2A DAT2B0 22 3 CD/DAT3
4 SD_D3 DAT3A DAT3B0 CMD
4 9 19 4
B SD_CLK 4 CLKA CLKB0 20 5 VDD B
4 SD_CMD CMDA CMDB0 CLK
6
24 17 7 VSS
VCC1V8 SEL VCCB1 14 8 DAT0
R94 2 DAT0B1 15 DAT1
GND1 DAT1B1

GND1
GND2
GND3
GND4
4.7K 11 8 9
R95 25 GND2 DAT2B1 10 CD
10K EPAD DAT3B1 13
CLKB1 12 Micro SD

10
11
12
13
CMDB1

TXS02612RTWR

4 R96 330R
SD_CD

A A

Title
Zynq-7000 UART & SD
Size Document Number Rev
AX7010 开发板原理图 1.0

Date: Thursday, April 12, 2018 Sheet 13 of 16

5 4 3 2 1
 5 4 3 2 1

VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 HDMI_5V

R97
27K
R98 R99 R100R101 R102R103 R104R105
49R949R9 49R949R9 49R949R9 49R949R9
D BAS16XV2T1G D
D1 J9
1
HDMI_D2_P 2 D2+ 20
5 HDMI_D2_P D2S S1
5 HDMI_D2_N 3 21
HDMI_D2_N 4 D2- S3
HDMI_D1_P 5 D1+ HDMI
5 HDMI_D1_P D1S
5 HDMI_D1_N 6
HDMI_D1_N 7 D1-
HDMI_D0_P 8 D0+
5 HDMI_D0_P D0S
5 HDMI_D0_N 9
HDMI_D0_N 10 D0-
HDMI_CLK_P 11 CLK+
5 HDMI_CLK_P CLKS
5 HDMI_CLK_N 12
HDMI_CLK_N HDMI_CEC 13 CLK-
VCC3V3 5 HDMI_CEC CEC
14
HDMI_SCL_LS 15 RES
HDMI_SDA_LS 16 SCL
U18 17 SDA 22
C207 6 1 18 DDC/CECG S2 23
0.1uF Y1 A1 19 5V0 S4
5 2 HPD
VCC GND

5 HDMI_HPD R106 1K 4 3 HDMI Connector (TYPEA) R108

HDMI_HPD Y2 A2 R107 0R
NC7WZ07P6X 100K

R109
100K U19 VCC3V3
C HDMI_OUT_EN 1 5 C
/OE VCC
2 C208
A 0.1uF
3 4 R110 1K
GND Y

NC7SZ125M5X

VCC5V
HDMI_5V

U28
F4
5 1
HDMI_OUT_EN 4 IN OUT
5 HDMI_OUT_EN EN
2 3 R161 1K VCC3V3 PTS120630V012
GND /OC C242
TPS2051BDBV 10uF
R162 C241
NC 0.1uF

B B

VCC3V3 VCC3V3
HDMI_5V HDMI_5V

R114
R112 R113 C210 200K
1K 1K 0.1uF

R115 R116
U21 1.5K 1.5K

1 8 C211
2 GND GREF 7 0.1uF
HDMI_SCL 3 SREF DREF 6 HDMI_SCL_LS
5 HDMI_SCL S1 D1
5 HDMI_SDA 4 5 HDMI_SDA_LS
HDMI_SDA S2 D2

GTL2002D

A A

Title
Zynq-7000 HDMI
Size Document Number Rev
AX7010 开发板原理图 1.0

Date: Thursday, April 12, 2018 Sheet 14 of 16

5 4 3 2 1
 5 4 3 2 1

RN1
5 1 8 EX_IO1_2N
IO1_2N
5 2 7 EX_IO1_2P
IO1_2P
5 3 6 EX_IO1_1N
IO1_1N
5 IO1_1P 4 5 EX_IO1_1P
33R
RN2
5 1 8 EX_IO1_4N
IO1_4N
5 2 7 EX_IO1_4P
IO1_4P
5 3 6 EX_IO1_3N
IO1_3N
5 IO1_3P 4 5 EX_IO1_3P
33R

FPGA 40 PIN External IO

RN3
5 1 8 EX_IO1_6N
D IO1_6N D
5 2 7 EX_IO1_6P
IO1_6P
5 3 6 EX_IO1_5N
IO1_5N
5 IO1_5P 4 5 EX_IO1_5P J10
33R
RN4 1 2 VCC5V
5 1 8 EX_IO1_8N EX_IO1_1N 3 4 EX_IO1_1P
IO1_8N
5 2 7 EX_IO1_8P EX_IO1_2N 5 6 EX_IO1_2P
IO1_8P
5 3 6 EX_IO1_7N EX_IO1_3N 7 8 EX_IO1_3P
IO1_7N
5 IO1_7P 4 5 EX_IO1_7P EX_IO1_4N 9 10 EX_IO1_4P
33R EX_IO1_5N 11 12 EX_IO1_5P
RN5 EX_IO1_6N 13 14 EX_IO1_6P VCC5V VCC3V3
5 1 8 EX_IO1_10N EX_IO1_7N clk 15 16 clk EX_IO1_7P
IO1_10N
5 2 7 EX_IO1_10P EX_IO1_8N 17 18 EX_IO1_8P
IO1_10P
5 3 6 EX_IO1_9N EX_IO1_9N 19 20 EX_IO1_9P C212 C213
IO1_9N
5 IO1_9P 4 5 EX_IO1_9P EX_IO1_10N 21 22 EX_IO1_10P 0.1uF 0.1uF
33R EX_IO1_11N 23 24 EX_IO1_11P
RN6 EX_IO1_12N 25 26 EX_IO1_12P
5 1 8 EX_IO1_12N EX_IO1_13N 27 28 EX_IO1_13P
IO1_12N
5 2 7 EX_IO1_12P EX_IO1_14N 29 30 EX_IO1_14P
IO1_12P
5 3 6 EX_IO1_11N EX_IO1_15N 31 32 EX_IO1_15P
IO1_11N
5 IO1_11P 4 5 EX_IO1_11P EX_IO1_16N 33 34 EX_IO1_16P
33R EX_IO1_17N 35 36 EX_IO1_17P
RN7 37 38
5 1 8 EX_IO1_14N VCC3V3 39 40 VCC3V3
IO1_14N
5 2 7 EX_IO1_14P
IO1_14P
5 3 6 EX_IO1_13N
IO1_13N
5 IO1_13P 4 5 EX_IO1_13P HEADER 20x2/M
33R
RN8
C 5 1 8 EX_IO1_16N C
IO1_16N
5 2 7 EX_IO1_16P
IO1_16P
5 3 6 EX_IO1_15N J11
IO1_15N
5 4 5 EX_IO1_15P
IO1_15P
33R 1 2 VCC5V
RN9 EX_IO2_1N 3 4 EX_IO2_1P
5 1 8 EX_IO1_17N EX_IO2_2N 5 6 EX_IO2_2P
IO1_17N
5 2 7 EX_IO1_17P EX_IO2_3N 7 8 EX_IO2_3P
IO1_17P
3 6 EX_IO2_4N 9 10 EX_IO2_4P
4 5 EX_IO2_5N 11 12 EX_IO2_5P
33R EX_IO2_6N 13 14 EX_IO2_6P
EX_IO2_7N clk 15 16 clk EX_IO2_7P
EX_IO2_8N 17 18 EX_IO2_8P
EX_IO2_9N 19 20 EX_IO2_9P
EX_IO2_10N 21 22 EX_IO2_10P
EX_IO2_11N 23 24 EX_IO2_11P
RN10 EX_IO2_12N 25 26 EX_IO2_12P
5 1 8 EX_IO2_2N EX_IO2_13N 27 28 EX_IO2_13P
IO2_2N
5 2 7 EX_IO2_2P EX_IO2_14N 29 30 EX_IO2_14P
IO2_2P
5 3 6 EX_IO2_1N EX_IO2_15N 31 32 EX_IO2_15P
IO2_1N
5 IO2_1P 4 5 EX_IO2_1P EX_IO2_16N 33 34 EX_IO2_16P
33R EX_IO2_17N 35 36 EX_IO2_17P
RN11 37 38
5 1 8 EX_IO2_4N VCC3V3 39 40 VCC3V3
IO2_4N
5 2 7 EX_IO2_4P
IO2_4P
5 3 6 EX_IO2_3N
IO2_3N
5 IO2_3P 4 5 EX_IO2_3P HEADER 20x2/M
33R
RN12
5 1 8 EX_IO2_6N
B IO2_6N B
5 2 7 EX_IO2_6P
IO2_6P
5 3 6 EX_IO2_5N
IO2_5N
5 IO2_5P 4 5 EX_IO2_5P
33R
RN13 RN14 J12
5 1 8 EX_IO2_8N 4 1 8 PMOD_IO6
IO2_8N PS_MIO8
5 2 7 EX_IO2_8P 4 2 7 PMOD_IO2 PMOD_IO0 1 7 PMOD_IO1
IO2_8P PS_MIO9
5 3 6 EX_IO2_7N 4 3 6 PMOD_IO1 PMOD_IO2 2 8 PMOD_IO6
IO2_7N PS_MIO10
5 IO2_7P 4 5 EX_IO2_7P 4 4 5 PMOD_IO0 PMOD_IO3 3 9 PMOD_IO7
33R PS_MIO11 33R PMOD_IO4 4 10 PMOD_IO5
RN15 5 11
5 1 8 EX_IO2_10N VCC3V3 6 12 VCC3V3
IO2_10N
5 2 7 EX_IO2_10P
IO2_10P
5 3 6 EX_IO2_9N RN16
IO2_9N
5 IO2_9P 4 5 EX_IO2_9P 4 1 8 PMOD_IO5 PMOD
33R PS_MIO12 2 7 PMOD_IO4
4 PS_MIO7
RN17 4 3 6 PMOD_IO7
1 8 EX_IO2_12N PS_MIO14 4 5 PMOD_IO3
5 IO2_12N 4 PS_MIO15
5 2 7 EX_IO2_12P 33R
IO2_12P
5 3 6 EX_IO2_11N
IO2_11N
5 IO2_11P 4 5 EX_IO2_11P
33R
RN18

MIO Connector
5 1 8 EX_IO2_14N
IO2_14N
5 2 7 EX_IO2_14P
IO2_14P
5 3 6 EX_IO2_13N
IO2_13N
5 IO2_13P 4 5 EX_IO2_13P
33R

A RN19 A
5 1 8 EX_IO2_16N
IO2_16N
5 2 7 EX_IO2_16P
IO2_16P
5 3 6 EX_IO2_15N
IO2_15N
5 IO2_15P 4 5 EX_IO2_15P
33R
RN20
1 8
2 7 Title
5 IO2_17N
3 6 EX_IO2_17N Zynq-7000 LED & KEY & IO
5 IO2_17P 4 5 EX_IO2_17P
33R Size Document Number Rev
AX7010 开发板原理图 1.0

Date: Thursday, April 12, 2018 Sheet 15 of 16

5 4 3 2 1
 5 4 3 2 1

VCC5V

VCC3V3 VCC1V8 VCC1V5 VCC1V0

J25 J18 J17 J16
F3 2A
1 1 1 1
2 2 2 2
5V/2A AC Adapter
CN1 SW6 CON2 CON2 CON2 CON2
3 D3
D D
2
1 SMAJ5.0CA

AJ243-3-3C
CN1_DCJACK
SW

VCC5V 1.0V POWER VCC1V0 VCC5V 1.8V POWER VCC1V8

U23 U24
L10 2.2uH 5000mA L11 2.2uH 5000mA
10 1 10 1
11 AVIN1 SW1 2 11 AVIN1 SW1 2
12 PVIN2 SW2 3 12 PVIN2 SW2 3
PVIN3 SW3 PVIN3 SW3
14 14
13 VOS 1V0_PG 13 VOS
EN 4 1V0_PG R123 10K R124 EN 4 1V8_PG R125 10K R126
9 PG 9 PG C218 C220
SS/TR 4.99K SS/TR 18.7K
C222 7 R0603 C219 C223 C225 7 22uF 0.1uF
C221 3.3nF FSW 22uF 0.1uF C224 3.3nF FSW
PGND1
PGND2
AGND3

PGND1
PGND2
AGND3
C C
TPAD

TPAD
10uF 8 5 10uF 8 5
DEF FB DEF FB

TLV62130RGT R127 TLV62130RGT R128

20
16
15
6

20
16
15
6
20K 1% 15K 1%

VCC5V 1.5V POWER VCC1V5 VCC5V 3.3V POWER VCC3V3

U25 U26
L12 2.2uH 5000mA L13 2.2uH 5000mA
10 1 10 1
11 AVIN1 SW1 2 11 AVIN1 SW1 2
12 PVIN2 SW2 3 12 PVIN2 SW2 3
PVIN3 SW3 PVIN3 SW3
14 14
1V8_PG 13 VOS 1V5_PG 13 VOS
EN 4 1V5_PG R129 10K R130 EN 4 PW_GOOD R132
PG PG PW_GOOD 12
9 13K 1% C226 C227 9 56.2K C228 C229
B
C231 SS/TR 7 22uF 0.1uF C233 SS/TR 7 22uF 0.1uF B

C230 3.3nF FSW C232 3.3nF FSW

PGND1
PGND2
AGND3

PGND1
PGND2
AGND3
TPAD

TPAD
10uF 8 5 10uF 8 5
DEF FB DEF FB

TLV62130RGT R133 TLV62130RGT R134

20
16
15
6

20
16
15
6
15K 1% 18K 1%

VCC5V VCC3V3 VCCIO_35

U20
Power On Sequnce: 1
VIN VOUT
5

4
1.0V -> 1.8V -> 1.5 V -> 3.3V -> VCCIO C192 ADJ
0.1uF 3 C216 C215
EN 10uF 0.1uF
2
GND
A A
SPX3819M5-3-3

Title
Power
Size Document Number Rev
AX7010 开发板原理图 1.0

Date: Thursday, April 12, 2018 Sheet 16 of 16

5 4 3 2 1