0% found this document useful (0 votes)
3 views6 pages

VLSI Lab

The document is a lab file from the VLSI Lab at Devi Ahilya University, authored by Devyanshi Mahant. It includes two experiments: one studying the I-V characteristics of NMOS transistors and another examining the characteristics of an inverter, both utilizing the Tanner EDA Tool for simulations. Each experiment outlines objectives, requisites, schematic details, and simulation settings.

Uploaded by

nehabhagwani0804
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
3 views6 pages

VLSI Lab

The document is a lab file from the VLSI Lab at Devi Ahilya University, authored by Devyanshi Mahant. It includes two experiments: one studying the I-V characteristics of NMOS transistors and another examining the characteristics of an inverter, both utilizing the Tanner EDA Tool for simulations. Each experiment outlines objectives, requisites, schematic details, and simulation settings.

Uploaded by

nehabhagwani0804
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

SCHOOL OF ELECTRONICS

DEVI AHILYA UNIVERSITY

VLSI LAB FILE

Name – Devyanshi Mahant


Roll No. - 22IMTEL02

1
Table of Content

S No. Name of experiment Date Remark


1. To study I-V Characteristics of
NMOS
2. To study characteristics of
Inverter

2
Experiment 1
1. Objective: To study the Characteristics of NMOS Transistor
2. Requisite: Tanner EDA Tool
3. Schematic:

4. T- Spice:
SPICE export by: S-Edit 15.00
Export time: Thu Apr 16 [Link] 2026
Design: NMOS1
Cell: Cell0
View: view0
Export as: top-level cell
Export mode: hierarchical
Exclude empty cells: yes
Exclude .model: no
Exclude .end: no
Exclude simulator commands: no
Expand paths: yes
Wrap lines: no

3
Root path: C:\Users\student\Desktop\Devyanshi\NMOS1
Exclude global pins: no
Control property name: SPICE

********* Simulation Settings - General Section ********* .lib "C:\Users\student\Documents\


Tanner EDA\Tanner Tools v15.0\Process\Generic_250nm\Generic_250nm_Tech\
Generic_250nm.lib"TT .param Vdd = 2.5 .param Vgs = 1

*-------- Devices With [Link] > 0.0 -------- ***** Top Level ***** MNMOS_1 N_1
N_2 Gnd Gnd NMOS25 W=4u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=4700
$y=2600 $w=400 $h=600 VVdd N_1 Gnd DC Vdd $ $x=5000 $y=3900 $w=400 $h=600
$r=180 VVgs N_2 Gnd DC Vgs $ $x=3300 $y=2600 $w=600 $h=400 $r=90 .PRINT DC
ID(MNMOS_1) .dc lin Vdd 0 2.5 0.1 lin Vgs 1 1.5 0.5 ********* Simulation Settings -
Analysis Section *********

********* Simulation Settings - Additional SPICE Commands *********

.end

5. Output:

Experiment 2
1. Objective: To study the characteristics of Inverter.
4
2. Requisite: Tanner EDA Tool
3. Schematic:

4. T- Spice:
SPICE export by: S-Edit 15.00
Export time: Thu Apr 16 [Link] 2026
Design: inverter
Cell: Cell0
View: view0
Export as: top-level cell
Export mode: hierarchical
Exclude empty cells: yes
Exclude .model: no
Exclude .end: no
Exclude simulator commands: no
Expand paths: yes
Wrap lines: no
Root path: C:\Users\student\Desktop\Devyanshi\inverter
Exclude global pins: no
Control property name: SPICE

5
********* Simulation Settings - General Section ********* .lib "C:\Users\student\Documents\
Tanner EDA\Tanner Tools v15.0\Process\Generic_250nm\Generic_250nm_Tech\
Generic_250nm.lib"TT

*-------- Devices With [Link] > 0.0 -------- ***** Top Level ***** MNMOS_1
Out_NOT A Gnd Gnd NMOS25 W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $
$x=3800 $y=1600 $w=400 $h=600 MPMOS_1 Out_NOT A Vdd Vdd PMOS25 W=2.5u
L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=3700 $y=5000 $w=400 $h=600

********* Simulation Settings - Analysis Section ********* v1 Vdd Gnd DC 5 vin A Gnd
pulse(0 5 0 1n 1n 20n 40n) .print tran v(A) v(Out_NOT) .tran 0.05n 80n start=0

********* Simulation Settings - Additional SPICE Commands *********

.end

5. Output:

You might also like