MODULE / SUBJECT TITLE: Introduction to Operating System

MODULE / SUBJECT CODE: ITOS101

SAQA CREDITS: 12
NQF LEVEL: 5
LECTURER: Prof. Emmanuel Adetiba

Topic 2: The Central Processing Unit (CPU) – Part 1

©2026 Department of Information Systems, Faculty of Accounting and Informatics, Durban University of
Technology
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Topic 2 Learning Objectives
By the end of this topic, you should be able to:
I. Function and features of CPUs
II. Characteristics of CPU
III. Identify features of modern CPUs

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1.0 CPU Fundamentals (1 of 4)
• The features of an OS used for a particular application
depend on the capabilities of the hardware.
✓ In many cases, modern operating systems do not support older
hardware.
✓ When you upgrade an operating system, you may need to upgrade
the hardware to match the new operating system’s capabilities.

• This module focuses on the CPU and its surrounding

electronics as hereafter presented.
1.0 CPU Fundamentals Cont’d (2 of 4)
• Central Processing Unit(CPU): This is the chip that performs the actual computational and logic work in
a computer system. It requires several support chips, such as chips that help manage communications with
devices and device drivers.
• System architecture: This includes the number and type
of CPUs in the hardware as well as the communication routes between the CPUs and other hardware
components (such as memory and disk storage).
• Bus: This is a path or channel between a computer’s CPU and the devices it manages, such as memory and
I/O devices.
• Single-processor computers: These are client computers with one CPU chip.
• Multiprocessor computers: These are servers and high-end client computers that have multiple
physical CPUs ranging from two to 128 or more
• Processor core: This is the part of a CPU that reads and executes machine code, such as reading and writing data
from and to memory or executing an arithmetic operation.
✓ A multicore processor has two or more cores.
✓ Dual-core processor contains two cores.
✓ Quad-core processor has four cores.
✓ Intel’s Xeon Phi processor has 72 cores.
• CPUs are manufactured on a silicon wafer, and the result is called a die.
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1.0 CPU Fundamentals Cont’d (3 of 4)

Figure 1.0: Inside of an Intel Core i7 Processor with

Six Cores

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1.1 CPU Startup Operation (4 of 4)
• When power is applied to the CPU, it begins reading data from a
memory address called the reset vector.
• The reset vector is sometimes called the boot vector. It is
preprogrammed into the CPU chip, and on some processors it can
be changed.
✓ Reset vector points to a location in non-volatile memory(ROM or flash memory), which
contains the bootloader code.
✓ The Intel 8086 processor’s reset vector is at hexadecimal FFFF0.
✓ ARM processors and Atmel processors point to address 0.
• On many processors, the data found at the address of the reset
vector is loaded into the CPU’s program counter.
• Program counter is used as the address where the CPU will begin
program execution, and could also contain the address of the next
instruction the CPU will execute.

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2.0 CPU Design (1 of )

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2.1 CPU Components (2 of )
• While modern CPUs are much more complex than the simple block diagram in the
previous slide, most CPUs follow this basic design and contain the following
elements:
i) Control unit – This provides timing and coordination between other parts of the
CPU.
✓ For example, when a new instruction should be executed, the control unit receives and decodes
the instruction and tells the arithmetic logic unit to execute it.

ii) Arithmetic Logic Unit (ALU) - ALU performs the primary task of executing
instructions. These might be:
✓ Arithmetic instructions - such as addition or multiplication of integers,
✓ Logic instructions - such as binary AND or binary OR instructions, and
✓ Most CPUs also contain a Floating-Point Unit (FPU) that performs floating-point operations.

iii) Registers – This is a temporary holding location where data must be placed
before the CPU can use it. There are:
✓ Instruction registers - that hold the instruction the CPU executes,
✓ Address registers - to access data stored in RAM,
✓ Data registers - that hold the data the CPU is currently working with.
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2.1 CPU Component cont’d (3 of )
iv) Memory/Cache Controller – the cache controller
intercepts accesses to memory for data or code and checks if
the requested data is in cache first.
✓ If the requested data is in cache, the request is fulfilled; otherwise, the request is
passed on to the memory controller to access main memory.
✓ Data accessed in main memory is usually then placed in cache, so subsequent
accesses to the data are pulled from cache.
v) System Bus – A series of lanes used to communicate
between the CPU and other major parts of the computer(e.g
RAM, I/O Devices).
• There are three types of buses:
✓ Control bus – carries status signals between the CPU and other devices. Interrupt
signals inform the CPU that a device needs attention.
✓ Address bus – carries address signals to indicate where data should be read or
written to in the system’s memory.
✓ Data bus – carries the actual data that is being read from or written to system
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2.2 CPU Classification (3 of )
• CPUs can be classified by several hardware elements, the most
important of which are:
✓Architecture
✓Clock speed
✓Cache
✓System bus(address, data and control buses)
✓CPU scheduling

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2.2 CPU Classification - Architecture (3 of )
• Two general CPU designs are used today:
✓Complex Instruction Set Computing (CISC)
✓Reduced Instruction Set Computing (RISC)
• The main difference between the two design types is the different
machine code instructions the chip supports and the complexity of
the instructions. Note the following
✓ A program consists of machine code instructions and data.
✓ An instruction is usually a very simple operation, such as load a byte of data into a register.
✓ When a program is loaded into memory on the computer and scheduled to run, the CPU reads
each instruction and executes the task specified by that instruction.
✓ The instruction set is the list of machine code commands that the CPU supports.
✓ CPUs can process as many as several billion operations per second, depending on the CPU
architecture and the clock speed.

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2.2 CPU Classification – Architecture cont’d (3 of )
• CISC and RISC CPUs differ in the following ways:
i) Complex versus simple instructions
✓ CISC CPUs are generally more complex, meaning each instruction does more work than a single
RISC instruction.

ii) Clock cycles

✓ Some instructions on CISC CPUs might require one clock cycle; others might need two, four, or
more clock cycles.
✓ Conversely, most instructions on RISC CPUs take only one clock cycle. Because the instructions
on RISC CPUs take a uniform number of clock cycles, designers can use this fact to their
advantage with pipelining.

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2.2 CPU Classification – Architecture cont’d (3 of )
iii) Pipelining
✓ This is the ability of the CPU to perform more than one task on a single clock cycle.
✓ While pipelining does occur in CISC CPUs, the varying number of cycles it takes to complete
each instruction makes pipelining more difficult and not as effective, compared to RISC CPUs.

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2.2 CPU Classification – Architecture cont’d (3 of )
iii) Hardware versus microcode
✓ Because CISC instructions are so complex, a small program inside the chip must interpret and
execute each instruction. This small program is called microcode.
✓ RISC instructions are all executed directly by the CPU hardware, with no microcode middleman,
which makes for faster execution of individual instructions.

iv) Compiler
✓ A compiler is a computer program that takes a high-level language like C++ or Java and turns it into
assembly code, which is the human-readable form of machine code that is executed by the CPU.
✓ An assembler turns those instructions into numeric values, called opcodes, that the CPU can
understand.
✓ Due to the complexity of CISC-based instructions, the compiler has less work to do because the
high-level language code need not be broken down into many assembly language steps.
✓ Conversely, for RISC, the compiler breaks the high-level language code into several assembly
language steps.

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2.2 CPU Classification – Architecture cont’d (3 of )

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From high-level language to machine code 15
2.2 CPU Classification – Architecture cont’d (3 of )
v) Number and usage of registers
✓ Because so much room is used for microcode on CISC CPUs, there are far fewer registers than
on a RISC chip, which doesn’t use microcode.
✓ The more registers there are, the more simultaneous operations the CPU can perform (as seen
with pipelining).
✓ CISC CPUs erase their registers after each instruction, requiring them to be reloaded with each
successive instruction,
✓ Whereas RISC CPUs can leave data in registers until the registers are needed for another
operation.
✓ Many CPUs today have a combination of CISC and RISC features, but CPUs are usually
described by their predominant architecture.
✓ Intel processors are still considered to be CISC, but they contain features of traditional RISC
CPUs.

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Knowledge Check #1
1) Which component of a computer carries data 4) If you are developing a bootloader for a CPU, what do
between the CPU and memory? you need to know about the CPU to ensure that your
bootloader code will be executed when the CPU is
A) Vector powered on?
B) Register A) Reset vector address
C) Bus B) Number of registers
D) Core C) Location of the program counter
2) The ability of the CPU to perform more than one D) Internal clock speed
task on a single clock cycle is known as?
5) Which of the following is true about CISC CPUs?
A) Multiprocessor
A) They have a simple instruction set.
B) Multithreading
B) They require a more complex compiler.
C) Caching
C) They use microcode.
D) Pipelining
D) Pipelining is easy.
3) Which part of a CPU carries signals to indicate
where data should be read from or written to in the 6) Which of the following is used to keep the CPU
system’s memory? informed of the status of resources and devices
connected to the computer?
A) Register
A) Control bus
B) Data bus
B) ALU
C) Control unit
C) Microcode
D) Address bus
D) Pipeline
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