DIGITAL ELECTRONICS

& DEVICES
Complete Finals Study Guide

Covers: Number Systems • Boolean Algebra • Logic Gates

Combinational Circuits • Sequential Circuits • Flip-Flops
Registers • Counters • Memory • ADC/DAC • Microprocessors

Finals Prep Edition • Good luck — you've got this! 🎯

 1. NUMBER SYSTEMS & CODES

1.1 Positional Number Systems

Digital electronics uses four main number systems. Understanding conversion between them is
essential.

Term Definition
Binary (Base-2) Uses digits 0 and 1. Each position is a power of 2. Used internally
by all digital circuits.
Octal (Base-8) Uses digits 0–7. Each octal digit = 3 binary bits. Useful shorthand
for binary.
Decimal (Base-10) The everyday number system. Uses digits 0–9.
Hexadecimal (Base-16) Uses digits 0–9 and A–F. Each hex digit = 4 binary bits (a nibble).
Common in memory addressing.

Conversion Quick Reference

Binary → Decimal: Multiply each bit by its positional power of 2 and sum.
💡 Example
1011 in binary = 1x8 + 0x4 + 1x2 + 1x1 = 8+0+2+1 = 11 in decimal

Decimal → Binary: Repeatedly divide by 2, collect remainders bottom-up.

💡 Example
13 ÷ 2 = 6 R 1 | 6 ÷ 2 = 3 R 0 | 3 ÷ 2 = 1 R 1 | 1 ÷ 2 = 0 R 1 → Read remainders upward: 1101₂

Hex ↔ Binary: Replace each hex digit with its 4-bit binary equivalent (or group binary into nibbles).
💡 Example
A3₁₆ = 1010 0011₂ | 11001010₂ = C A₁₆ = CA₁₆

1.2 Binary Arithmetic

Addition Rules
• 0+0=0
• 0+1=1
• 1+0=1
• 1 + 1 = 10 (sum=0, carry=1)
• 1 + 1 + 1 = 11 (sum=1, carry=1)
Subtraction via 2's Complement
• Invert all bits (flip 0→1 and 1→0): 1's Complement
• Add 1 to the 1's complement result: 2's Complement
• Subtraction A − B = A + (2's complement of B); discard final carry if it overflows
💡 Why 2's Complement?
It lets subtraction be performed using only adder circuits — a single hardware design handles
both add and subtract. Nearly all modern processors use 2's complement for signed integers.

1.3 Binary Codes

Term Definition
BCD (8421) Binary Coded Decimal — each decimal digit 0–9 is stored as its 4-
bit binary value. Used in calculators, displays.
Gray Code Only ONE bit changes between consecutive values. Prevents errors
in encoders and analog-to-digital conversion.
ASCII 7-bit code (128 characters) mapping letters, digits, and symbols.
Foundation of text in computers.
Excess-3 Code BCD + 3 (0011). Self-complementing: 9's complement found by
inverting bits.
Hamming Code Error-detecting/correcting code. Parity bits inserted at power-of-2
positions to detect single-bit errors.
 2. BOOLEAN ALGEBRA

2.1 Basic Postulates & Theorems

Boolean algebra is the mathematical foundation of digital logic. All operations reduce to 0 and 1.

Identity, Null, Idempotent, Complement Laws

Law AND form OR form
Identity A · 1 = A A + 0 = A
Null A · 0 = 0 A + 1 = 1
Idempotent A · A = A A + A = A
Complement A · A' = 0 A + A' = 1
Double Negation A'' = A —
Commutative A · B = B · A A + B = B + A
Associative (A·B)·C = A·(B·C) (A+B)+C = A+(B+C)
Distributive A·(B+C) = AB+AC A+(B·C) = (A+B)·(A+C)
Absorption A·(A+B) = A A + AB = A
De Morgan's 1st (AB)' = A' + B' —
De Morgan's 2nd (A+B)' = A'·B' —

2.2 De Morgan's Theorem (Critical for Exams!)

💡 De Morgan's Laws — Memorize These!
1st Law: The complement of a PRODUCT equals the sum of complements: (A·B)' = A' + B' 2nd
Law: The complement of a SUM equals the product of complements: (A+B)' = A'·B' Application:
NAND = Negative-OR | NOR = Negative-AND

2.3 Simplification using Karnaugh Maps (K-Maps)

K-maps are a visual method for minimizing Boolean expressions by grouping adjacent 1s.
• Groups must contain 1, 2, 4, 8, or 16 cells (powers of 2)
• Groups must be rectangular (can wrap around edges)
• Use the largest possible groups — fewer terms in final expression
• Each 1 must be covered by at least one group
• Look for groups that eliminate variables (a variable is eliminated if it appears both as 0 and 1 in
the group)
💡 K-Map Steps
1. Fill in the truth table values into the K-map cells 2. Identify and circle the largest possible
groups of 1s 3. For each group, identify which variables remain CONSTANT — those form the
term 4. Write the simplified SOP (Sum of Products) expression 5. Verify: check that all 1s are
covered
 3. LOGIC GATES

3.1 Basic Gates

Logic gates are the physical building blocks of all digital circuits. They perform Boolean operations on
binary inputs.

AND Gate
Output is HIGH (1) only when ALL inputs are HIGH. Expression: Y = A · B
AND Gate Truth Table
A B Y = A·B
0 0 0
0 1 0
1 0 0
1 1 1

OR Gate
Output is HIGH when AT LEAST ONE input is HIGH. Expression: Y = A + B
OR Gate Truth Table
A B Y = A+B
0 0 0
0 1 1
1 0 1
1 1 1

NOT Gate (Inverter)

Single input. Output is the complement of the input. Expression: Y = A'
NOT Gate Truth Table
A Y = A'
0 1
1 0

NAND Gate (NOT-AND) ★ Universal Gate

Output is LOW only when ALL inputs are HIGH. Expression: Y = (A·B)'
NAND Gate Truth Table
 A B Y = (A·B)'
0 0 1
0 1 1
1 0 1
1 1 0

NOR Gate (NOT-OR) ★ Universal Gate

Output is HIGH only when ALL inputs are LOW. Expression: Y = (A+B)'
NOR Gate Truth Table
A B Y = (A+B)'
0 0 1
0 1 0
1 0 0
1 1 0

XOR Gate (Exclusive-OR)

Output is HIGH when inputs are DIFFERENT. Expression: Y = A ⊕ B = AB' + A'B
XOR Gate Truth Table
A B Y = A⊕B
0 0 0
0 1 1
1 0 1
1 1 0

XNOR Gate (Exclusive-NOR)

Output is HIGH when inputs are the SAME. Expression: Y = (A⊕B)' = AB + A'B'
XNOR Gate Truth Table
A B Y = (A⊕B)'
0 0 1
0 1 0
1 0 0
1 1 1

💡 Universal Gates — Critical Concept!

NAND and NOR gates are called UNIVERSAL because any other gate can be built using only
NANDs or only NORs: • NOT from NAND: Connect both inputs together → Y = (A·A)' = A' • AND
from NAND: NAND followed by NOT • OR from NAND: Invert both inputs, then NAND them (De
Morgan's) Same logic applies for NOR as universal gate.
 4. COMBINATIONAL CIRCUITS

In combinational circuits, the output depends ONLY on the current inputs — there is no memory or
feedback.

4.1 Half Adder

Adds two 1-bit inputs A and B. Produces a Sum and a Carry-out. Cannot handle a carry-in.
• Sum = A ⊕ B (XOR gate)
• Carry = A · B (AND gate)
Half Adder
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

4.2 Full Adder

Adds three 1-bit inputs: A, B, and Carry-in (Cin). Used in multi-bit adder chains.
• Sum = A ⊕ B ⊕ Cin
• Carry-out = AB + Cin(A⊕B) = AB + BCin + ACin
💡 Key Point
A ripple carry adder chains N full adders to add N-bit numbers. The carry propagates from LSB to
MSB, causing delay. A carry look-ahead adder is faster but uses more hardware.

4.3 Multiplexer (MUX)

A MUX selects ONE of several input data lines and routes it to a single output, controlled by SELECT
lines.
• A 2ⁿ:1 MUX has n select lines and 2ⁿ data inputs
• Example: 4:1 MUX has 2 select lines (S1, S0) and inputs I0–I3
• Output Y = S1'S0'·I0 + S1'S0·I1 + S1S0'·I2 + S1S0·I3
• Application: data routing, function implementation, bus systems

4.4 Demultiplexer (DEMUX)

Routes ONE input to one of several outputs, selected by control lines. Reverse of MUX.
• A 1:2ⁿ DEMUX has n select lines and 2ⁿ outputs
• Only the SELECTED output carries the input signal; others are 0
4.5 Encoder & Decoder
Term Definition
Encoder Converts 2ⁿ input lines into n-bit binary code. Active input → binary
code output. Example: 8-to-3 priority encoder.
Decoder Converts n-bit binary input into 2ⁿ output lines. Activates exactly
one output. Example: 3-to-8 decoder, BCD to 7-segment.
Priority Encoder When multiple inputs are active, the highest-priority input is
encoded. Includes a valid output (V) indicating any input is active.
7-Segment Decoder Converts BCD (4 bits) into 7 outputs (a–g) to drive a 7-segment
LED display.

4.6 Comparator
Compares two binary numbers A and B and outputs three conditions: A > B, A = B, A < B.
• 1-bit comparator built with XNOR (equality), AND/NOT for greater/less
• Multi-bit: compare MSBs first; if equal, compare next bits
• IC 7485 is a popular 4-bit magnitude comparator that can be cascaded
 5. SEQUENTIAL CIRCUITS & FLIP-FLOPS

Sequential circuits have MEMORY — outputs depend on current inputs AND previous state. They
require a clock signal.

💡 Combinational vs Sequential
Combinational: Output = f(current inputs only). No memory. Examples: adder, MUX, decoder.
Sequential: Output = f(current inputs + previous state). Has memory. Examples: flip-flops,
registers, counters.

5.1 SR Latch (Set-Reset)

The most basic memory element. Built from cross-coupled NOR or NAND gates.
SR Latch (NOR-based)
S R Q (next) Action
0 0 Q (no change) Hold
0 1 0 Reset
1 0 1 Set
1 1 Invalid FORBIDDEN

💡 Warning!
S=1, R=1 is the FORBIDDEN state — both outputs try to be active simultaneously, creating an
undefined/unpredictable next state.

5.2 D Flip-Flop (Data / Delay)

Stores one bit. Output Q follows input D at the clock edge. Eliminates the forbidden state of SR.
• D = 0 → Q = 0 after clock edge
• D = 1 → Q = 1 after clock edge
• Characteristic equation: Q(next) = D
• Applications: data registers, shift registers, pipeline stages
D Flip-Flop
D Q(next)
0 0
1 1

5.3 JK Flip-Flop
The most versatile flip-flop. Eliminates the forbidden state by making J=1, K=1 a TOGGLE condition.
JK Flip-Flop
 J K Q(next) Action
0 0 Q Hold
0 1 0 Reset
1 0 1 Set
1 1 Q' Toggle
• Characteristic equation: Q(next) = JQ' + K'Q
• Application: counters (toggle mode), frequency dividers

5.4 T Flip-Flop (Toggle)

Special case of JK with J=K=T. When T=1, output toggles on every clock edge.
T Flip-Flop
T Q(next) Action
0 Q Hold
1 Q' Toggle
• Characteristic equation: Q(next) = T⊕Q
• Application: binary counters (divide-by-2 circuit)

5.5 Master-Slave Flip-Flop

Two flip-flops cascaded: master captures input on leading edge, slave transfers to output on trailing
edge. Prevents race conditions.
• Eliminates timing issues present in level-triggered latches
• Edge-triggered behaviour makes timing analysis predictable

5.6 Flip-Flop Timing Parameters

Term Definition
Setup Time (tsu) Minimum time input D must be stable BEFORE the clock edge for
reliable capture.
Hold Time (th) Minimum time input D must remain stable AFTER the clock edge.
Propagation Delay (tpd) Time from clock edge to stable output Q. Determines maximum
clock frequency.
Clock-to-Q Delay Specific propagation delay from clock edge to Q output changing.
Maximum Clock Freq fmax = 1 / (tpd + tsu + th + routing delay). Violating this causes
metastability.
 6. REGISTERS & COUNTERS

6.1 Registers
A register is a group of flip-flops storing multiple bits. An n-bit register holds n bits of data.

Types of Registers
Term Definition
Parallel In / Parallel Out All bits loaded and output simultaneously. Used as buffer/holding
(PIPO) registers.
Serial In / Serial Out Data enters and exits one bit at a time. Acts as a time-delay
(SISO) element.
Serial In / Parallel Out Data enters serially; all bits available at once after n clock pulses.
(SIPO) Used in serial-to-parallel conversion (e.g., UART receiver).
Parallel In / Serial Out All bits loaded at once; data exits one bit at a time. Used in parallel-
(PISO) to-serial conversion.
Universal Shift Register Can perform all four modes above, plus left-shift and right-shift.
Controlled by mode select lines.

Shift Register Applications

• Serial data transmission / reception (UART, SPI, I2C)
• Ring counter and Johnson counter construction
• Time delay buffers
• Pseudo-random number generation (LFSR)

6.2 Counters
Counters are sequential circuits that count clock pulses. They cycle through a defined sequence of
states.

Asynchronous (Ripple) Counter

• Each flip-flop is clocked by the output of the previous one — clock 'ripples' through
• Simple to design but has propagation delay accumulation
• Delay grows with more bits — problematic at high frequencies
• Example: 4-bit ripple counter using T flip-flops counts 0–15

Synchronous Counter
• All flip-flops share the SAME clock signal — no ripple delay
• Faster and more reliable for high-speed operation
 • More complex hardware (requires AND gates for carry logic)
• Preferred for most modern digital systems

Counter Types & Modulus

Term Definition
Mod-N Counter Counts N states (0 to N-1) then resets. Requires log₂N flip-flops
(round up).
Up Counter Increments count by 1 each clock pulse.
Down Counter Decrements count by 1 each clock pulse.
Up/Down Counter Controlled by a direction input: counts up or down.
Ring Counter One 1 circulates through n flip-flops. Has n states. Simple decoder-
free design.
Johnson Counter Twisted ring counter. Has 2n states from n flip-flops. Used in phase
generation.
BCD Counter Mod-10 counter. Counts 0–9 then resets. Used in decade counters
for displays.

💡 Exam Tip: Flip-Flop Count

To build a Mod-N counter: use ⌈log₂N⌉ flip-flops. Mod-8 → 3 flip-flops (2³=8) | Mod-10 → 4 flip-
flops (2⁴=16, but only 10 states used) Mod-16 → 4 flip-flops | Mod-32 → 5 flip-flops
 7. SEMICONDUCTOR MEMORY

Memory stores binary data. It is classified by volatility, access method, and read/write capability.

7.1 Memory Classification

Type Volatile? Writable? Example
SRAM Yes (volatile) Yes (R/W) Cache memory,
registers
DRAM Yes (volatile) Yes (R/W) Main RAM (DDR)
ROM No (non-volatile) No (read only) BIOS, boot firmware
PROM No Once (OTP) Field programming
EPROM No UV erasable Older microcontrollers
EEPROM No Electrically Config storage
Flash No Block erase USB drives, SSDs

7.2 SRAM vs DRAM

Term Definition
SRAM (Static RAM) Uses 6 transistors per bit (flip-flop). Fast, no refresh needed. Used
in CPU caches. More expensive per bit.
DRAM (Dynamic RAM) Uses 1 transistor + 1 capacitor per bit. Slower, needs periodic
refresh (capacitor leaks). Much denser, cheaper. Main system
RAM.

7.3 Memory Organisation

Memory capacity = Number of words × Word length. Example: 1K × 8 = 1024 bytes = 8192 bits.
• Address lines: n address lines → 2ⁿ addressable locations
• Data lines: width of each memory word (typically 8, 16, 32, or 64 bits)
• Memory expansion: multiple chips can be combined in depth (more words) or width (wider words)
 8. ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG
CONVERTERS

Real-world signals are analog (continuous). Digital systems need ADC/DAC to interface with the analog
world.

8.1 Digital-to-Analog Converter (DAC)

Converts a binary number to a proportional analog voltage or current.

Weighted Resistor DAC

• Each bit drives a resistor weighted by its binary significance (R, 2R, 4R, 8R...)
• Simple concept but requires precision resistors spanning a wide range
• Impractical for > 4 bits due to wide resistor range

R-2R Ladder DAC ★ Most Common

• Uses only TWO resistor values: R and 2R — much easier to manufacture precisely
• Can be extended to any number of bits without changing existing resistors
• Output voltage proportional to digital input value
💡 DAC Output Formula
Vout = Vref × (digital input / 2ⁿ) where n = number of bits Example: 8-bit DAC, Vref=5V,
input=128 → Vout = 5 × (128/256) = 2.5V

8.2 DAC Performance Parameters

Term Definition
Resolution Smallest output change = Vref / 2ⁿ. More bits = finer resolution. 8-
bit: 256 steps; 12-bit: 4096 steps.
Full Scale Output Maximum output voltage = Vref × (2ⁿ-1)/2ⁿ ≈ Vref
Settling Time Time for output to settle within ½ LSB of final value after input
changes.
Linearity Error Deviation from ideal straight-line transfer characteristic.
Monotonicity Output always increases (or stays same) as digital input increases.

8.3 Analog-to-Digital Converter (ADC)

Converts a continuous analog voltage into a discrete digital code through sampling and quantisation.
Flash (Parallel) ADC — Fastest
• Uses 2ⁿ-1 comparators operating simultaneously
• All bits output at once — extremely fast (GHz range)
• Very expensive: 8-bit needs 255 comparators; 12-bit needs 4095
• Used in: oscilloscopes, radar, video processing

Successive Approximation ADC (SAR) — Most Common

• Uses a binary search algorithm: tests MSB first, then next bit, etc.
• Requires exactly n clock cycles for n-bit conversion
• Good balance of speed, cost, and resolution
• Used in: microcontrollers, data acquisition systems

Dual-Slope (Integrating) ADC — Most Accurate

• Integrates input for fixed time, then integrates reference until zero
• Inherently rejects power-line noise (50/60 Hz)
• Slow but very accurate — used in digital multimeters

Sigma-Delta ADC — High Resolution

• Oversamples at very high frequency with 1-bit quantisation
• Digital filtering reduces noise and increases effective resolution
• Used in: audio systems, precision instrumentation (16–24 bit)

8.4 ADC Performance Parameters

Term Definition
Resolution n bits → 2ⁿ quantisation levels. More bits = finer measurement.
Sampling Rate Samples per second (S/s). Must satisfy Nyquist: fs ≥ 2 × fmax
signal.
Nyquist Theorem Sample at least TWICE the highest frequency component to
reconstruct perfectly. Violation causes aliasing.
Quantisation Error Inherent error = ±½ LSB. Cannot be eliminated, only reduced with
more bits.
SNR (Signal-to-Noise SNR ≈ 6.02n + 1.76 dB for ideal ADC with n bits. More bits = better
Ratio) SNR.
Aliasing Distortion when fs < 2×fmax. Prevented by anti-aliasing low-pass
filter before ADC.
 9. MICROPROCESSORS & MICROCONTROLLERS

9.1 Microprocessor Architecture

A microprocessor (MPU) is a programmable digital device that reads instructions from memory and
executes them.

Key Components
• Performs arithmetic (+, −, ×, ÷) and logical (AND, OR, NOT, XOR) operations: ALU
(Arithmetic Logic Unit)
• Decodes instructions, generates control signals, coordinates all components: Control Unit
(CU)
• Small, ultra-fast on-chip storage. Types: accumulator, program counter, stack pointer,
general purpose, flags/status: Registers
• Holds address of NEXT instruction to fetch. Auto-increments after each fetch: Program
Counter (PC)
• Points to top of stack in memory. Used for subroutine calls, interrupts: Stack Pointer (SP)
• Holds condition codes: Zero (Z), Carry (C), Sign/Negative (N), Overflow (V), Interrupt
enable: Status/Flag Register

9.2 Buses
Term Definition
Address Bus Unidirectional (CPU → memory/IO). n bits → 2ⁿ addressable
locations. 16-bit: 64KB; 32-bit: 4GB.
Data Bus Bidirectional. Transfers data between CPU, memory, and
peripherals. Width = word size (8, 16, 32, 64 bit).
Control Bus Carries timing and control signals: Read/Write, Memory Enable,
IO/M, Clock, Reset, Interrupt, DMA.

9.3 Instruction Execution Cycle (Fetch-Decode-Execute)

1. FETCH: Load instruction from address in PC into Instruction Register. Increment PC.
2. DECODE: Control Unit interprets the opcode to determine operation and addressing mode.
3. FETCH OPERANDS: If required, fetch data from memory or registers.
4. EXECUTE: ALU performs the operation; result stored in register or memory.
5. WRITE BACK: Store result. Update flags. Return to step 1.
9.4 Addressing Modes
Term Definition
Immediate Operand is part of the instruction itself. Fast, no memory access.
Example: MOV A, #25H
Register Operand is in a register. Fastest execution. Example: MOV A, B
Direct Instruction contains the memory address of operand. Example:
MOV A, 2050H
Indirect Instruction contains a register that holds the address. Flexible for
arrays. Example: MOV A, @HL
Indexed Effective address = base register + offset. Used for array access.
Relative Address = PC + signed offset. Used in branch/jump instructions.
Implied/Inherent No operand needed — operation is implicit. Example: CMA
(Complement Accumulator)

9.5 Interrupts
An interrupt is a signal that temporarily halts the main program to handle an urgent event.
• Hardware interrupt: triggered by external device (keyboard, timer, ADC)
• Software interrupt: triggered by instruction (INT n, trap, system call)
• Maskable interrupt: can be disabled by software (INTR pin in 8085)
• Non-maskable interrupt: cannot be disabled — handles critical events (TRAP in 8085)
• ISR (Interrupt Service Routine): code that handles the interrupt; CPU jumps here, executes, then
returns
💡 Interrupt Process
1. Interrupt signal arrives 2. CPU finishes current instruction 3. CPU saves PC (and possibly
other registers) to stack 4. CPU jumps to Interrupt Vector (address of ISR) 5. ISR executes 6.
CPU restores saved state, resumes main program

9.6 Microcontroller vs Microprocessor

Term Definition
Microprocessor (MPU) CPU only — no built-in memory or I/O. Needs external RAM, ROM,
peripherals. High performance. Example: Intel Core i7, 8085.
Microcontroller (MCU) CPU + RAM + ROM/Flash + I/O + timers + ADC all on ONE chip.
Self-contained. Low power. Example: Arduino (ATmega328), PIC,
STM32.
Application MPU: computers, servers. MCU: embedded systems, appliances,
IoT devices, robots.
 10. QUICK REVISION — EXAM CHEAT SHEET

10.1 Formulas to Memorize

Topic Formula / Key Fact
Number of states (n bits) 2ⁿ states
Flip-flops for Mod-N counter ⌈log₂N⌉ flip-flops
Address lines for memory n lines → 2ⁿ locations
DAC output voltage Vout = Vref × (Din / 2ⁿ)
ADC resolution (step size) Vstep = Vref / (2ⁿ - 1)
ADC SNR (ideal) SNR = 6.02n + 1.76 dB
Nyquist sampling rate fs ≥ 2 × f_max
Max clock frequency fmax = 1/(tpd + tsu + th)
JK characteristic eqn Q(next) = JQ' + K'Q
T characteristic eqn Q(next) = T ⊕ Q
D characteristic eqn Q(next) = D
XOR as adder Sum = A⊕B; Carry = A·B
De Morgan #1 (AB)' = A' + B'
De Morgan #2 (A+B)' = A'·B'

10.2 Common Exam Traps

💡 Watch Out For These!
• SR Latch: S=R=1 is FORBIDDEN (undefined state) • K-Map groups must be powers of 2
(1,2,4,8...) — never 3, 5, 6... • NAND/NOR universal gates: you can build ANY gate using only
one type • Ripple counter: slower than synchronous due to cumulative propagation delay • ADC
aliasing: ALWAYS need anti-aliasing filter before sampling • 2's complement: adding 1 to 1's
complement gives 2's complement • Full adder vs Half adder: full adder handles carry-in; half
adder does NOT • Gray code: adjacent values differ by EXACTLY 1 bit (unlike binary) • DRAM
needs refresh; SRAM does NOT (but SRAM is faster and more expensive)

10.3 Last-Minute Study Priority

6. Logic gate truth tables (AND, OR, NOT, NAND, NOR, XOR, XNOR)
7. Boolean theorems — especially De Morgan's laws
8. Flip-flop characteristic equations (D, JK, T)
9. Binary ↔ Decimal ↔ Hex conversions
10. DAC/ADC resolution formulas and types
11. Fetch-decode-execute cycle and bus types
12. Counter types: synchronous vs asynchronous, mod-N flip-flop count
13. Memory types: SRAM vs DRAM, ROM variants, volatile vs non-volatile

You've got this! 🚀

Review one section per study session, get good sleep before the exam,
and trust the knowledge you've built. Good luck on Monday! 🎯