CS25C06-Digital

Principles and Computer

Organization
Dr. A. MUTHUMARI
Assistant Professor ([Link].)
Department of Computer Science
and Engg.
AURC- Madurai
Input/Output System
Peripheral Devices (I/O Devices)

▶ Input/Output devices that are connected to a system are called Peripheral devices.
▶ These devices are designed to read information into or out of the memory or CPU upon
command from the CPU and are considered to be the part of computer system.
▶ For example: Keyboards, display units, printers etc. are common peripheral devices.
There are three types of peripherals:
1. Input peripherals: Allows user input from the outside world to the computer. Example:
Keyboard, Mouse etc.
2. Output peripherals: Allows information output from the computer to the outside world. Example:
Printer, Monitor etc.
3. Input-Output peripherals: Allows both input (from outside world to computer), as well as, output
(from computer to the outside world). Example: External memory devices.
Accessing I/O Devices

▶ Generally more numbers of devices are connected to a computer.

▶ So, some means have to be provided by which a particular device can
be selected to participate in a given I/O operation.
▶ This can be accomplished through the use of an I/O bus arrangement.
▶ I/O bus is the bus to which all I/O devices are connected used for
address, data and control signals.
▶ Each device is assigned an identifying code or address so that the
CPU can select a particular device by placing its address in the
address line.
▶ Only the device that recognizes its address responds to the CPU.
▶ This is called as I/O mapped I/O.
▶ An alternative arrangement for identifying I/O devices
are by assigning them by an unique address within the
memory address space of the computer.
▶ It become possible to access I/O device in the same way
as any other memory location accessing.
▶ This is known as Memory mapped I/O.
▶ Any machine instruction
and addressing mode that
can be used to deal with
operands can also refer to
an I/O device.
▶ The use of memory mapped
I/O offers some flexibility
in handling I/O operation.
▶ All the devices are
connected to the I/O bus
through a hardware device
or circuit is called as I/O
Interface.
I/O Interface

▶ Input/Output Interface provides a method for transferring

instruction between internal storage device and external
I/O device.
▶ Peripherals connected to a computer need special
communication link for interfacing them with the CPU.
▶ The purpose of communication link is to resolve the
differences that exists between the CPU and peripherals
and among peripherals.
The major differences are as follows:
1. Peripheral devices are electromagnetic or electro-mechanical. The CPU is purely
electronic device. The nature of operation of peripheral device is different from the
operation of CPU. Therefore a conversion of signal values may be required.
2. The data transfer rate of peripherals are usually slower than CPU. So,
synchronization mechanism may be needed.
3. The data code and formats in peripherals differ from the word format in the CPU
and memory. So, conversion mechanism may be needed.
4. The operating modes of peripherals are different from each other and each must be
controlled so as not to disturb the operation of other peripherals connected to CPU.
Interface Module

▶ To resolve these differences there is a need

of special hardware component between
CPU and peripheral devices to supervise and
synchronize all input and output transfers.
▶ This component is called as Interface unit or
I/O module.
▶ The data register is used to hold data to be
transferred.
▶ Status register is required to store the status,
that is, status or condition of the device for
operation.
▶ Control circuit is for receiving and sending
control signals to or from control unit.
Interrupt

▶ A computer must have some means to coordinate its activities with the external devices connected
to it.
▶ When accepting characters from a keyboard, the computer needs to know when a new character has
been typed.
▶ Similarly, during the output operation, it should send a character to a printer if the printer is ready to
accept it.
▶ The current status of each I/O device connected to a computer is indicated by one or more bits of
information.
▶ A program may run within the CPU to poll the device by testing the status bits before using an I/O
instruction to transfer data.
▶ During this polling period the CPU does not perform any useful computation.
▶ So, an alternative arrangement is required that when the I/O device will ready, it will alert the CPU.
▶ This can be possible by sending a signal called Interrupt.
▶ An interrupt is a signal emitted by
hardware or software that requests
the processor to suspend its current
execution and service the occurred
interrupt.
▶ To service the interrupt the
processor executes the
corresponding interrupt service
routine (ISR).
▶ After the execution of the interrupt
service routine, the processor
resumes the execution of the
suspended program.
Types of Interrupt

▶ There are two types of interrupt.

❑ Hardware Interrupt
❑ Software Interrupt
▶ Hardware Interrupt: If the signal for the processor is from external or
internal device or hardware is called hardware interrupt.
▶ Example: From keyboard we will press the key to do some action, this
pressing of key in keyboard will generate a signal which is given to the
processor to do action, such interrupt is hardware interrupt.
▶ Hardware interrupt may be generated from external device/hardware or
internal device/hardware.
▶ So, it may be External interrupt or Internal interrupt.
▶ External Interrupt: It comes from I/O devices, timing device, power failure or
from any other external hardware.
▶ Example: I/O device request for transfer of data.
I/O device finished transfer of data.
Elapse of time of an event – Time out
Power failure etc.
▶ Internal Interrupt: Arises illegal or erroneous use of an instruction or data and any
overflow/underflow condition.
▶ Example: Register overflow/underflow.
Stack/Queue overflow/underflow.
Attempt to divide by zero.
Invalid operation code etc.
▶ Internal interrupt is initiated by some exceptional
condition caused by the program itself rather than by
an external event.
▶ Internal interrupt is synchronous with the program
while external interrupt is asynchronous.
▶ If a program is rerun, the internal interrupt will occur
in the same place each time. The external interrupt
depends on external conditions that are independent of
the program being executed at that time.
▶ The hardware interrupts may be maskable or non-maskable.
▶ Maskable Interrupt: The hardware interrupt that can be ignored or
delayed for some time if the processor is executing a program with
higher priority are termed as maskable interrupts.
▶ This type of interrupt is entertained by the CPU just after completion
of current execution.
▶ Non-Maskable Interrupt: The hardware interrupts that can neither
be ignored nor delayed and must immediately be serviced by the
processor are termed as non-maskable interrupts.
▶ When a non-maskable interrupt arises, the CPU suddenly stops the
current execution and jumps to entertain the interrupt.
▶ Software Interrupts: A software interrupt is initiated by executing an instruction.
▶ This type of interrupt can be used by the programmer to initiate an interrupt procedure at
any desired point in the program.
▶ Software interrupt is a special CALL instruction that behaves like an interrupt rather than a
subroutine call.
▶ When an interrupt is initiated the Interrupt Service Routine (ISR) is executed.
▶ The way the processor chooses the branch address of the service routine, the interrupt may
be Non vectored interrupt or Vectored interrupt.
▶ Non vectored: In this case the branch address is assigned to a fixed location in the memory
where corresponding ISR is stored.
▶ Vectored: The source of the interrupt that supplies the branch information to the computer.
▶ This information is called the interrupt vector.
Modes of Data Transfer

▶ The data transfer between CPU and I/O devices may be handled
in a variety of modes.
▶ Some modes use the CPU as an intermediate path, others may
transfer data directly to and from the memory unit.
▶ Data transfer to and from peripherals may be handled in one of
the three possible modes.
❑ Programmed I/O
❑ Interrupt initiated I/O
❑ Direct Memory Access (DMA)
Programmed
I/O
▶ Programmed I/O operations are results of I/O operations written in computer program.
▶ Each data item transfer is initiated by an instruction in the program.
▶ Example: In this case, the I/O device does not have direct access to the memory unit. A
transfer from I/O device to memory requires the execution of several instructions by the
CPU, including an input instruction to transfer the data from device to the CPU and store
instruction to transfer the data from CPU to memory.
▶ Transferring data under program control requires constant monitoring of the peripheral by
the CPU.
▶ The CPU stays in the program loop (polling) until the I/O unit indicates that it is ready for
data transfer. X =A+ B
PUSH A
▶ This is a time consuming process since it needlessly keeps the CPU busy. PUSH B
ADD
▶ This situation can be avoided by using an interrupt facility. STORE X
Interrupt Initiated I/O

▶ In programmed I/O, the CPU remain busy unnecessarily.

▶ This situation can very well be avoided by using an interrupt driven method
for data transfer.
▶ When the interface determines that the device is ready for data transfer, it
generates an interrupt request signal to the CPU.
▶ In the meantime the CPU can proceed for any other program execution.
▶ Upon detection of an external interrupt signal the CPU momentarily stops the
execution of current task, the control branches to a service routine to process
the required I/O transfer, and then return to the task it was originally
performing.
▶ But what if multiple devices generate interrupts simultaneously.
Priority Interrupt

▶ In that case, there must have a way to decide which interrupt is to be serviced first.
▶ In other words, the priority must be assigned to all the devices for systemic
interrupt servicing.
▶ The concept of defining the priority among devices so as to know which one is to
be serviced first in case of simultaneous requests is called priority interrupt
system.
▶ Generally devices with high speed of data transfer, such as, magnetic disks are
assigned high priority than slow devices, such as, Keyboard.
▶ When multiple devices interrupt the system at the same time, the service given to
the device with highest priority.
▶ This could be done with either software or hardware methods.
Software Priority Method

▶ In this method a Polling procedure is used to identify the highest priority device by software
means.
▶ There is one common branch address for all interrupt to execute the ISR.
▶ The program that takes care of interrupts begins the execution of the ISR and Polls the
interrupt sources in sequence.
▶ The order in which they are tested determines the priority of the interrupt and its
corresponding device.
▶ If the highest priority device interrupt signal is on, then the service is given to that device.
▶ Otherwise, the next lower priority source is tested and so on.
▶ The major disadvantage of this method is that it is quite slow.
▶ To overcome this, we can use hardware priority interrupt.
Hardware Priority Method

▶ A hardware priority interrupt unit functions as an overall manager

in an interrupt system environment.
▶ To speed up the operation, each interrupt source has its own
interrupt vector to access its own ISR directly.
▶ So, no polling is required as all the decisions are established by the
hardware priority interrupt unit.
▶ The hardware priority function can be established by either a serial
or a parallel connection of interrupt lines.
▶ The serial connection of hardware priority interrupt method is
known as Daisy-Chaining Method.
Daisy-Chaining Priority interrupt Method

PI PO Operation

0 0 Acknowledge has been blocked

1 0 Particular VAD selected (Pending interrupt)
1 1 Transmit Acknowledge to next device
▶ The daisy-chaining method involves connecting all the devices that can request an
interrupt in a serial manner.
▶ This configuration is governed by the priority of the devices.
▶ The device with the highest priority is placed first position (nearer to CPU) followed
by lower priority device and so on up to the lowest priority device.
▶ There is an interrupt request line which is common to all the devices and goes into the
CPU.
▶ If any of the device raises an interrupt, it places the LOW (0) state in the interrupt
request line.
▶ When no interrupts are pending, the line is in HIGH (1) state.
▶ The CPU responds to an interrupt request by enabling the interrupt acknowledge line.
▶ This signal is received at the PI (Priority in) input of device 1.
▶ If the device has not requested the interrupt or no pending request, it passes
this signal to the next lower priority device through its PO (priority out)
output as (PI = 1 & PO = 1).
▶ However, if the device had requested the interrupt, (PI =1 & PO = 0).
• The device consumes the acknowledge signal and block its further use by
placing 0 at its PO (priority out) output.
• The device then places its interrupt vector address (VAD) into the
processor bus.
• The device puts its interrupt request signal in HIGH (1) state to indicate
its interrupt has been taken care of.
NOTE: VAD is the address of the service routine which services that device.
▶ If a device gets 0 at its PI input, it generates 0 at the PO output to
tell other devices that acknowledge signal has been blocked, that is,
(PI = 0 & PO = 0).
▶ Therefore, by daisy chain arrangement we have ensured that the
highest priority interrupt gets serviced first and have established a
hierarchy.
Direct Memory Access (DMA)

▶ The programmed I/O (CPU has to check for I/O device) and Interrupt-driven I/O (CPU
doesn’t has to check for I/O device, I/O device generate the interrupt signal) require the
active intervention of the processor to transfer data between memory and the I/O module,
and data transfer must traverse through the processor.
▶ DMA is a process of communication for data transfer between memory and input/output
device, controlled by an external circuit called DMA controller, without involvement of
CPU.
▶ DMA is a way to improve processor activity and I/O transfer rate by taking-over the job
of transferring data from processor and allow the processor to do other tasks.
▶ The DMA controller takes over the buses to manage the transfer directly between the I/O
devices and the memory unit.
▶ DMA controller is a hardware unit that allows I/O devices to access memory directly
without the participation of the processor.
 DMA Controller

▶ Whenever an I/O device wants to transfer

the data to or from memory, it sends the
DMA request (DRQ) to the DMA
controller.
▶ DMA controller accepts this DRQ and asks
the CPU to hold for a few clock cycles by
sending it to the CPU Bus Request (BR) or
Hold request (HLD) signal.
▶ Bus Request (BR) or Hold request (HLD):
It is used by the DMA controller to request
the CPU to give up the control of the IC 8257/8237

buses.
▶ After receiving Bus Request signal from DMA controller, the CPU acknowledges it
by granting Bus Grant (BG) or Hold acknowledgement (HLDA) to the DMA
Controller.
▶ Bus Grant (BG) or Hold acknowledgement (HLDA): It is activated by the CPU to
inform the DMA controller that the DMA controller can take control of the buses.
▶ After receiving the Hold acknowledgement (HLDA), DMA controller acknowledges
I/O device (DACK) that the data transfer can be performed to or from memory and
DMA controller takes the charge of the system bus.
▶ When the data transfer is completed, the DMA controller raise an Interrupt to the
processor that the task of data transfer is finished and the processor can take control
over the buses again and it will start processing where it has left.
DMA block diagram

▶ The DMA controller has an address register, a

word/data count register, data register and a
control logic unit.
▶ Whenever a processor is requested to read or
write a block of data, it instructs the DMA
controller by sending the following information.
▶ The first information is whether the data has to
be read from memory or the data has to write to
the memory.
▶ It passes this information via read or write
control line that is between the processor and
DMA controller Control logic unit.
▶ The processor also provides the starting address of the data block in the memory,
from where it has to be read or where the data block has to be written in memory.
▶ DMA controller stores this in its address register. It is also called the starting
address register.
▶ The processor also sends the word count, that is, how many words are to be read
or written.
▶ The DMA controller stores this information in the data count or word count
register. The register count is decremented by one after each word transfer and
internally it is tested for zero.
▶ The most important is the address of I/O device that wants to read or write data.
This information is stored in the data register.
▶ The CPU will not directly provide the BG to DMA
Controller. First the registers in the DMA controller are
selected by the CPU through the address bus by enabling
the DS (DMA Select) and RS (Register Select) inputs.
▶ Then it will provide the basic information of address
register, a word count register and a control register.
▶ When the BG (Bus Grant) input is 0, the CPU can
communicate with the Data Bus to read from or write to
the DMA registers.
▶ When BG =1, the CPU relinquish the buses and the
DMA controller can communicate directly with the
memory by specifying an address in the address bus and
activating the RD or WR control.
DMA Data Transfer

1. Burst Mode:
➢ Here, once the DMA controller gains the charge of the system bus,
an entire block of data is transferred in one contiguous sequence.
➢ Then it releases the system bus to the CPU only after completion
of data transfer.
➢ Till then the CPU has to wait for the system buses. CPU remains
inactive relatively long period of time.
➢ It can perform any work without the requirement of system bus.
➢ Basically used to transfer large volume of data.
➢ It is also called as Block transfer mode.
2. Cycle Stealing Mode:
➢ In this mode, the data transfer is byte by byte or word by word.
➢ The DMA controller forces the CPU to stop its operation and relinquish the
control over the bus for a short period to DMA controller.
➢ After the transfer of every byte, the DMA controller releases the bus and then
again requests for the bus.
➢ This will continue to complete the data transfer of entire block.
➢ In this way, the DMA controller steals the clock cycle for transferring every byte.
➢ Basically used to transfer very small volume of data.
➢ More time required to transfer total block of data.
➢ But, CPU utilization is more than the Burst mode.
3. Transparent Mode
➢ DMA controller takes charge of system bus for data transfer only when CPU performing operations
without using system bus.
➢ CPU executes the program and DMA controller takes charge of data transfer.
➢ When the CPU requires the system bus the DMA controller releases the control over buses.
➢ Complex hardware.

Advantages - allows a peripheral device to read from/write to memory without going

through the CPU
- allows for faster processing since the processor can be working on
something else while the peripheral can be busy with memory
Disadvantages - requires a DMA controller to carry out the operation, which increases
the cost of the system
- cache coherence problems
 Interface Standards

PCI
USB
SATA
1 Address Phase
• The initiator (master) places the address on the AD bus.
• The command (Read) is placed on C/BE#.
• FRAME# is asserted low to indicate the start of a transaction.
2 Device Selection
• The target device that matches the address asserts DEVSEL# (low).
• This means the device has been selected for the transaction.
3 Data Transfer Phase
• The target places data (#1, #2, #3, #4) on the AD bus.
• IRDY# (Initiator Ready) indicates the master is ready to receive data.
• TRDY# (Target Ready) indicates the target is ready to send data.
• Data transfer happens only when both IRDY# and TRDY# are low.
4 Burst Transfer
• Multiple data words are transferred in successive clock cycles (#1 to #4).
• This is called burst mode transfer.
5 End of Transaction
• When all data is transferred, FRAME# is de-asserted (goes high).
• Then IRDY# and TRDY# are de-asserted, ending the transaction.
Universal Serial Bus (USB)
 Universal Serial Bus
• A representative peripheral interface
• Universal Serial Bus (USB) provides a serial bus standard for connecting devices, usually to a
computer, but it also is in use on other devices such as set-top boxes, game consoles and PDAs.
([Link])
 What USB Can Do
• USB is a likely solution any time you want to use a computer to communicate with devices outside the computer.

• The interface is suitable for one-of-kind and small-scale designs as well as mass-produced, standard peripheral
types.
 USB
• Fast
• Bi-directional
• Isochronous
• low-cost
• dynamically attachable serial interface
• consistent with the requirements of the PC platform of today and tomorrow
•
USB
Four wires (+5V, Return, data twisted pair)
• Up to 5 m (16.4 ft)
Longer connections use hubs or active
extensions
 Features of USB
• Easy to use for end user
– Single model for cabling and connectors
– Electrical details isolated from end user (e.g., bus terminations)
– Self-identifying peripherals, automatic mapping of function to driver, and configuration
– Dynamically attachable and re-configurable peripherals
• Wide range of workloads and applications
– Suitable for device bandwidths ranging from a few kb/s to several Mb/s
– Supports isochronous as well as asynchronous transfer types over the same set of wires
– Supports concurrent operation of many devices (multiple connections)
– Supports transfer of multiple data and message streams between the host and devices
• Low-cost implementation
– Low-cost sub-channel at 1.5Mb/s
– Suitable for development of low-cost peripherals
– Low-cost cables and connectors
• Upgrade path
– Architecture upgradeable to support multiple USB Host Controllers in a system
 Features of USB (cnt..)
• Asynchronous bandwidth
– Guaranteed bandwidth and low latencies appropriate for telephony, audio, etc.
– asynchronous workload may use entire bus bandwidth
• Flexibility
– Supports a wide range of packet sizes, which allows a range of device buffering options
– Allows a wide range of device data rates by accommodating packet buffer size and latencies
– Flow control for buffer handling is built into the protocol
• Robustness
– Error handling/fault recovery mechanism is built into the protocol
– Dynamic insertion and removal of devices is identified in user-perceived real-time
– Supports identification of faulty devices
 Comparison
Interface Format Number of Length Speed Typical Use
Devices (maximum, (maximum,
(maximum) feet) bits/sec.)
USB asynchronous 127 16 (or up to 1.5M, 12M, Mouse,
serial 96 ft. with 5 480M keyboard, disk
hubs) drive, modem,
audio
RS-232 asynchronous 2 50-100 20k (115k Modem, mouse,
(EIA/TIA-232) serial with some instrumentation
hardware)
Parallel Printer parallel 2 (8 with 10–30 8M Printers,
Port daisy-chain scanners, disk
support) drives
 Benefits for Users
• Ease of Use
Ease of use was a major design goal for USB, and the result is an interface that’s a pleasure to use for many reasons:

• One interface for many devices.

USB is versatile enough to be usable with many kinds of peripherals. Instead of having a different connector type and
supporting hardware for each peripheral, one interface serves many.

• Automatic configuration.
When a user connects a USB peripheral to a computer, its OS automatically detects the peripheral and loads the appropriate
software driver.

• Hot pluggable
We can connect and disconnect a peripheral whenever you want, whether or not the system and peripheral are powered,
without damaging the PC or peripheral. The operating system detects when a device is attached and readies it for use.

• No power supply required (sometimes).

A peripheral that requires up to 500 milliamperes can draw all of its power from the bus instead of having its own supply..
 USB

⚫ USB 1.0 specification introduced in 1994

⚫ USB 2.0 specification finalized in 2001
⚫ Became popular due to cost/benefit advantage
⚫ Eg. IEEE 1394 – high bandwidth, high cost
⚫ Three generations of USB
⚫ USB 1.0
⚫ USB 2.0
⚫ USB 3.0 and WUSB
 Physical Appearances

• Type A connectors on host devices that supply power

• Type B connectors on target devices that receive power.
Serial Advanced Technology Attachment
(SATA)
Characteristics of SATA

• Low Voltage Requirement

• Simplified construction
• Differential Signalling
• High data transfer rate

Advantages of SATA
• Faster data transfer rate as compared to PATA
• SATA cable can be of length upto 1 meter, whereas PATA cable can only have length of
maximum 18 inches.
• SATA cables are smaller in size.
• Most modern computer motherboards today have SATA ports more than PATA ports.
• Low power consumption (0.5V).
Disadvantages of SATA
SATA standards and revisions
BUS
Bus Interconnection

▶ If a computer is to achieve a reasonable speed of operation, it must be organized so

that all units can handle one full word of data at a given time.
▶ When a word of data is transferred between units, all its bits are transmitted in
parallel.
▶ This requires a considerable number of wires (lines) to establish the necessary
connections.
▶ BUS: A collection of wires that connects several devices to carry the information to
or from different units of the system is called as BUS.
Three types Bus
▪ Data Bus
▪ Address Bus
▪ Control Bus
The interconnection structure must support
the following types of transfers:

Memory Processor I/O to or

I/O to Processor
to to from
processor to I/O
processor memory memory
An I/O
module is
allowed to
exchange
Processor Processor
Processor Processor data directly
reads an reads data with memory
writes a unit sends data to
instruction or from an I/O without going
of data to the I/O
a unit of data device via an through the
memory device
from memory I/O module processor
using direct
memory
access
 A communication Signals transmitted by any one
pathway connecting device are available for reception by
two or more devices all other devices attached to the bus
• Key characteristic is • If two devices transmit during the
that it is a shared same time period their signals will
transmission medium overlap and become garbled

Typically consists of Computer systems

multiple communication contain a number of
lines different buses that
Bus • Each line is capable of
provide pathways
between components at
Interconnection transmitting signals
representing binary 1
various levels of the
computer system
and binary 0
hierarchy

System bus The most common

• A bus that computer
connects interconnection
major computer structures are based on
components the use of one or more
(processor, memory, system buses
Data Bus

▶ Data lines that provide a path for moving data among system modules
▶ Number of wires depends on type of data transfer and word length
▶ May consist of 32, 64, 128, or more separate lines for parallel communication
▶ One line is required for serial communication
▶ The number of lines is referred to as the width of the data bus
▶ The number of lines determines how many bits can be transferred at a time (word
length)
▶ The width of the data bus is a key factor in
determining overall system performance
▶ Direction is Bidirectional
Address Bus

▶ Used to designate the source or destination of the data

▶ If the processor wishes to read or write a word of data
from or to memory it puts the address of the desired
word on the address lines
▶ Width determines the maximum possible memory capacity
of the system
▶ Also used to address I/O ports
▶ Used to select a I/O port
▶ Direction is unidirectional
Control Bus

▶ All the functions of the system must be synchronized and controlled

▶ This is the function of control unit which provides control signals through buses
▶ Used to control the access and the use of the data and address lines
▶ Because the data and address lines are shared by all components there must be a means
of controlling their use
▶ Control signals transmit both command and timing information among system modules
▶ Timing signals indicate the validity of data and address information
▶ Command signals specify operations to be performed
▶ Each line of the bus indicates a particular control signal
▶ A particular control line may be unidirectional or bidirectional but collectively as a bus
no concept of direction
Bus Structure

▶ According to the connection mechanism of different functional units the Bus structures are of two types
Single Bus structure
Multi-Bus structure

Single Bus structure:

▶ All units are connected to single I/O bus
▶ At any given time two units can actively use the bus
▶ Bus control is used to arbitrate multiple requests for use of bus
▶ Flexibility for attaching peripheral devices
▶ Low hardware complexity
▶ Low cost
▶ But, slower data transfer
Single Bus structure
Multi Bus structure:
▶ It is a simplest Multi bus (two bus) computer
▶ The processor interacts with memory through memory bus
▶ Input and output functions are handled over an I/O bus
▶ Data passes to memory for processing through the processor
▶ I/O transfers are usually under direct control of the processor
▶ Processor initiates the transfer and monitors their progress until completion
▶ In this architecture the processor sit ideally after initiating the I/O
operations till completion
▶ Wastage of CPU time which degrades the performance
▶ So, another multi bus architecture has been developed to enhance the
performance of the system
▶ It is another Multi bus (two bus) architecture
▶ Here, the position of memory and processor interchanged
▶ I/O transfers are performed directly to or from memory
▶ But, memory can not control the I/O transfer
▶ So, a control circuitry as part of the I/O equipment is necessary
▶ That control circuitry is a special purpose processor called as Peripheral Processor or
Secondary Processor or I/O Channel which controls the I/O transfer
▶ The main processor initiates I/O transfer by passing required information to the I/O channel
▶ The I/O channel then takes over and controls the actual transfer of data
▶ During I/O operations now the main processor is free and it can perform other CPU
operations
▶ So, the performance enhanced
 Types of Data Transfer

Types of Data Transfer

Parallel Data Transfer Serial Data Transfer

Asynchronous Data Transfer Synchronous Data Transfer Asynchronous Data Transfer

Strobe Controlled Handshaking

Source Initiated Destination Initiated Source Initiated

Synchronous Data Transfer

▶ Both sender and receiver share a common clock.

▶ For long distance transmission each unit is driven by separate clock of same
frequency.
▶ The transmitter transmits block of character along with synchronization information.
▶ The receiver decodes and find the synchronization information and keep its clock in
step with each other.
▶ The transmitter sends data, and the receiver counts the number of bits in the received
data.
▶ Furthermore, there are no gaps between data, that is, continuous transmission till
end.
▶ In this method, the timing signals must be accurate to transfer data efficiently.
▶ Moreover, this method is faster than asynchronous data transferring.
Asynchronous Parallel Data Transfer

▶ Asynchronous parallel data transfer between two independent units require control
signals for synchronization during the data transfer.
1. One way is by means of strobe pulse which is supplied by one of the units to other
unit when transfer has to occur. This method is known as “Strobe Control”.
2. Another method commonly used is to accompany each data item being transferred
with a control signal that indicates the presence of data in the bus. The unit
receiving the data item responds with another signal to acknowledge receipt of the
data. This method of data transfer between two independent units is said to be
“Handshaking”.
▶ Here we consider the transmitting unit as Source and receiving unit as Destination.
▶ The sequence of control during an asynchronous transfer depends on whether the
transfer is initiated by the source or by the destination.
▶ So, it can be further divided as source initiated and destination initiated.
 Source Initiated Strobe controlled

▶ The source unit first places the data on the data bus.
▶ After a brief delay to ensure that the data settle to
a steady value, the source activates a strobe pulse.
▶ The information on data bus and strobe control signal
remains in the active state for a sufficient period of
time to allow the destination unit to receive the data.
▶ The source removes the data from the data bus after
it disables its strobe pulse.
▶ The strobe signal disabled indicates that the data bus
does not contain valid data.
▶ New valid data will be available only after the strobe
is enabled again.
Destination Initiated Strobe controlled

▶ The destination unit initiates the data transfer.

▶ The destination unit first activates the strobe
pulse, informing the source is ready to receive
data or informing the source to provide the
data.
▶ Then the source unit may place the data on the
data bus.
▶ The data must be valid and remain in the bus
long enough for the destination unit to accept it.
▶ The destination unit then disables the strobe.
And source removes the data from data bus
after a time interval.
▶ In computer, in strobe initiated by source - the strobe may be a
memory-write control signal from the CPU to a memory unit. The
source, CPU, places the word on the data bus and informs the memory
unit, which is the destination, that this is a write operation.
▶ In the strobe initiated by destination - the strobe may be a memory-
read control from the CPU to a memory unit. Now the destination is
the CPU, initiates the read operation to inform the memory, which is a
source unit, to place selected word into the data bus.
▶ The transfer of data between the CPU and an interface unit is similar
to the strobe transfer.
Disadvantage
▶ In source unit that initiates the transfer has no way of knowing
whether the destination has actually received the data that was
placed on the bus.
▶ In a destination unit that initiates the transfer has no way of
knowing whether the source unit has actually placed data on the
bus.
▶ The Handshaking method solves this.
Handshaking

▶ The handshaking method is a two wire controlling method of data transfer.

▶ Handshaking method introduce a second control signal line that provides a reply to
the unit that initiates the transfer.
▶ In it, one control line is in the same direction as the data flow in the bus from the
source to destination to indicate the presence of valid data on the data bus.
▶ The other control line is in the other direction from destination to the source.
▶ It is used by the destination unit to inform the source whether the data accepted or not.

Data accepted/Ready for data

Source Initiated Handshaking

▶ Two handshaking lines are "data valid", which is

generated by the source unit, and "data accepted",
generated by the destination unit.
▶ The source initiates a transfer by placing data on the
bus.
▶ Then enable the data valid signal.
▶ The data accepted signal is then activated by
destination unit after it accepts the data from the bus.
▶ The source unit then disables its data valid signal
which invalidates the data on the bus.
▶ After this, the destination unit disables its data
accepted signal and the system goes into initial state.
▶ The source unit does not send the next data item
until the destination unit shows its readiness to
accept new data by disabling the data accepted
signal.
Destination Initiated Handshaking

▶ Two handshaking lines are "data valid", generated

by the source unit, and "ready for data" generated
by destination unit.
▶ Data transfer is initiated by destination, so source
unit does not place data on data bus until it receives
ready for data signal from destination unit.
▶ Enable ready for data.
▶ Source Places the data on data bus.
▶ Then enable the data valid signal.
▶ Destination accepts the data from the data bus.
▶ Then the destination disable the ready for data
signal after data acceptance.
▶ Now the source disable the data valid signal which
invalidate the data on data bus and the system goes
into initial state.
▶ Data transfer between an interface and an I/O device is
commonly controlled by a set of handshaking lines.
▶ The handshaking scheme provides a high degree of flexibility
because the successful completion of a data transfer relies on
active participation of both units.
▶ If a unit is faulty or the data transfer can not be performed
during specified time the time out error is generated.
Asynchronous Serial Data Transfer

▶ The transmitter and receiver generates their clock frequencies independently, but they
are more or less identical.
▶ Generally adopted for low speed transmission.
▶ Data transmitted character by character.
▶ The time interval between two character is not fixed.
▶ The technique adopted for asynchronous serial data transmission is called FRAMING.
▶ In this technique each character carries the information of START Bit and STOP Bit.
▶ If there is no transmission in the line then the line is maintained in high voltage level –
MARK.
▶ START Bit always is voltage level of Zero (0) – SPACE.
▶ After Start bit the data bits are transmitted followed by PARITY Bit and STOP Bit.
▶ The Parity bit may or may not present. If present always it is in either Low state (0) or High state (1)
depending on Parity generator.
▶ The Stop bit may be one bit or more bits. Always they are in High state (1).
▶ So, during transmission the data bits are framed with Start bit and Stop bits, called Framing.
 Synchronous Data Transfer Asynchronous Data Transfer
1. T w o units share a c o m m o n clock. 1. T w o units are independent and each
unit will h a v e their o w n private clock.
2. Data transfer between sender and 2. Data transfer between sender and
receiver are synchronized by the same r e c e i v e r is n o t s y n c h r o n i z e d b y t h e
clock pulse. s a m e clock pulse.
3. U s e d between the devices that 3. Used between the devices that does not
matches in speed. ma t ch in speed.
4. T h e t i m e i n t e r v a l o f t r a n s m i s s i o n is 4. T h e t i m e i n t e r v a l o f t r a n s m i s s i o n is
constant (due to c o m m o n clock) r a n d o m (due to r a n d o m c o m m o n
clock)

5. Bits are transmitted continuously to 5. B i t s a r e s e n t o n l y w h e n it is a v a i l a b l e

k e e p clock sy n ch ro n i zed in b ot h units. a n d t h e l i n e r e m a i n s i d l e w h e n t h e r e is
i n f o r m a t i o n is t ra n smi t t ed .
6. Fast. 6. Slow.
7. Costly. 7. Economical.
Communication Interface

▶ Serial transfer may be synchronous or asynchronous.

▶ The IC 8251A is a programmable chip designed for
synchronous and asynchronous serial data
communication.
▶ It is 25 pin DIP.
▶ It includes five blocks.
▪ Data bus buffer
▪ Read/Write control logic
▪ Modem control
▪ Transmitter
▪ Receiver

▶ It is also called as Universal Synchronous

Asynchronous Receiver and Transmitter (USART).
Bus Arbitration
1. Bus Sharing by Multiple Processors or
controllers
 Bus Arbitration Requirement

⚫ Several processor and several single

purpose processors sharing a bus.*
⚫ Bus can be granted to one processor at an
instance

*[A single purpose processor is also called

controller. A controller can be part of a
device or peripheral or port.]
Processor

Bus
Controller

Controller in a Controller for Controller at a IO

device DMA port
Processor

System buses shared between the controllers and an IO

processor and multiple controllers that have to access the bus,
but only one of them can be granted the bus master status at
any one instance
 Bus Arbitration Mechanism
⚫ System buses are shared between the
controllers and an IO processor and multiple
controllers that have to access the bus, but
only one of them can be granted the bus
master status at any one instance
⚫ Bus master has the access to the bus at an
instance
 Bus arbitration process
⚫ A process by which the current bus master
accesses the bus and then leaves the control
of bus and passes it to another bus-
requesting processor unit.
⚫ Three methods in bus arbitration process.
⚫ Daisy Chain method,
⚫ Independent Bus Requests and Grant
method,
⚫ Polling method
2. Daisy Chaining for Bus Sharing by
Multiple Processors or controllers
 Daisy chaining method

⚫ Centralized bus arbitration process.

⚫ Bus control passes from one bus master to
the next one, then to the next and so on.
⚫ Bus control passes from controller units C0
to C1, then to C2, then U3, and so on.
Processor
BR3
Bus
Controller BR2 Busy

BR1
Bus BG BR0
Controller C0 Controller C2 Controller C3 IO C4
Processor

Priority Highest Priority Lowest

Daisy Chaining
Sequence of Signals in the arbitration process
⚫ Bus-grant signal (BG) which functions like
a token, is first sent to C0.
⚫ If C0 does not need the bus, it passes BG to
C1.
⚫ A controller needing the bus raises a bus-
request (BR) signal.
⚫ A bus-busy (BUSY) signal generates when
that controller becomes the bus master.
 Signals in the arbitration process

⚫ When bus master no longer needs the bus, it

deactivates BR and BUSY signal also
deactivates.
⚫ Another BG is issued and passed from C0
to down the priority controllers one by one
[For example, COM2 to COM1 in IBM PC]
 Daisy method advantage

⚫ At each instance of bus access the i-th

controller gets the highest priority to bus
compared to (i + 1)th.
⚫ Controllers and processors priorities for
granting the bus access (bus master status)
fixed
3. Independent request and grant method for
Bus Sharing by Multiple Processors or
controllers
Processor Programmable
Priorities BR3
Bus
Controller BR2 Busy

BG1 BG2 BG3

BR1
Bus BG0 BR0
Controller C0 Controller C2 Controller C3 IO C4
Processor

Independent request and grant

 Independent bus request method

⚫ Controller separate BR signals, BR0, BR1,

…, BRn.
⚫ Separate BG signals, BG0, BG1, …, BGn
for the controllers.
⚫ An ith controller sends BRi (i-th bus
request signal) and when it receives BGi (i-
th bus grant signal), it uses the bus and then
BUSY signal activates
 Independent bus request method

⚫ Any controller, which finds active BUSY,

does not send BR from it.
⚫ Independent bus request method advantage
is that the i-th controller can be
programmed to get the highest priority to
the bus and the priority of a controller can
be programmed dynamically
4. Polling method for Bus Sharing by Multiple
Processors or controllers
Processor Programmable
Priorities BR3
Bus
Controller BR2 Busy

Poll Count
BR1
Bus BR0
Controller C0 Controller C2 Controller C3 IO C4
Processor

Polling Method
Polling the Requesting Device Method

⚫ A poll counts value is sent to the controllers

and is incremented. Assume that there are 8
controllers. Three poll count signals p2, p1,
p0 successively change from 000, 001, …,
110, 111, 000, … If on count = i, a BR
signal is received then counts increment
stops, BG is sent.
 Polling the Requesting Device Method
⚫ Then BUSY activates when that controller becomes the bu
master. When BR deactivates then BG and BUSY also
deactivates and counts increment starts. Polling method
advantage is that the controller next to the current bus mas
gets the highest priority to the access the bus after the curr
bus master finishes the operations through the bus.