Problem 1

Problem 1
A computer uses a memory unit with 256K words of 32 bits each. A binary instruction
code is stored in one word of memory. The instruction has four parts: an indirect bit, an
operation code, a register code part to specify one of 64 registers, and an address part.

a. How many bits are there in the operation code, the register code part, and the address
part?

b. Draw the instruction word format and indicate the number of bits in each part?

c. How many bits are there in the data and address inputs of the memory?

Solution
256K words = 256 × 210 = 218 words
64 registers = 26 registers

a. Address: 18 bits
Register Code: 6 bits
Indirect Bit: 1 bit
Operation Code: 32 − 25 = 7 bits

I Opcode Register Code Address

b.
1 bit 7 bits 6 bits 18 bits

c. Data: 32 bits
Address: 18 bits

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Problem 2
The following control inputs are active in the bus in Fig. 5.4. For each case, specify the
register transfer that will be executed during the next clock transition.

S2 S1 S0 LD of Register Memory Adder

a. 1 1 1 IR Read -
b. 1 1 0 PC - -
c. 1 0 0 DR Write -
d. 0 0 0 AC - Add

Solution
a. IR ← M [AR]

b. P C ← T R

c. DR ← AC, M [AR] ← AC

d. AC ← AC + DR

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Problem 3
The following register transfers are to be executed in the system of Fig. 5.4. For each register,
specify (1) the binary value that must be applied to bus select inputs S2 , S1 , and S0 ; (2)
the register whose LD control input must be active (if any); (3) a memory read or write
operation (if needed); and (4) the operation in the adder and logic circuit (if any).

a. AR ← P C

b. IR ← M [AR]

c. M [AR] ← T R

d. AC ← DR, DR ← AC (done simultaneously)

Solution

S2 S1 S0 LD of Register Memory Operation

a. 0 1 0 AR - -
b. 1 1 1 IR Read -
c. 1 1 0 - Write -
d. 1 0 0 AC and DR - Transfer DR to AC

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Problem 4
Explain why each of following microoperations cannot be executed during a single clock pulse
in the system shown in Fig. 5.4. Specify a sequence of microoperations that will perform the
operation.

a. IR ← M [P C]

b. AC ← AC + T R

c. DR ← DR + AC (AC does not change)

Solution
a. P C cannot provide address to memory. Address must be transferred to AR first:
AR ← P C
IR ← M [AR]

b. Add operation must be done with DR. Transfer T R to DR first:

DR ← T R
AC ← AC + DR

c. Result of addition is transferred to AC (not DR). To save value of AC its content must
be stored temporary in DR (or TR):
AC ← DR, DR ← AC
AC ← AC + DR
AC ← DR, DR ← AC

Note: As a homework, solve c. without using DR. Instead, use TR.

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Problem 5
Consider the instrcution formats of basic computer shown in Fig. 5.5 and list of instructions
given in Table 5-2. For each of following 16-bit instructions, give the equivalent four-digit
hexadecimal code and explain what it is that the instruction is going to perform.

a. 0001 0000 0010 0100

b. 1011 0001 0010 0100

c. 0111 0000 0010 0000

Solution
a. (1024)16
ADD 024
ADD content of M [024] to AC

b. (B124)16
STA I 124
Store AC in M [M [124]]

c. (7020)16
INC
Increment AC

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Problem 6
The content of AC in the basic computer is hexadecimal A937 and the initial value of E is
1. Determine the contents of AC, E, P C, AR, and IR in hexadecimal after the execution of
the CLA instruction. Repeat 11 more times, starting from each one of the register-reference
instructions. The initial value of P C in hexadecimal 021. Fill the table below according to
the problem.

Solution

E AC PC AR IR
Initial 1 A937 021 – –
CLA 1 0000 022 800 7800
CLE 0 A937 022 400 7400
CMA 1 56C8 022 200 7200
CME 0 A937 022 100 7100
CIR 1 D49B 022 080 7080
CIL 1 526F 022 040 7040
INC 1 A938 022 020 7020
SPA 1 A937 022 010 7010
SNA 1 A937 023 008 7008
SZA 1 A937 022 004 7004
SZE 1 A937 022 002 7002
HLT 1 A937 022 001 7001

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Problem 7
An instruction at address 021 in the basic computer has I = 0, an operation code of the
AND instruction, and an address part equal to 083 (all numbers are in hexadecimal). The
memory word at address 083 contains the operand B8F2 and the content of AC is A937. Go
over the instruction cycle and determine the contents of the following registers at the end of
the execute phase: P C, AR, DR, AC, IR. Repeat the problem six more times starting with
an operation code of another-memory reference instruction. Fill the table below according
to the given information.

Solution

PC AR DR AC IR
Initial 021 – – A937 –
AND 022 083 B8F2 A832 0083
ADD 022 083 B8F2 6229 1083
LDA 022 083 B8F2 B8F2 2083
STA 022 083 – A937 3083
BUN 083 083 – A937 4083
BSA 084 084 – A937 5083
ISZ 022 083 B8F3 A937 6083

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Problem 8
Show the contents in hexadecimal of registers P C, AR, DR, IR, and SC of the basic
computer when ISZ instruction is fetched from memory and executed. The initial content
of P C 7FF. The content of memory at address 7FF is EA9F. The content of memory at
address A9F is 0C35. The content of memory at address C35 is FFFF. Fill the table below
according to given information. Show the contents of the registers (in hexadecimal format)
after the positive transition of each clock pulse.

PC AR DR IR SC
Initial 7FF – – – 0
T0 7FF 7FF – – 1
T1 800 7FF – EA9F 2
T2 800 A9F – EA9F 3
T3 800 C35 – EA9F 4
T4 800 C35 FFFF EA9F 5
T5 800 C35 0000 EA9F 6
T6 801 C35 0000 EA9F 0

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Problem 9
The content of P C in the basic computer is 3AF (all numbers are in hexadecimal). The
content of AC is 7EC3. The content of memory at address 3AF is 932E. The content of
memory at address 32E is 09AC. The content of memory at address 9AC is 8B9F. What
instructions will be fetched and executed? Is this direct or indirect addressing? What is the
effective address? Sketch the memory map and show the binary operation performed in the
AC when the instruction is executed. Give the contents of registers P C, AR, DR, AC, and
IR in hexadecimal and the values of E, I, and sequence counter SC in binary at the end of
instruction cycle.

Solution

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Problem 10
The register transfer statements for a register R and the memory in a computer are as follows
(the X’s are control functions that occur at random):

X3′ X1 : R ← M [AR] Read memory word into R

X1′ X2 : R ← AC Transfer AC to R
X1′ X3 : M [AR] ← R Write R to memory

The memory has data inputs, data outputs, address inputs, and control inputs to read and
write. Draw hardware implementation of R and the memory in block diagram form. Show
how the control functions X1 through X3 select the load control input of R, the select inputs
of multiplexers that you include in the diagram, and the read and write inputs of the memory.

Solution

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Problem 11
The operations to be performed with a flip-flop F (not used in the basic computer) are
specified by the following register transfer statements:

xT3 : F ← 1 Set F to 1
yT1 : F ← 0 Set F to 0
zT2 : F ← F Complement F
wT5 : F ← G Transfer value of G to F

Otherwise, the content of F must not change. Draw the logic diagram showing the con-
nections of the gates that form the control functions and the inputs of flip-flop F . Use JK
flip-flop and minimize the number of gates.

Solution
J = xT3 + zT2 + wT5 G
K = yT1 + zT2 + wT5 G′

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Problem 12
Derive the control gates associated with the program counter P C in basic computer.

Solution
ZDR = 1 if DR = 0
ZAC = 0 if AC = 0

Look at P C ← P C + 1:
INR(P C) = R′ T1 + RT2 + D6 T6 ZDR + pB9 (F GI) + pB8 (F GO) + rB4 AC(15) + rB3 AC(15) +
rB2 ZAC + rB1 E ′

Look at P C ← xx:
LD(P C) = D4 T4 + D5 T5

Look at P C ← 0:
CLR(P C) = RT1

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Problem 13
Derive the control gates for the write input of the memory in the basic computer.

Solution
Look at M [AR] ← xx:
Write = RT1 + D3 T4 + D5 T4 + D6 T6

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Problem 14
Show the complete logic of the interrupt flip-flops R in the basic computer. Use JK flip-flop
and minimize the number of the gates.

Solution
J = (T0 + T1 + T2 )′ (IEN )(F GI + F GO)
K = RT2

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Problem 15
Derive the Boolean expression for the gate structure that clears the sequence counter SC to
0. Draw the logic diagram of the gates and show how the output is connected to INR and
CLR inputs of SC. Minimize the number of the gates.

Solution
CLR(SC) = RT2 + D0 T5 + D1 T5 + D2 T5 + D3 T4 + D4 T4 + D5 T5 + D6 T6 + D7 I ′ T3 + D7 IT3
= RT2 + T5 (D0 + D1 + D2 + D5 ) + T4 (D3 + D4 ) + D6 T6 + D7 T2 (I + I ′ )
= RT2 + T5 (D0 + D1 + D2 + D5 ) + T4 (D3 + D4 ) + D6 T6 + D7 T2

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Bidirectional Shift Register :)
Suppose A0 A1 A2 A3 = 1110, both serial inputs are 1 and all parallel inputs are 0.

a-) Determine the values and operation of S1 S0 .

b-) What will be the values of A0 A1 A2 A3 when the values of S1 S0 are 10, 01, 00, 11, 10
accordingly.

Solution

a-) b-)
S1 S0 Operation S1 S0 A0 A1 A2 A3
00 Parallel Load Initial 1110
01 Hold 10 1111
10 Shift Right with Serial Input 01 1111
11 Shift Left with Serial Input 00 0000
11 0001
10 1000

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Question Related to Three State Buffers (Homework)
Draw a diagram of a bus system similar to following image, but use three-state buffers and
decoder instead of multiplexers.

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Solution

Solution

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