MICROPROCESSORS (ENEX 201)

Tribhuvan University — Institute of Engineering

Exam Preparation Guide — 2082 Chaitra
Full Marks: 60 | Pass Marks: 24 | Time: 3 hrs | Programme: BEI, BCT

1. Most Frequently Asked Topics (2063–2081

Analysis)
Based on analysis of all past papers from 2063 to 2081 Chaitra:
Count Topic Priority

28× 8085 Assembly Language Programming VERY HIGH

26× 8086 Assembly Language Programming VERY HIGH

24× Memory Interfacing / Address Decoding VERY HIGH

22× Interrupts in 8085 and 8086 VERY HIGH

20× 8085 Architecture / Pin Signals HIGH

18× Stored Program Concept / Von Neumann HIGH

Architecture

18× 8086 Architecture (BIU, EU, Segmented Memory) HIGH

17× Timing Diagrams / Machine Cycles HIGH

17× Addressing Modes (8085 and 8086) HIGH

16× RISC vs CISC Architecture MEDIUM

15× PPI 8255A / Parallel Interface MEDIUM

14× Assembly Directives / Assembler Types MEDIUM

12× Serial Interface / RS-232 / USART MEDIUM

11× Flynn's Classification / Parallelism MEDIUM

10× Deadlock / OS Features MEDIUM

2. Chapter-wise Study Guide
Chapter 1: Introduction (4 hrs → ~6 marks)
Must Read Topics:
• Stored program concept — definition and significance
• Von Neumann architecture — components and data flow
• Processing cycle: Fetch → Decode → Execute (with RTL)
• Harvard architecture vs Von Neumann (differences)
• Bus organization of computer system
• RTL (Register Transfer Language) — how to write RTL for 8085 instructions
Tip: Do not skip RTL — it appears in almost every paper as a sub-question.

Chapter 2: Intel 8085 Microprocessor (12 hrs → ~15 marks)

Must Read Topics:
• Internal architecture — all blocks (ALU, registers, control unit, bus interface)
• Programming model — all registers with purpose
• All 5 flags: Sign, Zero, Auxiliary Carry, Parity, Carry — with examples
• Addressing modes: Immediate, Register, Direct, Indirect, Implicit
• Key instructions: PUSH, POP, CALL, RET, SIM, RIM, DAA, XTHL, PCHL
• ALP: conditional data transfer with bit-checking (D-bit patterns)
• ALP: counting elements (greater than X, less than Y)
• ALP: sorting (ascending and descending)
• ALP: BCD-binary conversion, multiplication/division without MUL instruction
• Machine cycles: Opcode fetch, Memory read/write, I/O read/write
• Timing diagrams: LDA, STA, MVI, OUT, IN — with T-state count
• Time calculation from clock frequency
• Pin signals: ALE, HOLD, HLDA, READY, IO/M, WR, RD, INTA, RESET
Tip: Two questions will come from Ch2 guaranteed. Master ALP with bit-checking — it appears almost
every year.

Chapter 3: Intel 8086 Microprocessor (14 hrs → ~18 marks)

Must Read Topics:
• BIU components: IP, CS/DS/SS/ES segment registers, instruction queue
• EU components: ALU, general-purpose registers (AX/BX/CX/DX and sub-registers)
• Pipelining in 8086 — how BIU prefetches while EU executes
• Segmented memory: physical address = segment × 16 + offset
• Flags of 8086: CF, PF, AF, ZF, SF, OF (status) + TF, IF, DF (control)
• Addressing modes of 8086: immediate, register, direct, register indirect, based, indexed, based
indexed, string
• Assembly directives: DB, DW, DD, EQU, ASSUME, SEGMENT, ENDS, PROC, ENDP, MACRO, ENDM
• Reserved words, identifiers, statements structure
• INT 21H services: AH=01 (char input), AH=02 (char output), AH=09 (string output), AH=0A
(string input), AH=4CH (exit)
• INT 10H services: AH=02 (set cursor), AH=06 (scroll/clear), AH=09 (write char with attribute)
• ALP: vowel/consonant counting from a string
• ALP: uppercase/lowercase conversion
• ALP: password validation
• ALP: display with color (background + text attributes)
• One-pass vs two-pass assembler
• EXE vs COM program differences
• Assembling → Linking → Execution process
Tip: Highest marks chapter. STRING processing ALP with INT 21H and INT 10H is essential. Know the
color attribute byte (background × 16 + foreground).

Chapter 4: Microprocessor System (7 hrs → ~12 marks)

Must Read Topics:
• Address decoding — why needed, unique vs non-unique
• 3:8 decoder (74LS138) — pin description and usage
• Memory interfacing design: ROM + RAM with base address — full address table
• I/O address decoding with NAND gates and block decoders
• Memory mapped I/O vs I/O mapped I/O
• PPI 8255A block diagram and three modes:
• Mode 0: Basic I/O (simple input/output)
• Mode 1: Strobed I/O (single handshaking)
• Mode 2: Bidirectional bus (double handshaking)
• Control word format of 8255A
• Parallel interface modes: simple, wait, single handshaking, double handshaking
• Serial interface: synchronous vs asynchronous transmission
• RS-232 standard: DTE, DCE, signal levels, handshaking signals
• USART — brief overview
Tip: Memory interfacing with 74LS138 is 100% guaranteed. Always draw the address table showing
which address bits go to which decoder input/output.

Chapter 5: Interrupt Operations (5 hrs → ~6 marks)

Must Read Topics:
• Interrupt types: hardware vs software, maskable vs non-maskable, vectored vs polled
• 8085 interrupt pins (in priority order):
• TRAP: non-maskable, vectored, highest priority, address 0024H
• RST 7.5: maskable, vectored, address 003CH
• RST 6.5: maskable, vectored, address 0034H
• RST 5.5: maskable, vectored, address 002CH
• INTR: maskable, non-vectored, lowest priority
• SIM instruction: Set Interrupt Mask — format and usage
• RIM instruction: Read Interrupt Mask — format and usage
• EI, DI instructions
• INTR pin handling: requires 8259 PIC or RST instruction on data bus
• ISR (Interrupt Service Routine) concept
• Interrupt processing cycle steps in 8085
• 8086 IVT (Interrupt Vector Table): structure at 0000H–03FFH
• Each vector entry: 4 bytes (IP low, IP high, CS low, CS high)
• 8086 interrupt processing sequence
Tip: Know the exact memory addresses of each RST interrupt. Priority order and maskable/non-
maskable distinction is always tested.

Chapter 6: Advanced Topics (3 hrs → ~3 marks)

Must Read Topics:
• RISC vs CISC: instruction set, addressing modes, execution cycles, pipelining, compiler
dependency
• Accumulator-based vs register-based architecture
• Hardwired vs microprogrammed control unit
• Flynn's classification: SISD, SIMD, MISD, MIMD with examples
• Deadlock: definition, 4 necessary conditions (mutual exclusion, hold and wait, no preemption,
circular wait)
• DSP features (brief)
Tip: Quick review only — 3-4 marks. Prepare short 4-point answers for each topic.
3. Predicted Questions — 2082 Chaitra
Based on pattern analysis of all past papers. HIGH = appeared in 80%+ of years.

Q1 (~6 marks) — Introduction / Architecture [HIGH]

Most likely: Define stored program concept. Explain briefly about Von Neumann Architecture. [2+4]
Alternative: Differentiate microprocessor and microcontroller. Write RTL for instruction LXI B, 2050H. [2+4]
Note: Appeared as Q1 in virtually every year. 2081 Chaitra (both old and new course) asked this exact
pattern.

Q2 (~7 marks) — 8085 Architecture and Addressing Modes [HIGH]

Most likely: Define addressing mode. Explain briefly about different types of addressing modes in
8085 with suitable example. [2+5]
Alternative: Draw programming model of 8085 and explain each unit. OR Explain flags of 8085 with arithmetic
examples.
Note: Addressing modes of 8085 appeared in 90%+ of all papers. New course 2081 asked exactly this
pattern.

Q3 (~6 marks) — 8085 Assembly Language Program [HIGH]

Most likely: Write a program in 8085 to transfer 8-bit numbers from one table to another by setting
bit D5 if the number is less than 50H, else transfer by resetting bit D6. [6]
Alternative: ALP to count elements greater than 40H and less than 50H. OR ALP to sort 10 bytes in descending
order. OR conditional transfer checking D7=0 and D3=1.
Note: Conditional data transfer with D-bit checking is THE most repeated ALP topic. Appeared in 2081,
2080, 2079, 2078 and many more years.

Q4 (~9 marks) — 8086 Architecture [HIGH]

Most likely: Explain 8086 microprocessor with its internal architecture. Explain flags in 8086
microprocessor. [6+3]
Alternative: What are BIU and EU in 8086? How is pipelining implemented? Explain segmented memory.
[3+2+3]
Note: 2081 new course asked full architecture + flags [6+3]. 2081 old course asked
BIU/EU/pipelining/segmented memory. Both patterns valid.

Q5 (~6 marks) — 8086 Assembly Language Program [HIGH]

Most likely: Write an Assembly Language Program in 8086 to read a string from user, count the
number of vowels and consonants and display the counts with color attribute. [6]
Alternative: ALP to display 'Programming is Fun'. OR ALP for password validation. OR ALP to convert string to
uppercase/lowercase and display.
Note: String-based ALP (vowels/consonants) appeared in 2081, 2080, 2079, 2078, 2077 — nearly every
year. Master INT 21H and INT 10H.

Q6 (~6 marks) — PPI 8255A / Parallel Interface OR Timing Diagram [MEDIUM]

Most likely: Explain in brief about 8255A PPI with its block diagram. [6] OR Explain parallel interface
and its modes of operation. Draw timing diagram for instruction DCR M. [4+4]
Alternative: Draw timing diagram for OUT xxH and calculate time. OR Explain modes of parallel data transfer.
Note: 2081 new course asked 8255A PPI [6]. 2081 old course asked parallel interface + timing diagram.
Both patterns likely.
Q7 (~6 marks) — Memory Interfacing / Address Decoding [HIGH]
Most likely: Design an address decoding circuit to interface one 2K×8 ROM chip, one 2K×8 RAM chip
and one 4K×8 EPROM chip with 8085 microprocessor consecutively starting from memory location
A000H. [6]
Alternative: Interface 4KB ROM + 2KB RAM starting at C000H using 3:8 decoder. OR Interface ROM + RAM +
EPROM at given base address.
Note: Memory interfacing design appeared in EVERY single paper without exception. Draw address table
showing A15–A0 allocation for full marks.

Q8 (~6 marks) — Interrupts in 8085 [HIGH]

Most likely: What is an interrupt? Explain about the interrupt processing in 8085. [2+4]
Alternative: Explain different interrupt pins of 8085 (vectored/maskable/priority). How is INTR pin used? [4+2]
OR Explain SIM and RIM instructions.
Note: Interrupt topic appeared in all papers. Know all 5 interrupt pins, their addresses, priority, and
maskable/non-maskable status.

Q9 (~4 marks) — RISC vs CISC Architecture [HIGH]

Most likely: Differentiate between RISC and CISC architecture. [4]
Alternative: Compare accumulator-based and register-based architecture. [4] OR Flynn's classification. [4]
Note: RISC/CISC appeared in nearly every paper. New course syllabus explicitly includes it. Prepare a
comparison table with 6–8 points.

Q10 (~4 marks) — Accumulator vs Register Architecture / Short Notes [MEDIUM]

Most likely: Compare and contrast between accumulator based and register based architecture. [4]
Alternative: Short notes on any two: IVT of 8086, CISC, Deadlock, Flynn's Classification, DMA Controller.
Note: 2081 new course asked exactly accumulator vs register-based [4]. Deadlock and Flynn's alternate
frequently as short notes.
4. Key Assembly Language Programs to Prepare
8085 Programs:
• Conditional data transfer with D-bit checking:
Transfer data from T1 to T2 based on specific bit conditions (D7, D3, etc.). This is the single most
repeated ALP topic.
• Counting elements in range:
Count numbers greater than 40H and less than 50H. Store count at a memory location.
• Sorting (ascending/descending):
Sort 10 data bytes using bubble sort. Know both ascending and descending versions.
• Largest and smallest:
Find largest and smallest from a block of N bytes. Store at specified locations.
• Odd/even separation:
Test each number and store even numbers separately.
• Upper/lower nibble operations:
Add upper and lower nibble of each byte, store result.
• BCD to binary conversion:
Convert BCD numbers stored in memory to binary.
• Multiplication without MUL:
Multiply two 8-bit numbers using repeated addition.
• Count 1s in upper nibble:
Count the number of 1 bits in the upper nibble across N bytes.

8086 Programs:
• Vowel and consonant counting with color display:
Read string using INT 21H (AH=0Ah), scan each character, count vowels (a,e,i,o,u — both cases)
and consonants, display counts using INT 10H with color attribute (e.g., green background = 20H,
blue text = 01H → attribute byte = 21H).
• Password validation:
Read password string, compare with stored string character by character, display 'Valid' or
'Invalid' message.
• Uppercase/lowercase conversion:
Read string, convert to opposite case using ASCII manipulation (A=65, a=97, difference=32).
• Display 'Programming is Fun':
Simple string output using INT 21H (AH=09H). The string must end with '$'.
• Largest and smallest in 16-bit array:
Find max and min from 10 sixteen-bit values using CMP and conditional jumps.
• String display with formatting:
Display each word on separate line, center-align, or convert case for each word.
5. Memory Interfacing Design — Quick Reference
Step-by-step approach for interfacing question (guaranteed in exam):
Step 1: Find base address in binary (16 bits). E.g., A000H = 1010 0000 0000 0000
Step 2: Determine chip size to find how many address lines the chip needs. 2K = 11 lines (A0–A10), 4K
= 12 lines (A0–A11)
Step 3: Remaining higher address lines go to the 74LS138 decoder inputs
Step 4: Draw the 74LS138 decoder: A, B, C inputs from address lines; G1=VCC, G2A=G2B=IO/M (low
for memory select)
Step 5: Connect each chip select (CE) to a decoder output (Y0, Y1, Y2...)
Step 6: Create address table: show exact address range for each chip
Step 7: Connect data lines D0–D7 to the bus; connect RD/WR to OE/WE of chips

Common chip sizes:

2K×8 = 2048 bytes, needs 11 address lines (A0–A10). Common chips: 2732 (EPROM), 6116 (RAM)
4K×8 = 4096 bytes, needs 12 address lines (A0–A11). Common chips: 2732 (EPROM variant), 6264
8K×8 = 8192 bytes, needs 13 address lines (A0–A12). Common chips: 6264 (RAM)

6. 8085 Interrupt Pins — Quick Reference Table

Pin Priority Maskable? Vectored? Vector Address Type

TRAP 1 (Highest) No Yes 0024H Hardware, NMI

RST 7.5 2 Yes Yes 003CH Hardware, edge-

triggered

RST 6.5 3 Yes Yes 0034H Hardware, level-

triggered

RST 5.5 4 Yes Yes 002CH Hardware, level-

triggered

INTR 5 (Lowest) Yes No External Hardware, non-

vectored

7. RISC vs CISC — Comparison Table

Feature RISC CISC

Instruction set Small, simple Large, complex

Instruction size Fixed (32-bit) Variable

Execution cycles 1 cycle per instruction Multiple cycles

Addressing modes Few (3–5) Many (12–24)

Registers Many (32+) Few (8–16)

Pipelining Easy to pipeline Difficult to pipeline

Memory access Only LOAD/STORE Many memory instructions

Control unit Hardwired Microprogrammed

Compiler Complex compiler needed Simpler compiler

Examples ARM, MIPS, SPARC Intel 8086, x86

8. Final Exam Tips

• Memory interfacing + 8085 ALP + 8086 ALP = 18+ marks. Master these three first.
• For ALP questions, always comment your code (using ';') — it shows understanding and earns
partial marks.
• For timing diagrams, count T-states carefully: opcode fetch = 4T, memory read/write = 3T, I/O =
3T.
• For address decoding, always draw and label the 74LS138 chip diagram — do not just write the
address table.
• For 8086 programs, always include model, stack segment, data segment, and code segment
declarations.
• INT 21H AH=09H requires string to end with '$'. INT 21H AH=0AH requires buffer with max
length byte first.
• Color attribute byte = background_color × 16 + foreground_color. Green bg + blue text = 2×16 + 1
= 33 = 21H.
• TRAP is the only non-maskable hardware interrupt in 8085. All others can be masked via SIM
instruction.
• Physical address in 8086 = Segment Register × 10H + Offset Register.
• Pass marks is 24 out of 60 — focus on scoring full marks in the topics you know well, not partial
marks in all.

Best of luck for your examination!