Chapter: I 16 Bit Microprocessor: 8086

1. List out any eight features of 8086. ii.

Address lines are unidirectional whereas data
1) It is a 16 bit Microprocessor. lines are bidirectional.
2) It has 16 bit data lines. (D0-D15) iii. AD0-AD7 lines carry lower order byte of address
3) It has 20 bit address lines. (A0-A19) & data and AD8-AD15, carry higher order byte of
4) It has multiplexed address and data bus AD0- AD15 address & data
to minimize the pins. iv. First they carry lower order 16 bit address, then
5) It provides 14, 16-bit registers. they carry 16 bit data.
6) The instruction set is powerful & flexible.  A19/S6, A18/S5, A17/S4, A16/S3:
7) Provides separate instructions for string
manipulation.
8) Operating clock frequencies 5 MHz, 8 MHz, 10 MHz
9) Arithmetic operations can be performed on 8 bit or
16 bit signed and unsigned data including
multiplication and division.
10) Operate in maximum and minimum mode to achieve
high performance level.
11) It provides 6 bytes instruction queue for pipelining.
i. These are multiplexed address and status lines.
12) It provides 256 types of vectored interrupts. ii. Address lines are unidirectional.
iii. First these lines carry upper four bit address &
2. Draw neat labeled Pin diagram of 8086. then they carry status lines.
iv. S3 & S4 carry status, indicating which segment
register is presently being used for memory
accesses.
v. S5 gives the status of interrupt flags.
vi. S6 will always be Zero.
 RD-Read:
RD is active low read signal given by processor to
indicate that the processor is performing read
operation with memory or I/O device depending on
the status.
 READY:
i. It is an active high input signal.
ii. This is the acknowledgement from the slow
devices or memory that they have completed or
ready for the data transfer (Operation).
iii. When high, it indicates that the peripheral
devices are ready to transfer data.
 INTR-interrupt Request:
i. This signal is active high, input interrupt
signal.
ii. If any interrupt request is occurred, the
processor enters the interrupt acknowledge
cycle.
iii. This can be internally masked by resetting the
interrupt enable flag.
iv. This is checked during the last clock cycle of
each instruction to determine the availability of
3. State functions of all pins of 8086. ((List and explain the request.
(separately) min & max) explain the functions of  TEST:
minimum mode pins.) i. This input is examined by a 'WAIT'
 AD15-AD0: instruction.
i. These are the multiplexed address and data lines.

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 ii. If the TEST input goes low, execution will  ALE-Address latch Enable:
continue, else, the processor remains in an idle i. This output signal indicates the availability of the
state. valid address on the address/data lines (AD0-
iii. The input is synchronized internally during AD15).
each clock cycle on leading edge of clock. ii. It is connected to latch enable input of latch
 NMI-Non-maskable Interrupt: 8282.
i. This is an edge-triggered input interrupt Request  WR- Write:
which causes a Type2 interrupt. i. It is an active low signal.
ii. The NMI is not maskable internally by software. ii. It indicates that the processor is performing a
 RESET: write memory or I/O operation depending on the
i. It is a system reset, active high signal. status of M/IO.
ii. It restarts execution when the RESET returns low.  DT /R -Data Transmit/Receive:
iii. This input causes the processor to terminate the i. This output is used to decide the direction of data
current activity and start execution from FFFF0H. flow through the transreceivers.
iv. The signal must be active for at least four clock ii. When the processor sends out data, this signal is
cycles. high and when the processor is receiving data,
 CLK-Clock Input: this signal is low.
i. The clock input provides the basic timing for  DEN-Data Enable:
processor operation and bus control activity. i. This signal indicates the availability of valid data
ii. The range of frequency for different 8086 over the address/data lines.
versions is from 5MHz to 10MHz. ii. It is used to enable the transreceivers
 GND, VCC: (bidirectional buffers) to separate the data lines
i. Vcc is +5V power supply for the operation of the from the multiplexed address/data signal.
internal circuit.  HOLD:
ii. GND ground for the internal circuit. i. When the HOLD line goes high, it indicates to
 MN/MX: the processor that another device is requesting
This pin decides whether the processor is to operate the bus access.
in either minimum (single processor) or maximum ii. The processor, after receiving the HOLD request,
(multiprocessor) mode. issues the hold acknowledge signal on HLDA
pin, in the middle of the next clock cycle after
 BHE/S7:-Bus High Enable/Status: completing the current bus (instruction) cycle.
i. BHE/S7 is a time multiplexed line. iii. When the processor detects the HOLD line low,
ii. BHE is low during T1; the status information is it lowers the HLDA signal.
available during T2, T3 and T4.  HLDA-Hold Acknowledge:
iii. The bus high enable signal is used to indicate the i. It is an active high signal.
transfer of data over the higher order (D15-D8) ii. The processor, after receiving the HOLD request,
data. issues the hold acknowledge signal on HLDA pin.
iv. It goes low for the data transfers over D15-D8.
The following pin functions are applicable for
The following pin functions are for the minimum maximum mode operation of 8086.
mode operation of 8086. S2 S1 S0 Status
 M/IO -Memory/IO:
0 0 0 Interrupt Acknowledge
i. This is an output status signal used to give
0 0 1 Read I/O Port
information of operation to be performed with
0 1 0 Write I/O Port
memory or I/O devices.
ii. When it is low, it indicates the CPU is having an 0 1 1 Halt
I/O operation, and when it is high, it indicates 1 0 0 Code Access
that the CPU is having a memory operation. 1 0 1 Read memory
1 1 0 Write memory
 INTA -Interrupt Acknowledge: 1 1 1 Passive
i. It is active low output signal.
ii. When it goes low, it indicates that the processor  S2, S1, S0 -Status Lines:
has accepted the interrupt. i. These are the status lines which indicate the type of
iii. When processor receives INTR signal, the operation being carried out by the processor.
processor completes current operation and ii. The list of status are given in the table.
acknowledges the interrupt by generating this
signal.

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 iii. These become active during T4 of the previous  QS1, QS0-Queue Status:
cycle and remain active during T1 and T2 of the i. These lines give information about the status of
QS1 QS0 Status the instruction queue.
0 0 No operation ii. These are encoded as in the table.
0 1 First byte of opcode from the queue  RQ/GT0, RQ/GT1-ReQuest/Grant:
i. These pins are used by other local bus devices, in
1 0 Empty queue
maximum mode, to force the processor to release
1 1 Subsequent byte from the queue the local bus at the end of the processor's current
current bus cycle. bus cycle.
 LOCK: ii. Each of the pins are bidirectional with RQ/GT0
i. This output pin indicates that other system bus having higher priority than RQ/ GT1.
devices will be prevented from gaining the system iii. After receiving request on these lines, the CPU
bus, while the LOCK signal is low. sends acknowledge signal on same lines.
ii. The LOCK signal is activated by the 'LOCK' prefix
instruction and remains active until the completion
of the next instruction.
4. Draw neat labeled Architecture of 8086 with all signals.

5. List out various blocks of BIU of 8086. State their 1. Segment Registers:
functions. (Describe the main blocks in BIU and EU/  There are 4 16-bit segment registers.
Describe MP 8086 in details.) a) Code segment (CS):-
 Bus Interface Unit (BIU):  It is a 16-bit register containing address
i. The BIU sends out address, fetches the instructions code segment.
from memory, read data from ports and memory,  It is used for addressing a memory location
and writes the data to ports and memory, generating in the code segment of the memory, where
the control signals and calculating the addresses of the executable program is stored.
the memory operands.
ii. In other words the BIU handles all transfers of data b) Stack segment (SS):-
and addresses on the buses for the execution unit.  It is a 16-bit register containing address of
stack segment.
iii. Various blocks of BIU are given below:

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  It is used for addressing stack segment of  AL can be used as 8 bit accumulator for 8
memory. bit operation.
c) Data segment (DS):-  It is the most important general purpose
 It is a 16-bit register containing address of register having multiple functions.
data segment. b) BX (Base Register):
 It is used for addressing the data segment  This register is mainly used as a base
memory where the data is stored. register.
d) Extra segment (ES):-  For memory related instructions BX is used
 It is a 16-bit register containing address of to store 16 bit effective address of the
extra segment. corresponding memory locations.
 It is used for addressing extra segment  It holds the starting base location of a
which contains another data of the memory. memory region within a data segment.
2. Instruction Pointer:-  It is used as offset storage for forming
 It holds the 16-bit address of next instruction physical address.
within the code segment. c) CX (Counter/ count Register):
 The value stored in IP is called offset or It is used as default counter or count register
displacement. in case of string and loop instructions.
3. Instruction Queue: d) DX(Data register):
 To increase the execution speed BIU fetches as  If the result of multiplication is more than
many as six instruction bytes ahead to time from 16 bit, then the lower order 16 bit are stored
memory. in AX and higher order16 bit are stored in
 All six byte registers are then held in FIFO six DX.
bytes registers called Instruction Queue.  It is used to store 16-bit port address during
certain I/O instruction.
6. Describe the register organization of 8086 MP. (List 3) Pointer Register (SP-Stack Pointer & BP-
all 16 bit registers of 8086. / List and explain general Base Pointer):
purpose registers of 8086 MP.)  The other registers in EU are SP, BP i.e.
 Execution Unit (EU): Stack Pointer & Base Pointer which is
i. The execution unit (EU) of the 8086 tells the BIU called Pointer Register.
where to fetch instructions or data from, decodes  Stack Pointer (SP) is a 16-bit register
instructions and executes instruction. pointing to program stack in stack segment.
ii. The Execution unit is responsible for decoding and
 Base Pointer (BP) is a 16-bit register
executing all instructions. pointing to data in stack segment.
iii. The EU contains control circuitry to perform
 Base Pointer register is usually used for
various internal operations.
based, indexed or register indirect
iv. It consists of 8 general purpose registers, two 16-
addressing to hold 16-bit offset within the
bit pointer registers, 16-bit ALU and flag registers.
particular instructions.
4) Index Register (SI- Source Index & DI-
1. ALU (Arithmetic and logical Unit):-
Destination Index):
 ALU is 16 bit, hence called 16-bit MP.
 The 8086 MP has two 16-bit index registers
 The ALU is responsible to perform all as SI & DI.
arithmetic and logical operations.
 These are particularly used for string
2. General purpose Register:
manipulation.
 EU has 8 general purpose registers as AH, AL,
 SI is a 16-bit register generally used to store
BH, BL, CH, CL, DH, DL.
the offset of source data or string in data
 These registers can be used as 8-bit registers segment.
individually for 8-bit operations, for 16-bit
 Destination Index (DI) is a 16-bit register
operations they can be used in pairs as AH-AL,
used to store the offset of destination in data
BH-BL, CH-CL, DH-DL.
or extra segment.
 The: AH-AL Referred as AX
 SI & DI are used in indexed, based indexed
BH-BL Referred as BX
and register indirect addressing
CH-CL Referred as CX
DH-DL Referred as DX
7. What is queue? How does queue speeds up
a) AX (Accumulator):
processing of 8086 MP?
 AX is a 16-bit accumulator, with lower 8-
bit of AX designed as AL and upper 8 bit of  Queue:
AX designed as AH.

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 i. The BI Unit fetches six instruction bytes ahead of - This flag is used to indicate the parity of
time from memory and are then stored in registers result.
in FIFO manner, this group of registers is called - Set, if lower order 8-bits of the result contains
Queue. even number of 1’s, the Parity Flag is set and
ii. While BIO fetches instruction byte, the EU for odd number of 1’s, the Parity flag is reset.
executes the previously decoded instruction f) Carry(C) flag:
- Set, if carry/borrow is generated in result.
simultaneously.
Else it is reset.
iii. Hence, it is quite faster than sending the address to
the memory & waiting for the memory to send II. Control Flags:-
back the next instruction byte. i. Control flags are set or reset by the programmer
iv. In this way, the Queue speeds up the processing of to control the operations of the execution unit.
8086. ii. Control flags are as follows:
a) Direction Flag (DF):
8. Draw flag register format and explain in brief - It is used in string operation.
various flags related to 8086. (List and explain - If it is set, string bytes are accessed from higher
control flags of 8086 MP. List instructions related to memory address to lower memory address.
control flags.) - When it is reset, the string bytes are accessed
from lower memory address to higher memory
address.
b) Interrupt Flag (IF):
- It is an interrupt enable/disable flag.
- If it is set, the maskable interrupt of 8086 is
enabled and if it is reset, the interrupt is
disabled.
- It can be set by executing instruction STI and
can be cleared by executing CLI instruction.
c) Trap Flag (TF):
- It is used for single step control.
- It allows user to execute one instruction of a program
at a time for debugging.
i. Flag register is a 16-bit register containing 9 one - When trap flag is set, program can be run in single
bit flags. step mode.
ii. A flag is set/reset to indicate some conditions
produced after the execution of an instruction 9. What is memory segmentation? How memory
operation in ALU. segmentation is achieved in 8086 MP.
iii. The flag register consist of status as well as I. Memory segmentation:-
control flags. i. The total memory size is divided into segments
I. Conditional Flags of various sizes.
Conditional flags are as follows: ii. A segment is just an area in memory.
a) Overflow Flag (OF) – iii. The process of dividing memory this way is
- Set, if the result is too large positive number, called Segmentation.
or is too small negative number to fit into iv. The memory in 8086 based system is organized
destination operand. Else it is reset. as segmented memory.
b) Sign Flag (SF): v. Each segment is 64KB in size and addressed by
- Set, if the result of operation is negative. one of the segment register.
Otherwise it is reset. vi. The 4 segment register in BIU hold the 16-bit
c) Zero Flag (ZF): starting address of 4 segments.
- Set, if the result of arithmetic or logical a) Code segment (CS):-
operation is zero. Else it is reset. i. It is a 64 KB segment with processor
instructions.
ii. The processor uses CS segment for all accesses
d) Auxiliary Flag (AC): to instructions referenced by instruction pointer
- Set, if carry is generated by bit d3. Else it is (IP) register.
reset. iii. It is used to store the executable program.
e) Parity Flag (PF):

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 b) Stack segment (SS):- - Physical address generation:-
i. It is a 64KB segment with program stack. i. In 8086, memory has four different types of
ii. By default, the processor assumes that all data segments.
referenced by the stack pointer (SP) and base ii. Each register stores the base address (starting
pointer (BP) registers is located in the stack address) of the corresponding segment.
segment. iii. These registers are 16-bit in size.
iii. The stack segment is that segment of memory, iv. But the physical addresses are 20 bit, so the
which is used to store stack data. segment registers stores only the upper 16 bits
iv. Stack segment contains the addresses of address.
procedures, interrupts etc. v. To convert this 16-bit address into 20-bit, the
BIU appends 0H to the LSBs of the address.
c) Data segment (DS):- vi. To calculate the Physical Address of the
i. It is a 64KB segment with program data. memory, BIU uses the following formula:
ii. By default, the processor assumes that all data Physical Address = Base Address + Effective
referenced by general registers (AX, BX, CX, Address or Offset
and DX) and index register (SI, DI) is located in
the data segment. 12. Explain the concept of pipelining. How it helps in
iii. Data segment contains the program data. improving system throughput.
- Pipelining:-
d) Extra segment (ES):- i. In 8086, pipelining is the technique of
i. It is a 64KB segment, usually with program overlapping instruction fetch and execution
data. mechanism.
ii. By default, the processor assumes that the DI ii. To speed up program execution, the BIU
register references the ES segment in string fetches as many as six instruction bytes ahead
manipulation instructions. of time from memory.
iii. It also refers to segment which essentially is iii. While executing one instruction other
another data segment of the memory. instruction can be fetched. Thus it avoids the
iv. It also contains data. waiting time for execution unit to receive other
instruction.
10. List diff advantages of segmentation. iv. The BIU can be fetching instructions bytes
I. Advantages of segmentation:- while the EU is decoding an instruction or
a) Programs and data can be stored separately executing an instruction which does not require
from each other in segmentation. use of the buses.
b) With the use of segmentation the instruction v. When the EU is ready for its next instruction, it
and data is never overlapped. simply reads the instruction from the queue in
c) Segmentation can be used in multi-user time the BIU.
shared system. vi. This is much faster than sending the address to
d) Segmentation allows two processes to share the memory and waiting for memory to send
data. back the next instruction byte or bytes.
11. Define physical and effective address. Describe 20 bit vii. This improves overall speed of the processor.
physical address generation process in 8086.
Calculate physical address by taking DS, CS, and IP. 13. State the advantages of pipelined architecture.
a) Physical address:- - Advantages of pipelined architecture:-
i. Each memory location has 20 bit address which i. It speeds the execution.
is called its physical address. ii. It helps in improving system output.
ii. The physical address is the combination of base iii. More efficient use of processor
address and effective address. iv. Large number of instructions can be executed in
quick amount of time.
b) Effective address:- v. This results in efficient use of the system bus
i. The address associated with any instruction or and system performance.
data type is only 16-bit called as effective or
offset or displacement address.

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 14. Diff between Minimum and Maximum modes of 8086 MP.

Minimum Mode Maximum Mode
MN/MX* pin is connected to Vcc i.e. MN/MX* pin is connected to ground i.e. MN/MX*
1
MN/MX* = 1 =0
Single MP in minimum mode system. Multiprocessor configuration in minimum mode
2
system.
Control signals M/IO*, RD*, WR* are directly Control signals M/IO*, RD*, WR* are not directly
3
available on 8086 MP. available on 8086 MP.
4 No separate bus controller is required. Separate bus controller (8288) is required.
Control signals such as IOR*, IOW*, MEMW*, Control signals such as IORC*, IOWC*, AIOWC*,
5 MEMR* can be generated using control signals MWTC*, AMWC*, MRDC* are generated by bus
M/IO*, RD*, WR*. controller 8288.
ALE, DEN*, DT/R* and INTA* signals are ALE, DEN*, DT/R* and INTA* signals are directly
6
directly available. available & are generated by bus controller 8288.
HOLD & HLDA signals are available to RQ*/GT0* & RQ*/DT1* signals are available to
7
interface another master in system. interface another master in system.
Status of the instruction queue is not available. Status of the instruction queue is available on pin
8 QS0 & QS1.

15. Diff between 8085 and 8086 MP.


8085 8086
1 It is 8-bit Microprocessor. It is 16-bit Microprocessor.
2 It has 16-bit address line. It has 20-bit address line.
3 It has 8-bit data bus. It has 16-bit data bus.
The speed is 3 MHz. The speed can vary between 5, 8, and 10MHz for
4
three different microprocessor.
Flag register is of 8-bit. Flag register is of 16-bit.
5
It has 5 flags. It has 9 flags.
6 It does not supports pipe-lining. It supports pipe-lining.
7 It does not supports memory segmentation. It supports memory segmentation.
8 It has 6500 transistors. It has 29000 transistors.
9 It has no minimum or maximum mode. It has minimum or maximum mode.
10 Only 64 KB memory is used together. 1 MB memory is used.
11 General purpose registers are of 8 bit size. General purpose registers are of 8 and 16 bit size.
It has five hardware interrupts, i.e. TRAP, RST It has only two hardware interrupts, i.e. NMI and
12
7.5, RST 6.5, RST 5.5 & INTR INTR
13 Instruction queue is not present. Instruction queue is present.

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