Module 1

Part 3- Basic Concepts

 Syllabus
Basic Concepts: Lexical Conventions, Data Types, System Tasks
and Compiler Directives

Digital Design Using Verilog HDL- 22ECE42

Objective
● Understand lexical conventions, comments,
whitespace
● Define logic value set and data types
● Identify useful system task for displaying and
monitoring information
● Learn Basic compiler directives
Digital Design Using Verilog HDL- 22ECE42
Lexical Conventions
● Basic lexical conventions are similar to C
programming language.
○ White space, comment, operator, number
specification, string, identifiers, keyword,
escaped identifier.
● case-sensitive language
○ keywords are in lowercase
Digital Design Using Verilog HDL- 22ECE42
 Whitespace

Blank space (\b) place anywhere [ignore]

Tabs (\t) White space separate token [not ignore]

Newlines (\n) place in string [not ignore]

Digital Design Using Verilog HDL- 22ECE42

Comment
◆ Single line : // a = b && c; // This is a one-line comment
/* This is a multiple
line comment */
◆ Multiple line: /*
/* This is /* an illegal */ comment */
………..
/* This is //a legal comment */
…………………... */

Digital Design Using Verilog HDL- 22ECE42

Operators
Type No. of Example
Operand
1
Unary a = ~b;

2
Binary a = b && c;

3
Digital Design Using Verilog HDL- 22ECE42
 Number Specification
● Sized numbers:
<size>’<base format><number>
0,1,2,3,.........d,e,f

Decimal Examples:
Binary ('b or 'B)
❏ 4'b1111 /* 4-bit binary
Decimal ('d or 'D)
Octal ('o or 'O) number*/
Hexadecimal ❏ 12'habc /* 12-bit
('h or 'H)
hexadecimal number*/
❏ 16'd255 /*16-bit decimal
Digital Design Using Verilog HDL- number*/
22ECE42
Number Specification
● Unsized numbers: ’<base format><number>

Decimal ('d or 'D)

Examples:

❏ 23456 // 32-bit decimal number by default

❏ 'hc3 // 32-bit hexadecimal number
❏ 'o21 // 32-bitDigital
octal number
Design Using Verilog HDL- 22ECE42
Number Specification

Digital Design Using Verilog HDL- 22ECE42

Number Specification
● X or Z values
◆ Unknown: x
◆ High impedance: z
Examples:
❏ 12’h13x = 0001_0011_xxxx // 12-bit hex number; 4 least
significant bits unknown
❏ 6’hx = xx_xxxx // 6-bit hex number
❏ 32’bz = zzzz_zzzz_..._zzzz // 32-bit high impedance
number Digital Design Using Verilog HDL- 22ECE42
 Number Specification
● Negative numbers
◆ A minus sign before the size for a constant number

8-bit for 2’s of 3

Examples: 0000 0011
❏ -8'd3 // 8-bit negative number stored as inverse
2's complement of 3 1111 1100
+1
1111 1101
❏ 4'd-2 // Illegal specification

Digital Design Using Verilog HDL- 22ECE42

 Number Specification
● Underscore characters and question marks
◆ "_" is allowed anywhere in a number except the first
character.
◆ "?" is the Verilog HDL alternative for z in the context of
numbers.

Examples:
❏ 12'b1111_0000_1010 // Use of underline characters
for readability
❏ 4'b10?? // Equivalent of a 4'b10zz
Digital Design Using Verilog HDL- 22ECE42
Strings

◆ Sequence of characters that are enclosed by double quotes

◆ String must be contained on a single line
◆ Strings are treated as a sequence of one-byte ASCII values

Examples:
❏ "Hello Verilog World" // 19 bytes
❏ "a / b" //5 bytes

Digital Design Using Verilog HDL- 22ECE42

 Identifiers and Keywords
● Keywords
◆ The special identifier ● The name of objects

reserved to define the ● alphanumeric characters, the

language constructs. underscore ( _ ), or the dollar sign ( $ )

● Identifiers are case sensitive

Examples:
● reg value; // reg is a keyword; value is an identifier
● input clk; // input is a keyword, clk is an identifier
Digital Design Using Verilog HDL- 22ECE42
● Identifiers and Keywords
Examples:

Digital Design Using Verilog HDL- 22ECE42

Escaped Identifiers

◆ Begins with the backslash ( \ ) character and end with

whitespace (space, tab, or newline).
◆ All characters between backslash and whitespace are
processed.
◆ Any printable ASCII character can be included in escaped
identifiers
Examples:
❏ \a+b-c
❏ \**my_name**
Digital Design Using Verilog HDL- 22ECE42
Data Types

Digital Design Using Verilog HDL- 22ECE42

Data Types
● Value set and strength
● Nets
● Registers
● Vectors
● Integer,Real and Time Register Data Types
● Arrays
● Memories
● Parameters
● Strings

Digital Design Using Verilog HDL- 22ECE42

 Value Set

Value Condition in Hardware Circuits

Logic zero, false condition

0

1 Logic one , true condition

Digital Design Using Verilog HDL- 22ECE42

Value Set
Value Condition in Hardware Circuits

Unknown logic value

x

z High impedance, floating state

Digital Design Using Verilog HDL- 22ECE42

Strength Level
Strength Level Type Strongest
supply Driving

strong Driving

pull Driving

large Storage

weak Driving

medium Storage

small Storage

highz High Impedance

Digital Design Using Verilog HDL- 22ECE42 Weakest
 Nets
● It represent connections between hardware elements
● Declares a physical wire
● Keywords: wire, wand, wor, tri, trior, trireg Example:
● Default value of a net: z wire a; // declare net a

wire b, c; /* declare two wires

b, c */
Wire
wire d = 1’b0; /* net d is fixed
to logic value 0*/
Continuously driven on

Digital Design Using Verilog HDL- 22ECE42

 Registers
Examples:
● Storage element for data reg reset; /* declare a variable reset
that can hold its value*/
● Not equal to “hardware initial
register” begin
reset = 1’b1;
● Keyword: reg #100 reset = 1’b0;
end
● Similar to variables in C
● Default value: x

Digital Design Using Verilog HDL- 22ECE42

 Vectors

● wire and register can be defined as “vector” form format

● [high#:low#] or [low#:high#]

Examples: Wire a
wire a;
wire [7:0] bus;
wire [31:0] busA, busB, busC;
reg clock;
reg [0:40] virtual_addr;
Digital Design Using Verilog HDL- 22ECE42
Vectors
● wire and register can be defined as “vector” form format
● [high#:low#] or [low#:high#]
Wire [7:0]bus

bus[7]
Examples:
wire a; 8
wire [7:0] bus;
wire [31:0] busA, busB, busC;
reg clock;
reg [0:40] virtual_addr; bus[0]

Digital Design Using Verilog HDL- 22ECE42

Vectors

● wire and register can be defined as “vector” form format

● [high#:low#] or [low#:high#]

32
busA
Examples:
wire a; 32
busB
wire [7:0] bus;
wire [31:0] busA, busB, busC; 32
busC
reg clock;
reg [0:40] virtual_addr;
Digital Design Using Verilog HDL- 22ECE42
 Vectors
● wire and register can be defined as “vector” form format
● [high#:low#] or [low#:high#]

Examples:
wire a;
wire [7:0] bus;
wire [31:0] busA, busB, busC;
reg clock; clock
reg [0:40] virtual_addr;
Digital Design Using Verilog HDL- 22ECE42
 Vectors
● wire and register can be defined as “vector” form format
● [high#:low#] or [low#:high#]

Examples:
wire a;
wire [7:0] bus;
wire [31:0] busA, busB, busC;
reg clock;
reg [0:40] virtual_addr;

0 1 2 3 4 5 6 . . . . . . . . . . 37 38 39 40

Digital Design Using Verilog HDL- 22ECE42

 Vectors

wire [31:0] busA, busB, busC;

busA[7] // bit # 7 of vector busA

31 30 29 28 . . . . . . . 8 7 6 5 4 3 2 1 0

busA[30];

Digital Design Using Verilog HDL- 22ECE42

 Vectors
wire [7:0] bus;
bus[2:0] // Three least significant bits of vector bus

7 6 5 4 3 2 1 0

bus[0:2] Illegal Since given vector MSB is 2 and LSB is 0

Digital Design Using Verilog HDL- 22ECE42

 Vector
reg [0:40] virtual_addr;
virtual_addr[0:1]

Two Most Significant Bits

0 1 2 3 4 5 6 . . . . . . . . . . 37 38 39 40

MSB LSB

Digital Design Using Verilog HDL- 22ECE42

 Variable Vector Part Selection
[<starting_bit>+:width] part-select increments from starting bit
Eg. starting_bit = 3, width = 4
[3+:4] =>
[3:6]
7 6 5 4 3 2 1 0

[<starting_bit>-:width] - part-select decrements from starting bit

[3-:4] =>
[3:0] 7 6 5 4 3 2 1 0

Digital Design Using Verilog HDL- 22ECE42

 Big-endian keeps the most
significant byte of a word at
Variable Vector Part Selection the smallest memory
location and the least
significant byte at the
reg [255:0] data1; //Little endian notation largest. On the other hand,
little-endian keeps the least
reg [0:255] data2; //Big endian notation significant address at the
reg [7:0] byte; smallest memory location.
byte = data1[31-:8]; starting bit = 31, width =8

255 254 ... ... 32 31 30 29 28 27 26 25 24 23 22 21 20 19 .. 1 0

Start End

data[31:24]
Digital Design Using Verilog HDL- 22ECE42
 Variable Vector Part Selection
reg [255:0] data1; //Little endian notation
reg [0:255] data2; //Big endian notation
reg [7:0] byte;
byte = data1[24+:8]; starting bit = 24, width =8

255 254 ... ... 32 31 30 29 28 27 26 25 24 23 22 21 20 19 .. 1 0

data[31:24]
Digital Design Using Verilog HDL- 22ECE42
 Variable Vector Part Selection
reg [255:0] data1; //Little endian notation
reg [0:255] data2; //Big endian notation
reg [7:0] byte;
byte = data2[31-:8]; starting bit = 31, width =8

0 1 2 3 ... 21 22 23 24 25 26 27 28 29 30 31 32 ... .. 254 255

data[24:31]
Digital Design Using Verilog HDL- 22ECE42
 Variable Vector Part Selection
reg [255:0] data1; //Little endian notation
reg [0:255] data2; //Big endian notation
reg [7:0] byte;
byte = data2[24+:8]; starting bit = 24, width =8

0 1 2 3 ... 21 22 23 24 25 26 27 28 29 30 31 32 ... .. 254 255

data[24:31]
Digital Design Using Verilog HDL- 22ECE42
 Variable part selection

starting bit can also be a variable

data1[(byteNum*8)+:8] = 8'b0;

If byteNum = 1, clear 8 bits [15:8]

Digital Design Using Verilog HDL- 22ECE42

 Variable part selection

reg [255:0] data1;

for (j=0; j<=31; j=j+1) J Data

byte = data1[(j*8)+:8]; 0 data1[7:0]

1 data1[15:8]

2 data1[23:16]

... ….

31 data1[255:248]

Digital Design Using Verilog HDL- 22ECE42

Register data types
Integer

Register
Real
data types

Time

Digital Design Using Verilog HDL- 22ECE42

 Integer

● General purpose register data type

Example:
● Keyword: integer integer counter;
initial
● Default width :32 bit Counter = -1;
● Used to store signed values compared …
...
to unsigned storage in reg

Digital Design Using Verilog HDL- 22ECE42

 Real Example:

● Keyword: real real delta; /* Define a real variable

● Can be specified in decimal notation called delta*/
or scientific notation initial
● Real data type cannot have range begin
declaration delta = 4e10; /* delta is
● Default value : 0 assigned in scientific notation*/
● Real values are rounded when delta = 2.13; /* delta is
assigned with integer type assigned a value 2.13*/
end
integer i;
initial
i=delta; /* i gets the value 2*/
Digital Design Using Verilog HDL- 22ECE42
 Time
● Store simulation time
Example:
● Keyword: time
● Special data type is used to store time save_sim_time; /* Define a
time
time variable save_sim_time*/
● Default width :64 bit initial
● $time is system function to invoke
save_sim_time = $time;
current simulation time
● Measured in terms of simulation
seconds (s)

Digital Design Using Verilog HDL- 22ECE42

 Arrays
● Allowed to work with reg, integer, time ,real , realtime and vector register data
types
● Multidimensional array can be declared with any number of dimension
● Array of nets can be used to connect ports
● Each element in an array can be used as scalar or vector
● Syntax: <data_type> <array_name>[<subscript>]
● [Number];
● Note: ● [start_index : stop _index];
○ Vector is a single element that is n-bit width.
○ Array is multiple elements that are n-bit width.
Digital Design Using Verilog HDL- 22ECE42
 Arrays
Example
● integer count[0:9]; /*an array of
10 count variable*/

● reg bool[31:0] /*array of 32 one

bit boolean register variable*/

Digital Design Using Verilog HDL- 22ECE42

 Arrays
Example
● reg [4:0] port [0:6]; /* array of 7 0
port each port is 5 bit wide*/
1

Digital Design Using Verilog HDL- 22ECE42

 Example

integer matrix [0:2][0:3];

● integer matrix [0:2][0:3];
//Two dimensional array

Digital Design Using Verilog HDL- 22ECE42

Example

Digital Design Using Verilog HDL- 22ECE42

 Memories
● Memories are one- dimensional array of registers.
● Each element of the array is known as element or word
○ Each word can be one or more bits

Examples:
● reg mem1bit[0:1023]; /* Memory mem1bit with
1K 1-bit words*/

Digital Design Using Verilog HDL- 22ECE42

 Memories

Examples:
● reg [7:0] membyte[0:1023]; /*
Memory membyte with 1K 8-bit
words(bytes) */
● membyte[511] /*Fetches 1 byte
word whose address is 511*/

Digital Design Using Verilog HDL- 22ECE42

 Parameters
● Define a constant in a module using the keyword parameter.
● Parameters cannot be used as variables
● Can be overridden individually at compile time

Examples:
parameter port_id = 5; // Defines a constant port_id
parameter cache_line_width = 256; // Constant defines width of cache line
parameter signed [15:0] WIDTH; /*Fixed sign and range for parameter
WIDTH */

Digital Design Using Verilog HDL- 22ECE42

 Parameter
● Parameter value can be changed using “defparam”
● Local parameters are identical to parameters except that they cannot be
directly modified with the defparam statement
● The localparam keyword is used to define parameters when their values
should not be changed.
● Example:
localparam state1 = 4'b0001,
state2 = 4'b0010,
state3 = 4'b0100,
state4 = 4'b1000;
Digital Design Using Verilog HDL- 22ECE42
 Strings

● Strings can be stored in reg

● Character in the string takes up 8 bits (1 byte).
● Width of the register variables must be large enough to hold the string
○ If the width of the register is greater than the size of the string, Verilog fills bits
to the left of the string with zeros.
○ If the register width is smaller than the string width, Verilog truncates the
leftmost bits of the string.

Digital Design Using Verilog HDL- 22ECE42

 Example:

module test_string;
reg [8*19:1] string_value;
initial
begin
string_value = “Hello Verilog World”; 0 0 0 1 1 1 1 1
#10 $display(“%s”, string_value);
end
endmodule
string value[8*19:1] H e l l o V e r i l o g W o r l d

string value [8*23:1] 0 0 0 0 H e l l o V e r i l o g W o r l d

l l o V e r i l o g W o r l d
string value[8*17:1]
Digital Design Using Verilog HDL- 22ECE42
Special Characters
Escaped Characters Character Displayed

\n newline

\t tab

%% %

\\ \

\" "

Character written in 1 - 3 octal

\ooo
digits
Digital Design Using Verilog HDL- 22ECE42
 System task and
Compiler directive

Digital Design Using Verilog HDL- 22ECE42

 System tasks

● Verilog provides standard system tasks for certain routine operations

● All system tasks appear in the form $<keyword>
◆ Displaying on the screen $display
◆ Monitoring values of nets $monitor
◆ Stopping the simulation $stop
◆ Finishing the simulation $finish

Digital Design Using Verilog HDL- 22ECE42

 System tasks
● Displaying information
○ System task for displaying values of variables or strings expressions.

● Usage: $display(p1, p2, p3,....., pn);

○ p1, p2, p3,..., pn can be quoted strings or variables or expressions
○ The format of $display is very similar to printf in C

Digital Design Using Verilog HDL- 22ECE42

Display Format
Format Display

%d or %D Display variable in decimal

%b or %B Display variable in binary

%s or %S Display string

%h or %H Display variable in hex

%c or %C Display ASCII character

%m or %M Display hierarchical name (no argument required)

%v or %V Display strength

%o or %O Display variable in octal

%t or %T Display in current time format

%e or %E Display real number in scientific format

%f or %F Display real number in decimal format

%g or %G Display real Digital

number Design Using Verilog
in scientific HDL- whichever
or decimal, 22ECE42 is shorter
 Example

$display("Hello Verilog World"); -- Hello Verilog World

$display($time); -- 230

reg [0:40] virtual_addr; -- At time 200 virtual address is

$display("At time %d virtual address is %h", 1fe0000001c
$time, virtual_addr);

reg [4:0] port_id; -- ID of the port is 00101

$display("ID of the port is %b", port_id);

Digital Design Using Verilog HDL- 22ECE42

 Example

reg [3:0] bus; -- Bus value is 10xx

$display("Bus value is %b", bus);

$display("This string is displayed from %m -- This string is displayed from

level of hierarchy"); top.p1 level of hierarchy

$display("This is a \n multiline string with a %% --This is a

sign"); -- multiline string with a % sign

Digital Design Using Verilog HDL- 22ECE42

● Monitoring information
○ Continuously monitors the values of variables or signals mentioned
in the parameter list and displays all the parameters in the list
whenever the value of any one of the variable or signal changes.
○ $monitor needs to be invoked only once.
○ More than one $monitor statement in your simulation, the last
$monitor statement will be the active statement

● Usage: $monitor(p1,p2,p3,....,pn);
○ p1, p2, ... , pn can be variables, signal names, or quoted strings

Digital Design Using Verilog HDL- 22ECE42

● Monitoring information
○ Two tasks are used to switch monitoring on and off.

● Usage:
○ $monitoron;
○ $monitoroff;
● The $monitoron tasks enables monitoring, and the $monitoroff task disables
monitoring during a simulation.
● Monitoring is turned on by default

Digital Design Using Verilog HDL- 22ECE42

 Example

initial
begin
$monitor($time," Value of signals clock = %b reset = %b", clock,reset);
end
initial clk = 1'b0;
always #5 clk = ~clk;

initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $finish;
end
Digital Design Using Verilog HDL- 22ECE42
 ● Stopping and finishing in a simulation

debug
● $stop: To suspend the simulation at a certain time
● $finish: To terminate the simulation at a certain time

Digital Design Using Verilog HDL- 22ECE42

● Stopping and finishing in a simulation

● $stop: Example:
○ Used to stop during a simulation initial begin
○ Usage: $stop; clock = 0;
● $finish : reset = 1;
○ Used to terminates the simulation #100 $stop; // This will suspend the
○ Usage: $finish; simulation at time = 100
#900 $finish; // This will terminate
the simulation at time = 1000
end

Digital Design Using Verilog HDL- 22ECE42

 Compiler Directives
● All compiler directives are defined by
using the `<keyword> construct
● `define
■ Directive is used to define text
macros in Verilog.
■ The Verilog compiler
substitutes the text of the
macro wherever it encounters a
`<macro_name>.
■ This is similar to the #define
construct in C

Digital Design Using Verilog HDL- 22ECE42

 Compiler Directives
Example for `define:

Digital Design Using Verilog HDL- 22ECE42

Compiler Directives
● `include
■ `include directive allows you to include entire contents of a Verilog
source file in another Verilog file during compilation
■ This is similar to the #include in C

Digital Design Using Verilog HDL- 22ECE42

Compiler Directives

Digital Design Using Verilog HDL- 22ECE42

 Summary

● Lexical conventions for operators, comments, whitespace, numbers,

strings, and identifiers were discussed
● Various data types are available in Verilog
● Verilog provides useful system tasks to do functions like displaying,
monitoring, suspending, and finishing a simulation
● Compiler directive `define is used to define text macros, and `include
is used to include other Verilog files.

Digital Design Using Verilog HDL- 22ECE42

Thank You

Digital Design Using Verilog HDL- 22ECE42