Module – 1 Introduction

Introduction: Need for low power VLSI chips, charging and discharging capacitance, short circuit current in
CMOS leakage current, static current, basic principles of low power design, low power figure of merits.
Simulation power analysis: SPICE circuit simulation, discrete transistor modeling and analysis, gate level
logic simulation, architecture level analysis, data correlation analysis in DSP systems, Monte Carlo simulation.
(Text 1)

Power: Power is the rate at which energy is delivered or exchanged.

Power Dissipation: The rate at which energy is taken from the source and converted into heat is the power
dissipation.
In a VLSI chip, electrical energy is converted to heat energy during operations.

Question 1
Explain the needs of low power VLSI design. (05 Marks)
Explain the needs for low power VLSI design. (04 Marks)
Discuss the need for low power VLSI design. (08 Marks)
Discuss the need of low power VLSI design. (05 Marks)
Explain the need for low power chips and the sources of power dissipation in digital CMOS. (08 Marks)
Discuss the need of low power VLSI design of also explain basic principles of low power design and low
power figure of merits principles (12 Marks)
Need for low power VLSI chips

Miniaturization and Moore's Law:

 As transistors shrink and more are packed onto a chip (Moore's Law), operating frequency and processing
power increase.
 This advancement also leads to higher power dissipation.

Portable Electronics and Battery Limitations:

 The demand for smaller, lighter, and longer-lasting portable devices necessitates low power consumption.
 Battery technology advancements haven't kept pace with miniaturization of electronics, limiting battery life.
 Increasing battery energy density raises safety concerns.

High-Performance Computing:

 High-power dissipation in high-performance systems creates challenges:

o Increased packaging costs for chips.
o Higher cooling system costs.
o Challenges in power supply design and noise immunity.

Environmental Concerns:

 The growing number of electronic devices contributes significantly to overall energy consumption.
 Inefficient power usage in electronics translates to increased air pollution from electricity generation.
Government regulations and programs like Energy Star promote energy-efficient computing, driving the need
for low-power VLSI design.

Low power chips and systems are driven by both business and technical needs.
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 Demand for low power chips is fueled by portable electronics market craving smaller, lighter, and durable
products.
 Battery technology struggles to keep pace with rapid advancements in electronic circuits, raising safety
concerns.
 High-performance computing systems with large power dissipation also drive the need for low power solutions.
 Power dissipation impacts chip packaging and cooling costs, with some CPUs requiring cooling fans directly on
chip carriers.
 Challenges arise from transient currents and digital noise immunity analysis in high-power chips.
 Environmental concerns drive demand for low power chips, as office automation equipment consumes
significant energy.
 Inefficient energy usage in computing equipment contributes to environmental pollution, prompting initiatives
like Energy Star certification.

Sources of power dissipation in digital CMOS:

1. Dynamic Power Dissipation: This type of power dissipation results from the switching activities of the
circuits. Higher operating frequencies lead to increased switching activities and consequently higher power
dissipation. The primary cause of dynamic power dissipation in CMOS circuits is the charging and
discharging of capacitance, primarily due to parasitic effects in interconnection wires and transistors.
 Switching Power: This is the dominant source of power dissipation in CMOS circuits. It occurs when the
transistors switch between their on and off states, charging and discharging parasitic capacitances associated
with the gates, interconnects, and load devices.

The power dissipation is proportional to the switching activity, the capacitance being switched, and the square
of the supply voltage. The formula for switching power is:

Where:

 α = Activity factor (percentage of time the node switches)

 CL = Load capacitance
 VDD = Supply voltage
 f = Clock frequency

 Short-Circuit Power: During the transition from one logic state to another, there's a brief period when
both the NMOS and PMOS transistors are partially on. This can lead to a direct path between the power
supply and ground, resulting in a short-circuit current flow and additional power dissipation.
This short-circuit current dissipates power, which is proportional to the rise/fall times of the input
signals.

 Glitching Power: Glitches are unwanted transient signals that can occur within a circuit due to
asynchronous switching or propagation delays. These glitches can cause additional charging and
discharging of capacitances, leading to power dissipation
2. Static Power Dissipation: Static power dissipation is related to the logical states of the circuits rather than
switching activities. In CMOS logic, leakage current is the main source of static power dissipation.
However, deviations from strict CMOS logic can also cause static current to be drawn occasionally.

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  Subthreshold Leakage: Even when a MOSFET is turned off (when the gate-source voltage is less than
the threshold voltage), there can still be a small amount of current that flows from drain to source, known as
subthreshold leakage. This leakage increases with reduced threshold voltage and higher temperatures.

 Gate Leakage: Due to the shrinking size of

transistors, the oxide layer between the gate and
channel becomes very thin, allowing tunneling current
to flow through the gate even when the transistor is off.
This is gate oxide leakage.

 Reverse-Biased Junction Leakage: Leakage can

also occur at the reverse-biased p-n junctions (e.g.,
source/drain to substrate), contributing to the overall
static power dissipation.

3. Parasitic Capacitance: Parasitic capacitance, resulting from the interconnection wires and transistors, is a
significant source of dynamic power dissipation in CMOS circuits. While some capacitors may be intentionally
fabricated for non-digital operations, most digital CMOS circuits rely on parasitic capacitance. Estimating and
analyzing parasitic capacitance is crucial for both signal delay and power dissipation analysis.

Question 2
With the usual notation derive the expression for dynamic power dissipation in an inverter circuit. (08
Marks)
Derive an equation for total power dissipation in terms of capacitance and switching frequency using
charging and discharging a capacitor. (10 Marks)
Derive the expression for power dissipation in CMOS circuit due to charging and discharging of
capacitance. (07 Marks)
Note: The most significant source of dynamic power dissipation in CMOS circuits is the charging and
discharging of capacitance.

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 Figure 1.1 illustrates the equivalent circuit for charging and discharging the output capacitance of a CMOS
logic gate, using a switch to model the cycles. In the circuit, V represents an ideal constant voltage source, and
Rc (Rd) represents the resistance of the charging (discharging) circuitry, which can be intentional or parasitic.

According to the laws of physics, the voltage vc(t) and the current ic(t) of a capacitance CL at time t are given
by:

 vc(t): The voltage across the capacitor at time t.

 ic(t): The current flowing into or out of the capacitor at time t.

These quantities are determined by the charging and discharging processes, influenced by the voltage source
and the resistances in the circuitry.

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Equation (1.7) is the most important power dissipation equation in digital VLSI chip design. It relates power
dissipation to a few quantities that are readily observable and measurable in VLSI circuits. The equation is easy
to compute, and more important, it is applicable to almost every digital CMOS circuit because only a few mild
assumptions have been used in the derivation.
The discussion reviews the generality and applicability of the equation P=CLV2f by examining its derivation
procedure. It highlights that during the charging process, CLV2 energy is drawn from the energy source. Half of
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this energy is dissipated in the charging resistance Rc, while the other half is stored in the capacitor. Conversely,
during discharge, the energy stored in the capacitor is dissipated as heat in the discharging resistor Rd. This
observation underscores the balance of energy transfer and dissipation within the circuit, leading to the
formulation of the power dissipation equation.
few assumptions are made in our derivation:
1. The capacitance C L is constant.
2. The voltage V is constant.
3. The capacitor is fully charged and discharged, i.e., vc(to) = 0, vc(t1) = V, v c(t2) = 0.

The result is independent of the charging and discharging circuitry Rc, Rd ; the length of charging and
discharging cycle to, t1, t2 ; the voltage or current waveform v c(t), ic(t), etc. Furthermore, Rc, Rd can be
nonlinear, time varying resistance (such as a transistor) and the above derivation is still valid as long as the
three assumptions are satisfied.
Most CMOS digital circuits that we design today satisfy the three assumptions above when their
capacitances are charged and discharged during logic operations.

For most CMOS circuits operating at medium to high frequency, this is the prevailing mode of power
dissipation.
Equation (1.7) is only the power dissipation caused by a single capacitor CL . In general, the total power
should be summed over each capacitance Ci in a circuit yielding

where Vi is the voltage swing across the capacitor Ci switching at frequency fi. For CMOS circuits, V is
typically the same for all capacitance Ci . One simple approximation is to assume that fi is constant, for
example, by taking the average of all fi 's. This allows us to write

in which Ctotal is the sum of all capacitance, I is the average frequency and V is the voltage swing.

In today's typical CMOS process with minimum feature size of 0.I8-0.5um, typical values of Ci are in the order
of 0.005pF to 1pF. The charging and discharging frequency can be as high as several hundred MHz, with V at
several volts.

Question 3
A 32 bit off chip bus operating at 5 V and 55 MHz clock rate is driving a capacitance of 20pF/bit. Each
bit is estimated to have a toggling probability of 0.25 at each clock cycle. What is the power dissipation in
operating the bus? (04 Marks)
C = bits * C = 32* 20pF/bit = 640pF
V = 5V
f =toggling probability X clock rate = 0.25* 55MHz =13.75MHz

P= 640pF * 52*13.75MHz= 220mW

Question 4
A 128 bit NOC operating at 1.2 V and 250 MHz clock rate is driving a capacitance of size 10mm X
50mm . (Assume NOC router has length of the clock, which is estimated to be thrice the circumference of
the chip) with metal layer width of 0.6µm and parasitic capacitance of the metal layer is 0.5 fF/mm 2. Each
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bit is estimated to have a toggling probability of 0.25 at each clock cycle. What is the power dissipation in
operating the bus? (04 Marks)
f – femto – 10-15
Circumferences rectangle = 2(l+w) = 2(10mm+50mm)
C = 3*2 (10mm +50mm) * metal layer width* parasitic capacitance
C= 6(60mm)*0.6 µm* 0.5 fF/mm2 = 216 µm*0.5 fF/mm = 108µ*1000mmfF/mm = 108mfF =0.108fF
V= 1.2V
f = toggling probability X clock rate = 0.25*250MHz = 62.5MHz
p=cv2f = 0.108f* 1.22* 62.5M = 9.72nW

Question 5 – Note: power dissipation also caused by signal switching called short-circuit power.
Derive the equation for the short circuit power dissipation in a CMOS inverter supporting with diagrams
and explanation. (12 Marks)
Discuss short circuit power dissipation in CMOS inverter and hence derive with usual notation

How to minimize this power dissipation? (12 Marks)

Question 6
Mathematically discuss the leakage current in a MOS transistors. (10 Marks)
Leakage current exists as a natural phenomenon of the semiconductor device operation.
Leakage is a form of current that is generally not intended for the normal operation of a digital circuit.
There are two major sources of leakage current:
1. Reverse biased PN-junction current
2. Subthreshold channel conduction current.

Reverse Biased PN-junction:

The first source of leakage current occurs when the source or drain of an N-transistor (P-transistor) is at Vdd
(Gnd}. PN-junctions are formed at the source or drain of transistors because of a parasitic effect of the bulk
CMOS device structure. As shown in Figure 1.7, the junction current at the source or drain of the transistor is
picked up through the bulk or well contact. The magnitude of the current depends on the temperature, process,
bias voltage and the area of the PN-junction. Analysis of the semiconductor physics shows that the reverse
biased PN-junction current is

The current Is is the reverse saturation current dependent on the fabrication process and the PN-junction area.
The variable Vth, which often appears in leakage equations, is called the thermal voltage where

In the above equation, k = 1.38 x 10-23Joule/K is the Boltzmann's constant, q = 1.60 X 10-19C is the electronic
charge and T is the device operating temperature. At room temperature, T = 300K and Vth = 25.9mV.

Note that Equation (1.11) is applied when V is negative, i.e., the PN-junction is in reversed bias. If IVI >> V th ,
we have ev IV, = 0 and Ireverse = Is' Thus, a small reverse voltage is sufficient to induce current saturation. For
all practical purposes, the current is largely independent of the circuit operating voltage.

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The saturation current Is is highly dependent on the temperature. As a rule of thumb, the saturation
current Is doubles for every ten-degree increase in temperature.

To summarize, the reverse biased PN-junction current is largely independent of operating voltage but
depends on the fabrication process, junction area and temperature. Generally, the leakage current is not a
problem for most chips and there is very little one can do to reduce this current in a large scale digital design.

Subthreshold Channel Leakage

Discuss the fundamental physical mechanisms of power dissipation in digital CMOS VLSI circuits. (10 Marks)

Explain the basic principles of low power design. (04 Marks)

Discuss basic principles of low power design. (10 Marks)
Explain the different design techniques and methodologies for low power VLSI design. (06 Marks)
Conservation and trade-off are the philosophy behind most low power techniques.
Conservation school of thought aims to save energy by identifying and eliminating unnecessary or inefficient
uses of power. The design skills required are in identifying, analyzing and preventing waste.
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intimate understanding of the design specification, operating environment and intuition acquired from past
design experience are keys to creative low power techniques.
Low power considerations should be applied at all levels of design abstraction and design activities.
1. Reduce Switching Voltage

 The dynamic power dissipation in digital chips is mainly determined by voltage, capacitance, and
frequency (P = CV²f), with voltage having the greatest impact due to its quadratic effect. Lowering the
operating voltage of CMOS circuits is an effective way to save power. Other techniques include
reducing voltage swing using methods like charge sharing and adjusting transistor threshold voltage.
 However, reducing voltage has trade-offs. Performance decreases as transistors slow down at lower
voltages, and threshold voltages can't scale down easily without increasing leakage current.
Additionally, low voltage swings reduce noise immunity, requiring special level converters for
interfacing signals.

2. Reduce Capacitance:
 Reducing parasitic capacitance can improve performance and power consumption in digital design.
However, it is important to reduce the product of capacitance and switching frequency, not just
the capacitance itself. Signals with high switching frequencies should have minimal parasitic
capacitance to conserve power, while nodes with large capacitance should avoid high-frequency
switching.

 Capacitance reduction can be achieved at various design levels, including material selection, process
technology, physical design (like floorplanning, placement, and routing), circuit techniques, transistor
sizing, logic optimization, architecture changes, and alternative algorithms.

3. Reduce Switching Frequency

 To reduce power dissipation, lowering the switching frequency has a similar effect as reducing
capacitance. This technique is most effective for signals with large capacitance and is commonly
applied at the logic design level and above, where the impact is greater.

 Techniques for reducing switching frequency can be applied at various design levels, with higher-level
techniques generally having greater impact.
 Reducing switching frequency can also improve chip reliability, as some failure mechanisms are tied to
high switching frequencies.
 One key method is eliminating unnecessary logic switching that is not necessary for computation.
Other approaches involve alternate logic implementations, such as using different coding methods,
number systems, counting sequences, and data representations, which can change the switching
frequency of a design.

4. Reduce Leakage and Static Current

 Leakage current, such as reverse biased junction or subthreshold current, is generally not beneficial in
digital design, but designers have limited control over it. Fortunately, leakage power in CMOS circuits
is much smaller than dynamic power. However, it becomes a concern in low-frequency circuits or

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 those with "sleep modes," where dynamic activity is minimal. Most leakage reduction techniques are
applied at low-level design, such as process, device, and circuit design.
 Memory chips that have very high device density are most susceptible to high leakage power.
 Static current can be reduced through transistor sizing, layout techniques, and careful circuit design.
Unused circuit modules should be turned off, and signal polarity can be reversed to minimize static
current flow.

Low power figure of merits principles:

To measure the power efficiency of a chip or system, several units of measure and figures of merit are used,
with no single measure being universally applicable. Here are the important points:

1. Power in Watts is the most straightforward measure, useful for determining the total power
consumption, packaging, cooling, and peak power needs. However, it becomes less useful when
measuring power efficiency, especially for higher-frequency chips.
2. Energy in Joules or μW/MHz is often used to measure energy dissipation per clock cycle, representing
power efficiency. Lower values are better since they indicate less energy is required for the same
computational task.
3. μW/MIPS or mA/MIPS measures energy consumption per instruction, which is useful for comparing
processors of different architectures. It normalizes power consumption with respect to performance
(MIPS = millions of instructions per second).
4. Limitations of μW/MIPS: It can be misleading when comparing processors with different architectures
(e.g., RISC vs. CISC) since different architectures require varying numbers of instructions to complete
the same task.
5. SPEC-based measures (μW/SPEC): SPEC is a more comprehensive performance rating based on
standardized benchmarks, useful for comparing processors that perform different tasks.
6. Energy-Delay Product (EDP): This is another common measure, especially for logic styles, that
factors in both energy consumption and computation delay.
7. Battery life in mA-Hour: For portable electronics, measures that involve battery lifetime (like mA-
Hour) are important for assessing energy efficiency.
8. No single measure is sufficient: Different figures of merit are used depending on the analysis and
application, and it’s up to the designer to choose the right metric for each situation.

No Single Perfect Measure:

 There is no universally ideal figure of merit for power efficiency.

 Designers must carefully select the appropriate measure based on their specific needs and goals.

 Watt: Absolute measure of power consumption.

 Joule: Measure of energy.
 uW/MHz: Energy dissipation per clock cycle.
 uW/MIPS: Energy consumed by a typical instruction.
 uW/SPEC: Energy consumed by a typical instruction (based on SPEC benchmarks).
 uW/MIPS^2 or uW/SPEC^2: Emphasizes performance rating over power dissipation.

Simulation Power Analysis

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  Simulation at a lower-level design abstraction offers better accuracy at the expense of increased
computer resource.
 Circuit simulators such as SPICE attain excellent accuracy but cannot be applied to full chip analysis.
 Logic simulation generally can handle full-chip analysis but the accuracy is not as good and
sometimes the execution speed is too slow.
 Behavioral-level or functional-level simulation offers rapid analysis but the accuracy is sacrificed.

Since no single simulation technique is applicable to all levels of design, the top down estimation, refinement
and verification methodology is used.

SPICE (Simulation Program with IC Emphasis) is the de facto power analysis tool at the circuit level.
SPICE Simulation basics:
 KCL-based: SPICE solves nodal currents using Kirchhoff's Current Law.
 Basic Components: Resistors, capacitors, inductors, current sources, and voltage sources are fundamental
elements.
 Complex Models: Diodes and transistors are built from these basic components.
 Circuit Analysis: SPICE calculates voltage, current, charge, and power dissipation with high precision.
 Transient Analysis: This mode is most useful for digital IC power analysis, simulating circuit behavior over
time.

Device Models

 Characterization: Device models are derived from physical measurements.

 Parameters: Models are described by numerous parameters.
 Calibration: Calibration with test chips ensures high accuracy.
 Lower-Level Tools: Finite Element Methods can be used to generate device model parameters.

SPICE Power Analysis:

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SPICE Advantages:

 Accuracy: SPICE is highly accurate, even capturing low-level phenomena.

 Versatility: It can handle various power analysis types (dynamic, static, leakage) and components
(MOS, bipolar, diodes, resistors, inductors, capacitors).
 Modeling: Specialized components can be created using SPICE's modeling capabilities.

Limitations:

 Computational Resources: SPICE is resource-intensive, limiting its use for large circuits.
 Device Models: Accuracy depends on the quality of device models, which can be challenging to obtain.
 Process Variation: Fabrication variations can affect SPICE accuracy.

Addressing Process Variation:

 Extreme Case Analysis: Simulating with different device models (TYPICAL, BEST, WORST) helps
account for variations.
 Device Speed: Faster devices often have higher power dissipation, but exceptions exist.
 Marginal Power Budgets: Thorough analysis across extreme cases is crucial for designs with limited
power.
 Bottom-Up Characterization: Process variation is a common issue in this approach, and SPICE is
particularly sensitive to it.

Discrete Transistor Modeling and Analysis:

In SPICE, a transistor is modeled with a set of basic components using mathematical equations. The solution of
the node currents and voltages requires complex numerical analysis involving matrix operations. Equation (2.1)
gives a simple SPICE transistor model to compute Ids as a function of Vgs and V ds ' The model is obtained by
the first order approximation of the nonlinear equation at the operating point Vgso and Vdso

to form a linear approximation equation. In the small signal model, the equation can be simplified as

which leads to the model shown in Figure 2.2. The linear equation has to be numerically evaluated in SPICE
whenever the operating point Vgso and V dso changes, resulting in excessive computation requirements.

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Tabular Transistor Model:

Tabular Transistor Models

 Speedup: Replacing equation evaluation with table lookups accelerates computation.

To speed up computation in circuit analysis, transistor models can be expressed in tabular form and
stored in a database. Instead of evaluating equations for each transistor, a simple table lookup is used
based on pre-calculated values of current (Ids) for given voltages (Vgs and Vds). This method requires a
one-time SPICE simulation to generate the lookup tables for various transistor sizes.

 Characterization: SPICE simulations are used to generate lookup tables.

 Event-Driven Approach: This method improves efficiency by focusing on significant voltage changes.

Circuit-level analysis tools based on these tabular models are primarily designed for timing and power analysis
of digital circuits. They use an event-driven approach, where a calculation is triggered only when there is a
significant voltage change in the circuit. If this approach fails, the system reverts to traditional circuit analysis
methods similar to SPICE.

 DC Convergence: Using logic values from primary inputs helps address convergence issues in large
circuits.

Trade-offs:

 Accuracy: Quantization introduces inaccuracies, but it's generally tolerable for digital circuits.
 Scale: While faster than SPICE, transistor-level tools may still struggle with very large chips.

Overall:

 Tabular transistor models offer a significant speedup compared to SPICE, but they come at the cost of
some accuracy.
 These tools are suitable for timing and power analysis of digital circuits, but their effectiveness may be
limited for extremely large chips.

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While using tabular models improves computation speed—up to two orders of magnitude faster than SPICE—it
introduces some inaccuracies, which are usually acceptable for digital circuits.

 Speed up computation
 The system was mainly designed for timing an power analysis of digital circuits.
 It applies the event-driven approach, in which an event is registered when significant change in node
voltage occurs.
 DC convergence problem

Switch Level Analysis:

 Most digital circuit analysis focuses on basic components like transistors, capacitors, and resistors. To
improve computation speed and memory usage without much loss in accuracy, higher-level abstraction
models, such as switch-level simulation, are used.
 In switch-level simulation, a transistor is modeled as a simple on-off switch with a resistor.
 The transistor turns on when the gate voltage exceeds the threshold voltage, and timing simulation is
done using an approximate RC (resistance-capacitance) calculation, which is more efficient than
transistor-level analysis.
 Switch-level simulation is a higher-level abstraction that can improve computational efficiency without
sacrificing much accuracy for digital circuit analysis.
 By representing transistors as switches, timing analysis can be performed using simpler RC calculations.
 Power analysis can be estimated based on the switching activity and node capacitances.
short-circuit power by observing when a power-ground path forms.
Although switch-level analysis is less accurate than circuit-level analysis, it offers significantly faster simulation
speed.

Question
Explain the techniques to obtain the
i) Capacitive power
ii) Internal switching power
iii) Static state power. (08 Marks)
Briefly discuss Gate – level logic simulation approach. (07 Marks)
Discuss the terms capacitive power dissipation, internal switching energy and static state
power with respect to gate level logic simulation. (08 Marks)
The basic principle of such tools is to perform a logic simulation of the gate-level circuit to obtain the
switching activity information. The information is then used to derive the power dissipation of the circuit.
 Maturity: A well-established technique in VLSI design.
 Component Abstraction: Focuses on logic gates, nets, and basic circuit elements.
 Logic Behavior: Simulates the behavior of components like NAND gates, latches, and flip-flops.
 Software Availability: Numerous gate-level logic simulators exist, capable of handling large-scale circuits.
 Full-Chip Simulation: Can simulate chips with millions of gates.

Gate-level Logic Simulation

|- Basics of Gate-level Analysis
|- Capacitive Power Dissipation
|- Internal Switching Energy
|- Static State Power
|- Gate-level Capacitance Estimation
|- Gate-level Power Analysis
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Basics of Gate-level Analysis
Gate-level analysis typically uses event-driven logic simulation, where events are logic switches (like 0 to 1)
that occur at specific times in the circuit. When an input event happens at a gate, it triggers an output event after
a delay. This method provides accurate pre-fabrication logic analysis and verification of digital chips.
Simulators often support additional logic states like "unknown," "don't care," and "high-impedance" to simulate
real-world scenarios more realistically. Verilog and VHDL are common languages for gate-level design.

Cycle-based simulators are a newer approach, assuming circuits are driven by synchronous clocks. They limit
the number of events per clock cycle, making the analysis more efficient by reducing the total events to
simulate.

To speed up gate-level simulations, hardware acceleration is used, where special hardware (like graphic
coprocessors) optimizes logic simulation, leading to faster performance. Hardware emulation is another
advanced technology, partitioning logic networks into smaller sub-blocks and implementing them using RAM
or FPGAs. This allows circuits up to a million gates to be emulated, providing near-real-time simulation at
speeds much faster than traditional software-based simulators, although it is costly to maintain.

Acceleration Techniques

 Hardware Acceleration: Specialized hardware can significantly speed up simulation.

 Hardware Emulation: Replaces software simulation with hardware implementation for dramatic
speedup.

Capacitive Power Dissipation:

 Gate-level power analysis offers a straightforward and efficient way to estimate power consumption in
digital circuits.
 The ability to accurately calculate the P=CV2f equation is a key advantage over other methods.
 In contrast to analog simulations (like SPICE), where node frequencies aren't well-defined due to non-
periodic and non-digital waveforms,
 In logic simulation, the switching activities of each node can be monitored to determine its frequency.
The power dissipated due to charging and discharging capacitors can be easily computed.

Each net i of a gate-level circuit is associated with a capacitance Ci and a counter variable ti . As simulation
progresses, a logic switching at net i increments the counter ti. At the end of the simulation, the frequency of net
i is given by fi = t/(2D where T is the simulation time elapsed. The capacitive power dissipation of the circuit is

 Pre-Layout Estimation: Can estimate Ci capacitance and power before physical layout.
 Post-Layout Accuracy: Layout extraction tools provide accurate capacitance values.
 Quick Estimation: Provides a rapid assessment of chip power dissipation.
 By combining logic simulation with capacitance estimation, designers can obtain valuable insights
into power consumption at various stages of the design process.

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Internal Switching Energy:

If a node appears inside a logic cell, its switching activities are not accounted because the logic-level abstraction
does not define internal nodes.
Short circuit power is also not captured by the equation 2.3.

The dynamic power dissipated inside the logic cell is called internal power, which consists of short-circuit
power and charging/discharging of internal nodes.

The energy dissipation events in a gate, such as a NAND gate, are tied to specific logic transitions that cause
dynamic energy consumption. This energy dissipation occurs when internal nodes are charged or discharged, or
when short-circuit currents flow during switching events.
Dynamic Energy Dissipation Events: These are triggered by changes in the gate's inputs. For example, in a 4-
transistor NAND gate, the event "A = 1, B switches from 0 to 1" leads to the output switching from 1 to 0,
consuming dynamic energy internally.
Sources of Energy Dissipation: This energy results from short-circuit current and charging/discharging
internal nodes during input transitions.
The dynamic energy dissipation event can be easily observed during logic simulation.
The computation of dynamic internal power uses the concept of logic events. Each gate has a pre-defined set of
logic events in which a quantum of energy is consumed for each event.
For example, a simple 4-transistor NAND gate has four dynamic energy dissipation events as shown in Figure
2.3(b).

This energy accounts for the short-circuit current and charging or discharging of internal nodes of the gate.
The computation is repeated for all events of all gates in the circuit to obtain the total dynamic internal power
dissipation as follows.

E(g, e) is the energy of the event e of gate g obtained from logic gate characterization and f(g, e) is the
occurrence frequency of the event on the gate observed from logic simulation.

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The parameter E(g, e) depends on many factors: Factors Affecting Event Energy:

 Process Conditions: Manufacturing variations influence energy consumption.

 Operating Conditions: Voltage, temperature, and output load affect energy.
 Input Signal Slopes: Rising and falling times of input signals impact energy dissipation.
 Gate Implementation: Different circuit structures can have varying numbers of energy events.

Static State Power:

 the power dissipation depends on the state of the logic gate.
 For example, a two-input NAND gate has four distinct states, as shown in

 The transistors operate in different modes and thus the static leakage power of the gate is different.
 The leakage power is primarily determined by the subthreshold and reverse biased leakage of MOS
transistors.
 During logic simulation, we observe the gate for a period T and record the fraction of time T(g, s)/T in
which a gate g stays in a particular state s.

In the above equation, p(g, s) is the static power dissipation of gate g at state s obtained from characterization.
The state duration T(g, s) is obtained from logic simulation. It is the total time the gate g stays at state s.
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The static power p(g, s) depends on process conditions, operating voltage, temperature, etc.

Gate-level Capacitance Estimation:

Capacitance significantly affects power dissipation, delays, and signal slopes in CMOS circuits.
Accurate capacitance estimation is crucial for power analysis and optimization.
Capacitance Impact on Power: Capacitance is crucial for power dissipation in CMOS circuits, directly
affecting delays, signal slopes, and power dissipation (dynamic and short-circuit current).

Types of Parasitic Capacitance:

 Device Parasitic Capacitance: This includes capacitance at the transistor's gate, source, and drain,
influenced by factors like oxide thickness and transistor dimensions (width, length, shape).
 Wiring Capacitance: This is based on wire characteristics (layer, area, shape), and process parameters
like wire thickness, substrate distance, and width.

Factors Affecting Capacitance

 Device: Gate oxide thickness, gate dimensions, diffusion region size.

 Wiring: Wire layer, width, length, and distance from substrate.

Capacitance Measurement:

 Pin Capacitance: Pin capacitance of a cell can be measured using SPICE simulations, based on the
current-voltage relationship i=C⋅dv/dt

We vary the pin voltage ΔV of the cell in time Δt and observe the current i to obtain the capacitance C. This
measurement can be performed during the characterization of the cell.

 Wiring Capacitance: This is estimated using a capacitance-per-unit-length model based on wire length
and routing.
 the width of routing wires is set to the minimum and the wiring capacitance is estimated from the
lengths of the wires.

Estimation Techniques

 Cell-Based Design: Pin capacitance can be measured and stored in cell libraries.
 Wire-Load Model: Estimates wire capacitance based on pin count and circuit size before physical
design.
 Post-Layout Extraction: Accurate capacitance calculation using wire lengths after physical design.

 Pre- and Post-Layout Capacitance Estimation:

 Before physical design, capacitance is estimated using wire-load models, predicting wire length based
on pin counts.
 After physical design, the actual wire length provides accurate wiring capacitance for verification.
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 Importance of Capacitance Estimation: Accurate capacitance estimation is vital for power analysis, both
in the pre-layout and post-layout stages, to optimize power dissipation in chip designs.

List the approaches followed in event driven gate level power simulation. (04 Marks)
Explain the event driven gate level power simulation. (04 Marks)
1. Run logic simulation with a set of input vectors.
2. Monitor the toggle count of each net; obtain capacitive power dissipation P cap with Equation (2.3).

3. Monitor the dynamic energy dissipation events of each gate; obtain internal switching power dissipation
Pin, using Equation (2.4).

4. Monitor the static power dissipation states of each gate; obtain static power dissipation Pstat, with
Equation (2.5).

5. Sum up all power dissipation components.

The total power dissipation of the circuit is the sum of the three power components expressed in Equations
(2.3), (2.4) and (2.5)

Simulation Vectors - Careful selection of simulation vectors is essential for accurate power analysis.

 Choice Matters: Power dissipation depends on simulation vectors.

 Representative Vectors: Vectors should reflect desired operating conditions.
 Application-Specific: Vectors depend on the chip's intended use.
 Avoid Test Vectors: Test vectors may not represent typical operating conditions.

Power Dissipation Factors - Considering various operating conditions and using case analysis helps capture
power variations.

 Operating Conditions: Voltage, temperature, output load, input slopes, fabrication process affect
power.
 Case Analysis: Simulating under various conditions helps capture power variations.
 Characterization: Storing results in a multi-dimensional table for efficient lookup.

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Gate-Level Power Analysis -Gate-level power analysis provides valuable insights but may have limitations in
modeling signal glitches.

 Accuracy: Can achieve 10-15% accuracy compared to SPICE.

 Commercial Tools: Available for gate-level power analysis.
 Detailed Analysis: Provides per-gate, per-net power dissipation information.

Limitations:

 Signal Glitches: Gate-level analysis struggles to accurately model signal glitches, which can be a
significant source of power dissipation.
 Probabilistic Techniques: Some approaches use probability to estimate glitch effects, but precise
deterministic analysis remains challenging.

Discuss the concept of gate level estimation with an example of 2 input NAND gate, extend
the same to gate level power analysis flow. (08 Marks)

Questions:
Discuss architectural level power analysis method. (10 Marks)
Describe architectural level power analysis method. (10 Marks)
Explain architectural level power analysis method. (10 Marks)
Model the architectural-level power based on activities and component operations. (06
Marks)
Explain the following models related to architectural level analysis.
i) Power model based on activities
ii) Power model based on component operations. (07 Marks)

Architecture-level Analysis
|- Power Models Based on Activities
|- Power Model Based on Component Operations
|- Abstract Statistical Power Models

Challenges of Gate-Level Characterization

 Event and State Explosion: Architectural components have numerous possible events and states.
 Intractability: Enumerating all possible combinations for a 16-bit adder, for example, is
computationally infeasible.

 Architecture-Level Abstraction: This design level is above logic gates, focusing on blocks like registers,
adders, multipliers, memories, etc., which perform high-level functions. It is also called block-level or macro-
level design.

 Shift Toward Architectural Design: As VLSI chips grow in complexity, designing at the gate level has
become inefficient. The focus has shifted from designing individual gates and transistors to using higher-level
architectural components. Lower-level descriptions (gates, transistors) can now be automatically generated from
architectural descriptions.

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 Challenges in Power Characterization: The dynamic event and static state characterization methods used
at the gate level cannot be easily applied to architectural components due to the vast number of possible states
and events. For example, fully characterizing a 16-bit adder may require enumerating billions of possible
events, making it impractical for power analysis.

 Importance of Architectural Power Analysis: With more digital circuits being synthesized from
architectural descriptions, architecture-level power analysis is becoming increasingly crucial for managing
power dissipation in complex designs.

Architecture-Level Abstraction

 Building Blocks: Registers, adders, multipliers, busses, multiplexors, memories, state machines, etc.
 Higher Level: Focuses on the functional behavior of components rather than individual gates.
 Rising Importance: Becoming more prevalent due to increasing circuit size and complexity.

Power Models Based on Activities

 Architecture-level power modeling simplifies analysis by focusing on component-level

characteristics.
 Architectural components often have structured, repetitive patterns.
 The components are typically constructed by cascading or repeating simpler units built from logic
gates.
 One way to characterize the architectural components is to express the power dissipation as a function
of the number of bits of the components and their operating frequencies.
 Power Models: Power can be expressed as a function of component size and frequency.
 Data Dependency: More accurate models consider the impact of input data values on power.

Example

• The power dissipation of an adder can be expressed as

• where n is the no. of bits, f is the frequency of addition operation,

• K1 and K2 are empirical coefficients derived from characterization with a lower- level power analysis
such as gate-level simulation.
• The model does not take into account the data dependency of the power dissipation.
• More Accurate Model

• perform characterization to derive the coefficients Ki

• The number of coefficients can be reduced because of the particular characteristics of the component.
Ai and Bi (ith Bit Position)
• For larger components with deep logic nesting, e.g., multipliers,

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Equations (2.9) and (2.10) require a factor Ki for each input i. Sometimes this is too
tedious to characterize and we can simplify them to

The characterization of the coefficients involves generating random signals with

the specified frequencies to exercise the architectural components. The power
dissipations of the components are observed and the K factors are derived by regression
fitting.

Characterization:

 Random Signals: Generating random signals with specified frequencies to exercise components.
 Regression Fitting: Deriving coefficients K1, K2, and Ki using regression analysis based on observed
power dissipation.

Power Model Based on Component Operations:

• Operation-based power modeling provides a simplified approach for architecture-level components.
• Express power in terms of frequencies of fundamental operations.
• Example: Memory component power modeled using read and write frequencies.
• Power dissipation for architecture-level components, like small memory units, can be modeled using the
frequency of key operations (e.g., READ and WRITE). This simplifies power analysis since components
typically perform only a few well-defined operations.

The parameters f read and fwrite are the frequencies of READ and WRI1E operations,
• The Coefficients K1 and K2 are determined through characterization and properties of the component.
• The compromise is to use the average READ and WRITE energy of the operations in Equation (2.12),
which introduces some inaccuracies, but improves the computation efficiency and generality of the
power model.
• Skewed Access Patterns: the memory access pattern is skewed such that most of the READ and
WRITE operations occur at a particular location, e.g., address zero. If this is known a priori, the power
model can be modified to improve the accuracy.
• For example, we can characterize the zero address (ZA) and the non-zero address (NZA) operations as

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Abstract Statistical Power Models:

 Efficiency vs. Precision: To model power dissipation efficiently, assumptions about the statistical behavior
of components are necessary. Precise signal-level models are computationally inefficient due to the large
number of I/O pins.

Power models for architecture-level components require statistical assumptions due to computational inefficiency.

 Statistical Models: Power models often use statistical parameters like Pin toggling, operations, probabilities,
and other statistical quantities rather than exact logic events.

 Key Issues in Power Modeling:

 Key factors influencing power dissipation include size, signal frequency, operation frequency, etc.
 Identifying parameters (size, signal frequency, operation frequency) that affect power dissipation.
 Defining the relationship between these parameters and power consumption (using equations or
lookup tables).

 Component-Specific Analysis: Different components like adders, multipliers, memories, and registers have
distinct characteristics, requiring different parameters for accurate power analysis.

 Trade-off Between Accuracy and Efficiency: While gate-level models are more precise, architecture-level
models are less robust due to necessary assumptions. However, these models are useful for comparing
designs and guiding design trade-offs.

 Relative Accuracy Focus: Instead of aiming for absolute accuracy, the goal is to provide insights into the
relative power consumption between different designs, enabling informed design decisions at the
architecture level.

 Emphasizing relative accuracy over absolute accuracy is a good strategy for composing power models.
 A good power estimation technique should provide insights into relative power consumption, even if
absolute accuracy is difficult to achieve.

Data Correlation Analysis in DSP Systems

|- Dual Bit Type Signal Model
|- Datapath Module Characterization and Power Analysis

How do you analyse the data correlation in DSP systems? What are the effects of data
correlation on bit switching frequency? (10 Marks)
Briefly discuss Data correlation Analysis in DSP systems (8 Marks)
Explain the dual bit type used for characterization of data signals. (08 Marks)
Data Correlation Analysis in DSP Systems
 Sample correlation is a phenomenon where successive data samples have similar numerical values and
binary representations.
 This is caused by sampling band-limited analog signals at higher rates than their bandwidth.

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 Some data streams exhibit negative correlation (anti-correlation) with alternating large positive and negative
values.
 Delta modulation is an example of a digital signal coding scheme that can produce negatively correlated
data.
 Positive or negative correlation significantly affects power dissipation in DSP systems due to switching
activities on the system datapath.
 The goal is to estimate power dissipation at the architecture level component based on
frequency and correlation measures of the data stream.
 A high-level power model can be developed without sample-by-sample analysis by understanding the
relationship between data correlation and power dissipation.

High-Level Power Modeling: By understanding the relationship between data correlation and power dissipation, a
high-level power model can be developed. This avoids the need for detailed, sample-by-sample analysis and instead
uses data frequency and correlation measures to estimate power dissipation at the architecture level.

Dual Bit Type Signal Model

 Data correlation's effect on power dissipation depends on the numerical representation (two's
complement or signed magnitude).
 Two's complement representation is assumed for analysis, as signed magnitude is similar.
 Toggle characteristic of the data signals under the influence of data correlation.
 If the data sample is positively correlated, successive data sample values are very close in their binary
representation.
 This means that the least significant bits (LSB) of the data bus toggle frequently while the most
significant bits (MSB) are relatively quiet.
 Bit-toggle frequency plots show a white noise region (LSB) and a sign bit region (MSB).
 The grey area between regions has a changing bit-toggle rate from near zero to 0.5.
 Switching frequency is normalized to the maximum toggle rate (half the sampling frequency).
 Some of the LSB bits toggle at approximately half the maximum frequency. This is called the uniform
white noise region because the bits toggle in a random fashion.
 On the MSB side, the bits have a very low toggle rate and they are called the sign bit region.
 There is also a grey area between the two regions where the toggle frequency changes from white
noise to sign bit.
 In this region, the bit-toggle rate changes from near zero to 0.5, typically in a linear fashion.
 Negatively correlated data have a high switching frequency in the sign bit region and random noise in
the noise bit region.

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  No correlation results in uniform white noise characteristics for all bit switching.

The above observation allows us to characterize the data stream with only a few
parameters:
1. Sample frequency.
2. Data correlation factor from -1.0 to + 1.0.
3. The sign bit and unifonn white noise regions with two integers.
Such characterization of data signals is called the dual bit type model

Datapath Module Characterization and Power Analysis:

 Dual bit type signal model provides a compact representation of switching characteristics.
 Develop power dissipation models (equations) under such signal excitation (power analysis of
architectural components)
 Power dissipation models are sensitive to signal correlation and bit types.
 Various methods exist to characterize power dissipation.
 Example
 A simple single-input single-output block (FIFO) is used for illustration.
 Assumption:
 Activity coupling between bits is assumed to be negligible.
 A lower-level power analysis tool is used to characterize effective capacitance under white noise. To
analysis power dissipation
• Power Dissipation of a single bit under the uniform white noise signal at a particular frequency f₁ &
voltage V₁
• The effective capacitance Cu of the bit is defined as

• The effective capacitance Cu is approximately equal to the capacitance being switched under the white
noise signal excitation.
• This effective capacitance is used to compute power at a different frequency f2 and different voltage V2
under white noise signal excitation

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 • The concept of effective capacitance can also be used on the module bits under the sign bit signal
excitation.
• Effective capacitance is no longer a scalar quantity.
• Between successive data samples, the sign bit may or may not change sign.
• Thus, Four effective capacitance values: C++, C+-, C-+, C-- subscript sign pairs
• In a FIFO data queue, it is most likely that C +- = C-+ and C++ = C—
 Construct circuits in which all four effective capacitance variables have different values.
• With the four effective capacitance values characterized by a lower-level power analysis tool,
• Construct a power equation.
• Let p++, p+-, p-+, p-- be the probabilities that sign changes occur in the data stream.
• Power equation for the bit excitation under the sign bit signal:

where V is the operating voltage and I is the frequency of the data stream.
Note that
p ++ + p +- + p -+ + p-- = 1 and for long data sequence p +- = p -+

N-Bit Module:
 For a module that consists of multiple bits
 Distinguish the white noise bits from the sign bits
 Take the midpoint of the grey area

 All bits to the left (right) of the midpoint are considered to have sign bit (white noise) signals.
 Ns = sign bits Nu = whit noise bits
 The power dissipation P of the module :

 The effective capacitance Cu' C++, C+_, C_+, C _ are obtained during characterization, once per
module design.
 The variables Ns' Nu' p++, p+_, p_+, p __ , are obtained from the correlation factor and signal properties
of the data stream, typically by analyzing the data stream from the behavior-level simulation.
 If the data stream has high positive correlation,

 Equation (2.17) assumes that there are no interactions among data bits in the module and allows us to
characterization one bit and applies the effective capacitance to the other bits.
 This is no longer true for modules that have interactions among data bits such as barrel shifters.
 The characterization for all possible combinations of Nu and Ns. Since Nu + Ns is equal to the number of
bits N of the module, there are only N + I conditions to be characterized.

Where C(Nu), 0≤ Nu≤ N is the effective capacitance when there are Nu white noise bits at the module's input.
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Explain dual bit type signal model for DSP systems. How an adder of 2 input and 1 output
module is characterized. (08 Marks)
Refer the above points
Adder of 2 input and 1 output module:
 The two inputs may have different sign and noise bit separation points.
 Modules with two inputs and one output (e.g., adders) have overlapping sign and noise bit regions at the
output.
 as shown in Figure 2.7. There are four possible polarity conditions in the sign bit portions of the
inputs and output.
 Therefore, there are 4 x 4 x 4 = 64 possible types of signal transition patterns. This means that there are
64 effective capacitances from C+ +/++/++, C+ +/++/+- to C--/--/--.
 The "u/ss" condition (INI has noise bits and IN2 has sign bits) requires another four effective
capacitances and so is the "ss/u"
 condition.
 The "ulu" input combination only requires one effective capacitance value.
 In total, there are 64 + 4 + 4 + I = 73 effective capacitance values to be characterized using a lower-level
power analysis tool.
 for an adder, some transition patterns may not occur. For example, C ++1++1 _ is zero because when
both inputs have the positive sign, the output cannot have the negative sign.
 In general, all 73 effective capacitances have to be characterized for an arbitrary two-input one-output
module.
 The power dissipation is given by

The dual bit type characterization method can be generalized to most types of
architecture- level components such as multipliers, memories, etc.

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  Determining the boundary between sign and noise bits is a key step in power analysis.
 This can be done through simulation or probabilistic analysis.
 Once bit types are determined, Equation (2.17) or (2.19) calculates power dissipation.
 The analysis method is a bottom-up approach where modules are pre-designed and pre-characterized.
 Cell libraries are suitable for bottom-up approaches due to their small size and reusability.
 Architecture-level components (adders, multipliers, register files) are less reusable and often require
custom design.
 Once characterized, these components can be analyzed under various data correlation and dynamic
ranges.
 Characterization of newly designed components is essential in any bottom-up approach.

Explain Monte Carlo – simulation technique. (08 Marks)

Explain Monte-Carlo simulation technique. (10 Marks)
 Simulation-based power analysis: Requires simulation vectors at primary inputs to trigger circuit activities.
 Power dissipation calculation: Switching activity information is collected and applied to power models to
obtain power dissipation.
 Simulation vectors impact: Vectors significantly affect power dissipation, as power depends on switching
activities.
 Vector selection: Vectors should represent typical conditions for accurate power estimation.
 Vector sources: For CPUs, simulation vectors can be obtained from instruction traces of benchmark
software.
 Vector length: Shorter vector lengths may not accurately represent circuit activity, while longer lengths can
be computationally expensive.
 Stopping criteria: Determining when simulation is accurate enough for the intended purpose is important.
is it necessary wasting computer resources to simulate that many vectors?
How many input vectors are required for correct estimation of power dissipation?
How much extra accuracy can we achieve by simulating a million vectors versus only a
thousand vectors?
How do we know that we have simulated enough vector length?
All these lead to an important question of the stopping criteria of the simulation:
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Statistical Estimation of Mean
 Sample period: A basic sample period T is defined, during which a single power dissipation value is
observed.
 For example, T may be several vectors or several clock cycles.
 After a particular simulation period Ti the power dissipation Pi of the circuit during the period Ti is
computed.
 a series of power samples P0 P0' ... , PN
 The estimated power dissipation P of the circuit under simulation is given by the average value of
the samples, i.e.,

 This is the classical mean estimation problem in statistics in which we draw N samples from a large
population and try to determine the mean of the population.
 For small value of N, P is not truthful
 For large N unnecessary computation will be performed without gaining meaningful accuracy.
 Trade-off between sample size and accuracy. Our questions of stopping criteria now become the
determination of the sample size N.
 The power samples Pi are random variables following some unknown probability density function.
 The distribution of Pi depends on the circuit, simulation vectors and the sample interval.
 Let µ and σ2 be the mean and variance of pi, Now the question is how accurate is P in estimating µ with
N samples?
 According to the well-known central limit theorem in statistics, the sample mean P approaches the
normal distribution for large N regardless of the distribution of Pi.
 For theoretical development, let us assume that the samples Pi have normal distribution.
 Basic statistical theory states that the average of normally distributed random variables also has normal
distribution. The mean of P is exactly µ and its variance is

As we increase the sample size N, the variance σp2 diminishes so that we obtain more accurate measures of the
true mean µ.

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  To quantify the accuracy of the sample mean P, a maximum error tolerance Ɛ term is used typically with
values less than 10%, Given Ɛ, what is the probability that P is within the Ɛ error range of the true mean
µ?
 what is the probability for the condition 0≤ |P-µ|/µ ≤ Ɛ?

 If this probability is high, we will trust the estimate P; otherwise, we must increase the sample size N to
gain more confidence.
 The probability can be obtained by integrating the normal distribution curve p(x) in Figure 2.8.
 For historical reason, the probability is more conveniently expressed by a confidence variable .
 The confidence level is defined as 100 (1 - )%. A confidence level of 100% ( = 0) means that P is
absolutely within the error tolerance of Ɛ.
 Typically, the confidence level is set to more than 90% to be meaningful, i.e., ≤ 0.1.
 To explore the relationships among Ɛ, . and N. We define a variable z/2 such that the area between µ-
z/2σp and µ + z/2σp under the normal distribution curve p(x) is (1- ).
 To ensure the condition |P-µ|/µ ≤ Ɛ , we require that

 Substituting Equation (2.21) into the second inequality of (2.22), we have

 Since  and Ɛ are fixed constants prescribed by the experimenter, the equation can be rewritten as

 Equation (2.24) tells us the minimum number of samples N to be taken in order to be at least (l - )
confident that the error of P is within the tolerance of Ɛ.
 The value of z/2 is typically obtained from a mathematical table known as the z-distribution function.
For most practical purposes, z/2 is a small number.

At confidence level of 90% ( = 0.1), Z0.05 is approximately 1.65. At confidence of 99% ( = 0.01), Z0.005 is
approximately 2.58. The following table shows some values of (1 - ) and z/2.

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The variables P and S2 are quantities that can be directly computed from the observed N samples of Pi.

Discuss Monte Carlo power simulation. (08 Marks)

Describe the Monte Carlo power simulation approaches. (07 Marks)
Monte Carlo power simulation is a statistical technique used to estimate the power consumption of digital
circuits. It leverages random sampling to generate a large number of input vectors and simulates the circuit's
behavior under these conditions. 1 By analyzing the power consumption of these simulations, the technique can
provide a more accurate estimate of the circuit's average power dissipation.

we collect samples Pi at a fixed interval to compute the sample mean P = (P0 + P1 + ... + PN)/N and sample
variance S2 using Equation (2.26). Given the confidence level (1 - ) and error tolerance Ɛ, we check if Equation
(2.27) is satisfied. If so, we claim that the stopping criteria have been achieved and stop the simulation.
This process is called Monte Carlo power simulation.

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The procedure is summarized as follows:
 Simulate to collect one sample pi.
 Evaluate sample mean P and variance S2 using equation 2.20 & 2.26

 Check if the inequality (2.27) is satisfied; if so stop, else repeat from Step 1.

 As more samples are collected, the power dissipation value P becomes more accurate and eventually the
stopping criteria are satisfied.
Logic-level Monte Carlo simulation
 First the samples Pi have to be statistically independent. This is always a fundamental assumption of the
statistical analysis.
 if the sample period T is shorter than the typical gate delay, we could violate the independence
assumption.
 This is because when the input of a gate is switching, the output is very likely to switch after the
gate delay. Thus, subsequent samples are highly correlated if the sample period is shorter than the
gate delay.
 we can always set T to be very large to assure independence but this prolongs the simulation time.
 Simulation time: The simulation time (related to sample size N) depends on the ratio of the sample variance
and sample mean S2/p2.
 Circuit size and variance: For larger circuits, the sample variance S2 typically decreases due to the
increased number of uncorrelated nodes. This leads to a reduction in the required sample size N.
 Simulation time for large circuits: Despite the reduced sample size, the simulation time for large circuits
can be similar to that for small circuits. This is because large circuits have more randomness, leading to less
variation in power samples.
 Stopping criteria: A technique for deciding the stopping criteria without observing the power samples has
been reported.

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The standard deviation of the power samples measured from the circuit has been observed to have ±18%
fluctuation from the mean. How many samples are required so that we are 95% confident that the error
of sample mean is within ±5%? The 2 distribution table shows 1.96 for 95% confidence. (04 Marks)

We have σ/µ =0.18 Ɛ = 0.05. Since (1- σ) = 0.95, we have z/2 = 1.96

σ/µ -> fluctuation from the mean

Ɛ -> error of sample mean
(1- σ) -> confident

N = (1.96 *0.18/0.05)2 = (7.056)2

N = 49.787= 50

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Explain, how an MOS transistor is modeled for amplification and switching simulation model. (04 Marks)

Discuss dynamic energy dissipation events and static power dissipation states of 4 transistors CMOS
NAND Gate. (10 Marks)

For an 4-transistor, 2-input NAND gate evaluate how an dynamic energy and static power dissipation states are
obtained and also evaluate the dynamic energy dissipation events. (06 Marks)

Power Analysis

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