Topic 7 Notes

7.1 Computer Buses

Buses are the basic transportation lines for moving data, instructions, addresses, and other
information inside a computer.

A bus is a set (group) of parallel lines that information (data, addresses, instructions, and other
information) travels on inside a computer. Information travels on buses as a series of electrical
pulses, each pulse representing a one bit or a zero bit (there are trinary, or three-state, buses, but
they are rare). Some writers use the term buss with a double ‘s’
The purpose of buses is to reduce the number of "pathways" needed for communication between
the components, by carrying out all communications over a single data channel. This is why the
metaphor of a "data highway" is sometimes used.

Fig 7.1: Bus architecture

7.2 Characteristics of a bus

The size or width of a bus is how many bits it carries in parallel. Common bus sizes are: 4 bits, 8
bits, 12 bits, 16 bits, 24 bits, 32 bits, 64 bits, 80 bits, 96 bits, and 128 bits.
The speed of a bus is how fast it moves data along the path. This is usually measured in MegaHertz
(MHz) or millions of times a second.
The bus speed is also defined by its frequency (expressed in Hertz), the number of data packets
sent or received per second. Each time that data is sent or received is called a cycle.
The capacity of a bus is how much data it can carry in a second. In theory this is determined by
multiplying the size of the bus by the speed of the bus, but in practice there are many factors that
slow down a bus, including wait cycles (waiting for memory or another device to have information
ready).
Some recent buses move two sets of data through the bus during each cycle (one after the other).
This is called double pumping the bus.
A bus master is a combination of circuits, control microchips, and internal software that control
the movement of information over a bus. The internal software (if any) is contained inside the bus
master and is separate from the main processor.
Parallel buses have a relatively large number of wires bundled together that enable data to be
transferred in parallel. This increases the throughput, or rate of data transfer, between the
peripheral and computer.
Serial bus is a shared channel that transmits data one bit after the other over a single wire or fiber.

7.3 The primary buses

There are generally two buses within a computer:
the internal bus (sometimes called the front-side bus, or FSB for short). The internal bus
allows the processor to communicate with the system's central memory (the RAM).
the expansion bus (sometimes called the input/output bus) allows various motherboard
components (USB, serial, and parallel ports, cards inserted in PCI connectors, hard drives,
CD-ROM and CD-RW drives, etc.) to communicate with one another. However, it is
mainly used to add new devices using what are called expansion slots connected to the
input/output bus.

7.4 The chipset

A chipset is the component which routes data between the computer's buses, so that all the
components which make up the computer can communicate with each other. The chipset
originally was made up of a large number of electronic chips, hence the name. It generally has two
components:
The NorthBridge (also called the memory controller) is in charge of controlling transfers
between the processor and the RAM, which is way it is located physically near the
processor. It is sometimes called the GMCH, forr Graphic and Memory Controller Hub.
The SouthBridge (also called the input/output controller or expansion controller) handles
communications between peripheral devices. It is also called the ICH (I/O Controller
Hub). The term bridge is generally used to designate a component which connects two
buses.
Fig 7.2: The Chipset

7.5 Example of buses

A processor bus is a bus inside the processor. Some processor designs simplify the internal
structure by having one or two processor buses. In a single processor bus system, all information
is carried around inside the processor on one processor bus. In a dual processor bus system, there
is a source bus dedicated to moving source data and a destination bus dedicated to moving results.
An alternative approach is to have a lot of small buses that connect various units inside the
processor. While this design is more complex, it also has the potential of being faster, especially
if there are multiple units within the processor that can perform work simultaneously (a form of
parallel processing).
A system bus connects the main processor with its primary support components, in particular
connecting the processor to its memory. Depending on the computer, a system bus may also have
other major components connected.
A data bus carries data. Most processors have internal data buses that carry information inside
the processor and external data buses that carry information back and forth between the processor
and memory.
An address bus carries address information. In most processors, memory is connected to the
processor with separate address and data buses. The processor places the requested address in
memory on the address bus for memory or the memory controller (if there is more than one chip
or bank of memory, there will be a memory controller that controls the banks of memory for the
processor). If the processor is writing data to memory, then it will assert a write signal and place
the data on the data bus for transfer to memory. If the processor is reading data from memory, then
it will assert a read signal and wait for data from memory to arrive on the data bus.
In some small processors the data bus and address bus will be combined into a single bus. This is
called multiplexing. Special signals indicate whether the multiplexed bus is being used for data
or address. This is at least twice as slow as separate buses, but greatly reduces the complexity and
cost of support circuits, an important factor in the earliest days of computers, in the early days of
microprocessors, and for small embedded processors (such as in a microwave oven, where speed
is unimportant, but cost is a major factor).
Instruction (I) Bus allows communication between the CPU and memory. It carries to the CPU
the program instruction words to be operated on by the CPU from memory or returns instructions
to memory. The I bus is controlled by the CPU. It is capable of sending or receiving data while the
operand (O) bus is receiving or sending data at the same time, but only in one direction at a time
Operand (O) Bus allows communication between the CPU and memory or the CPU and an I/O
Controller (IOC). The CPU controls the operation in both cases. The O bus is capable of sending
or receiving data, while the I bus is receiving or sending data at the same time, but only in one
direction at a time. The direction of the data depends on whether the CPU is reading data from
memory or data is being written back into memory
memory bus is a bus that connects a processor to memory or connects a processor to a memory
controller or connects a memory controller to a memory bank or memory chip.
A cache bus is a bus that connects a processor to its internal (L1 or Level 1) or external (L2 or
Level 2) memory cache or caches.
An I/O bus (for input/output) is a bus that connects a processor to its support devices (such as
internal hard drives, external media, expansion slots, or peripheral ports). Typically the connection
is to controllers rather than directly to devices.
A graphics bus is a bus that connects a processor to a graphics controller or graphics port.
A local bus is a bus for items closely connected to the processor that can run at or near the same
speed as the processor itself.

7.6 Bus standards

ISA (Industry Standard Architecture) is a bus system for IBM PCs and PC clones. The original
standard, from 1981, was an 8 bit bus that ran at 4.77 MHz. In 1984, with the introduction of the
IBM AT computer (which used the 80286 processor, introduced by Intel in 1982), ISA was
expanded to a 16 bit bus that ran at 8.3 MHz.
MCA (Micro Channel Architecture) is a 32 bit bus introduced in 1987 by IBM with the PS/2
computer that used the Intel 80386 processor. IBM attempted to license MCA bus to other
manufacturers, but they rejected it because of the lack of ability to use the wide variety of existing
ISA devices. IBM continues to use a modern variation of MCA in some of its server computers.
EISA (Extended Industry Standard Architecture) is a 32 bit bus running at 8.3 MHz created by
the clone industry in response to the MCA bus. EISA is backwards compatible so that ISA devices
could be connected to it. EISA also can automatically set adaptor card configurations, freeing users
from having to manually set jumper switches.
NuBus is a 32 bit bus created by Texas Instruments and used in the Macintosh II and other
680x0 based Macintoshes. NuBus supports automatic configuration (for “plug and play”).
VL bus (VESA Local bus) is created in 1992 by the Video Electronics Standards Association
for the Intel 80486 processor. The VL bus is 32 bits and runs at 33 MHz. The VL bus requires use
of manually set jumper switches.
PCI (Peripheral Component Interconnect) is a bus created by Intel in 1993. PCI is available in
both a 32 bit version running at 33 MHz and a 64 bit version running at 66 MHz. PCI supports
automatic configuration (for “plug and play”). PCI automatically checks data transfers for errors.
PCI uses a burst mode, increasing bus efficiency by sending several sets of data to one address.
DIB (Dual Independent Bus) was created by Intel to increase the performance of frontside L2
cache.
SECC (Single Edge Contact Cartridge) was created by Intel for high speed backside L2 cache.
AGP (Accelerated Graphics Port) was created by Intel to increase performance by separating
video data from the rest of the data on PCI I/O buses. AGP is 32 bits and runs at 66 MHz. AGP
2X double pumps the data, doubling the amount of throughput at the same bus width and speed.
AGP 4X runs four sets of data per clock, quadrupling the throughput.
DRDRAM was a memory bus created by Rambus to increase speed of connections between the
processor and memory. DRDRAM is a 33 bit bus running at 800 MHz. 16 bits are for data, with
the other 17 bits reserved for address functions.

Revision questions
1. What is the purpose of a bus n a computer system?
2. Describe the architecture of a bus systems
3. Explain the characteristics of a bus
4. Identify the types of buses
5. Differentiate between a north and south bridge