Chapter : 2

INSTRUCTION SET
Programming Model of 8085
 Classification of
Instructions
1. Data transfer group.
2. Arithmetic group.
3. Logical group.
4. Branching group.
5. Machine control group.
 Data Transfer group
• This group of instruction copies data
from a location called source to
another location called a
destination without modifying the
content of source.
• These instructions move data
between registers or between
memory locations and registers.
• For eg. MOV, MVI etc.
 Arithmetic group
• The instruction of this group
performs arithmetic operations
such as addition, subtraction
increment or decrement etc. on
data in registers or memory.
• For eg. ADD, SUB, INR, DCR etc
 Logical group
•The logical group
instructions perform
logical operations
•such as AND, OR, XOR,
complement etc. generally
with the accumulator.
 Machine Control Group :
•These instructions
control machine
operations such as Halt,
Interrupt
•For e.g. NOP, HLT.
 Branching Group
•The branching group
instructions allow
programmer to change the
sequence of execution of
program either conditionally
or unconditionally.
• For e.g. JMP, JC, JZ etc.
 Data transfer group
1. MOV rd , rs
2. MOV rd , M
3. MOV M , rs
4. MVI r , data ( 8bit )
5. MVI M , data ( 8bit )
6. LXI rp , data ( 16 bit )
7. LDA address ( 16 bit )
8. STA address ( 16 bit )
9. LDAX rp, [ LDAX B, LDAX D]
10. STAX rp , [ STAX B, STAX D]
11. LHLD address ( 16 bit )
12. SHLD address ( 16 bit )
13. XCHG
 MOV rd, rs
• COPY rs rd
• E.g MOV B(rd), A(rs) [B A]

Before Execution After Execution

A 08H A 08H
MOV B,A

B XXH B 08H
 MOV rd, m
• COPY M rd
• E.g MOV C(rd), M(rs) [C M]
Before Execution After Execution

C XXH C 04H

F002H XX
F002H XX
MOV C,M
F001H 04
F001H 04
F000H XX
F000H XX
F0 01
memory F0 01
H L memory
H L
 MOV M, rs
• COPY rs M
• E.g MOV M(d), D(rs) [M D]
Before Execution After Execution

D 07H D 07H

F002H XX
F002H XX
MOV M,D
F001H xx
F001H 07
F000H XX
F000H XX
F0 01
memory F0 01
H L memory
H L
 MVI r,data ( 8 bit)
• r is any one of the general purpose register such as
A,B,C,D,H&L
• r data (8bit)
• Eg :- MVI A , 04H

Before Execution After Execution

A xx MVI A,04H
A 04H
 MVI M, data (8 bit )
• COPY M data (8 bit )
• E.g MVI M , 02H [ M 02H ]

Before Execution After Execution

F002H XX F002H XX
MVI M, 02H
F001H XX
F001H 02
F000H XX F000H XX
F0 01
F0 01
H L memory memory
H L
 LXI rp,data (16 bit)
• rp is any one of the valid register pair such as
BC,DE & HL LXI B, data (16bit)
• rp data (16 bit) B data (higher 8bit)
C data (lower 8 bit)
• H data (higher 8bit)
LXI D, data (16bit)
• L data (lower 8 bit)
D data (higher 8bit)
• Eg :- LXI H, 8090H E data (lower 8 bit)

Before Execution After Execution

xx xx LXI H , 8090H 80 90
H L H L
Eg :- LXI B, 4070
H
Before Execution After Execution

xx xx 40 70
B C B C
Eg :- LXI D,
5080H
Before Execution After Execution

xx xx 50 80
D E D E
 LDA Address(16 bit)
• LDA--- Load Accumulator Direct

• Load Accumulator With content of memory whose address is

specified in the instruction Itself
• Acc. ( Address )
• E.g LDA F020H
• A (F020H)
Before Execution After Execution
Acc=xxH Acc = 04H
LDA F020H
F021H xxH
F021H xxH
F020H 04 F020H 04H
MEMORY MEMORY
 STA Address(16 bit)
• STA Store Accumulator Direct
Store accumulator at memory location whose address is
specified in the instruction Itself
• ( Address) Acc.
• e.g STA F030H
• (F030H) Acc.
Before Execution After Execution
Acc=07H Acc = 07H

F031H xx H STA F030H

F031H xxH
F030H xx H F030H 07H
MEMORY MEMORY
 Working Of LDAX D
Where ‘rp’ is DE register pair
Load Acc. With content of memory whose
address is in DE Pair
Before Execution After Execution
Acc=xx H
LDAX D A= 08 H
D E
F0 13 D E
F012H xxH F0 13
F012 xxH
F013H 08H
MEMORY
F013 08 H
MEMORY
 Working Of STAX D
Where ‘rp’ is DE register pair
Store Acc. in memory whose address is in DE Pair
(DE) Acc
Before Execution After Execution

Acc=09H Acc = 09H

STAX D
D E
F0 47
D E
F046 xx H F0 47
F047 Xx H F046 xxH
MEMORY F047 09 H
MEMORY
 Working Of STAX B
Where ‘rp’ is BC register pair
Store Acc. in memory whose address is in BC
Pair

Before Execution After Execution

Acc=03 H
Acc = 03H
B C STAX B
F0 22 B C
F021 xx H F0 22
F021 xxH
F022 xx H
F022 03H
MEMORY MEMORY
 LHLD address( 16 bit) Load HL direct
e.g. LHLD F010 H
e.g. LHLD Address(16 bit)
Operation : Operation :
L (F010H) L ( Address)
H ( F011 H ) H (Address+1)

Before After Execution

Execution
H L H L
Load
XX XX LHLD F010 H 02H 06H HL

F010 H 06H
F010 H 06 H F011 H 02H

F011 H 02 H
RAM
 SHLD address( 16 bit) Store HL direct
e.g. SHLD F001 H
e.g. SHLD Address(16 bit)
Operation : Operation :
( F001 H ) L ( Address ) L
( F002 H ) H (Address+1) H

Before After Execution

Execution
H L H L
Store
04 09 SHLD F001 H 04 09 HL

F001 H 09H
F001 H XX H F002 H 04H
F002 H XX H
RAM
 XCHG(Exchange DE with HL Pair)
• This instruct exchanges the contents of HL register pair with
contents of DE register pair only
• DE HL OR
• D H and E L

Before Execution After Execution

D E
D E
04H 05H
09H 08H
XCHG
09H 08H
04H 05H
H L
H L
 Arithmetic Group
1. ADD r ( A A +r) used for 8 bit addition
2. ADD M ( A A + M ) without carry
3. ADI data( 8 bit) ( A A + data( 8 bit)
4. ADC r ( A A + r + Cy) used for 8 bit addition
5. ADC M ( A A + M + Cy) with carry
6. ACI data(8 bit) ( A A+data(8 bit)+Cy)
7. SUB r ( A A - r) used for 8 bit Subtraction
8. SUB M ( A A - M) without Borrow
9. SUI data(8bit ) ( A A-data( 8 bit)
10. SBB r ( A A - r - Cy ) ) used for 8 bit Subtraction
11. SBB M ( A A - M - Cy ) with Borrow
12. SBI data(8bit) ( A A-data(8bit)–Cy)
13. DAD rp ( HL HL + rp) used for 16 bit addition
14. INR r (r r +1) / DCR r ( r r -1) 15). INX rp, DCX rp
 Difference between ADD and DAD
instruction
ADD r DAD rp
1. It is used for 8 bit 1. It is used for 16 bit
addition addition
2. A A + r 2. HL HL + rp ( HL/
DE/ BC)
3. One of the operand/
data must be Acc. 3. One of the operand/
data must be HL
4. Result is always register pair.
stored in Acc. 4. Result is always stored
5. All flags are affected in HL reg. pair
5. Only carry flag is
affected
 DAD rp( Double byte Addition(16 bit)
DAD rp ( HL HL + rp ) ( Result is always stored in HL)
Where ‘rp ‘ is an one of the valid reg. pair such as HL, DE or BC
1)e.g. DAD D ; Operation is HL HL + DE
2) e.g. DAD B ; Operation is HL HL + BC
3) e.g. DAD H ; Operation is HL HL + HL
Before Execution After Execution
H L H L
05 03
st
08 07
( 1st16 bit no.) ( 1 16 bit no.)
DAD D
D E D E
03 04 03 04
(2nd16 bit no.) (2nd16 bit no.)

Example of DAD D 16 bit addition

 ADD r (A A+r)
• This instruction is used to add content of register ‘r’ to the Acc. And result
is stored in Acc.
• A A+r
• where ‘r’ is any one of the general purpose register such as A, B, C, D, E,
H and L
• e.g. ADD B
• A A + B, after execution All flags are affected

Before Execution After Execution

A 08H A 0CH
ADD B

B 04H B 08H
 ADD C ( A A + C)
• This instruction is used to add content of register ‘r’ to the Acc. And result
is stored in Acc.
• A A+r
• where ‘r’ is any one of the general purpose register such as A, B, C, D, E,
H and L
• e.g. ADD C
• A A + C, after execution All flags are affected

Before Execution After Execution

A 08H A 0FH
ADD C

C 07H C 07H
 ADD M ( A A + M)
• This instruction is used to add content of MEMORY ‘M’
whose address is pointed by HL reg. pair to the contents Acc.
And result is stored in Acc.
• A A + M or A A + (HL)
• E.g HL=F050H, F050H=07H, after execution All flags are affected

Before Execution After Execution

A 02H A 09
ADD M
H L
F0 50
H L SUM
F051 xx H F0 50
F050 07H F051 xxH
MEMORY F050 07 H
 ADI data( 8 bit)
• This instruction is used to add 8 bit data specified
instruction to the contents of Acc. And result is
stored in Acc.
•A A + data(8 bit)
• e.g. ADI 04H( 8 bit)
•A A + 04H, after execution All flags are affected

Before Execution After Execution

A 03H ADI 04H

A 07H

A 03+04=07
 ADC r ( A A + r+ cy )
• This instruction is used to add content of register ‘r’ to the Acc
along with carry . And result is stored in Acc.
• A A + r + Cy
• where ‘r’ is any one of the general purpose register such as A, B,
C, D, E, H and L
• e.g. ADC B
• A A + B + Cy, after execution All flags are affected

Before Execution After Execution

A 07H A 0CH
ADC B
B 04H B 04H
Cy=1 A 07+04+1 Cy=0
 ADC M ( A A + M+ Cy)
• This instruction is used to add content of MEMORY ‘M’
whose address is pointed by HL reg. pair along with carry to
the contents Acc. And result is stored in Acc.
• A A + M +Cy or A A + (HL) + Cy
• E.g HL=9050H, 9050H=06H After execution all flags are affected
Before Execution After Execution

A 03H A 0A SUM
H L
ADC M
90 50
H L Cy=0
9051 xx H 90 50
9050 06H 9051 xxH
Cy=1 MEMORY 9050 06H
A 03+06+1
 ACI data( 8 bit)
• This instruction is used to add 8 bit data specified
instruction along with carry to the contents of
Acc. And result is stored in Acc.
•A A + data(8 bit) + Cy
• e.g. ACI 04H
•A A + 04H + Cy, after execution All flags are affected
Before Execution After Execution

A 03H ACI 04H A 08H

Cy=1 Cy=0
A 03+04+1=08
 SUB r (A A-r)
• This instruction is used to Subtract content of register ‘r’ from the Acc.
And result is stored in Acc.
• A A - r
• where ‘r’ is any one of the general purpose register such as A, B, C, D, E,
H and L
• e.g. SUB C
• A A - C, after execution All flags are affected

Before Execution After Execution

A 06H A 02H
SUB C

C 04H
C 04H
A 06 – 04
A=02
 SUB D ( A A - D)
• This instruction is used to subtract content of register ‘r’ from the Acc. And
result is stored in Acc.
• A A - r
• where ‘r’ is any one of the general purpose register such as A, B, C, D, E,
H and L
• e.g. SUB D
• A A - D , after execution All flags are affected

Before Execution After Execution

A 08H A 00H
SUB D

D 08H D 08H
A 08 – 08
A=00
 SUB M ( A A - M)
• This instruction is used to subtract content of MEMORY ‘M’
whose address is pointed by HL reg. pair from the contents
Acc. And result is stored in Acc.
• A A - M or A A - (HL)
• E.g HL=7050H, 7050H=07H after execution All flags are affected

Before Execution After Execution

A 0AH A 03
SUB M
H L
70 50 Subtract
H L result
7051 xx H 70 50
7050 07H 7051 xxH
MEMORY 7050 07 H
 SUI data( 8 bit)
• This instruction is used to subtract 8 bit data
specified instruction from the contents of Acc.
And result is stored in Acc.
•A A - data(8 bit)
• e.g. SUI 09H
•A A - 09H

Before Execution After Execution

SUI 09H
A 0BH A 02H

A 0B-09=02
 SBB r ( A A - r -Cy)
• This instruction is used to Subtract content of register ‘r’ from the Acc
along with carry. And result is stored in Acc.
• A A - r - Cy
• where ‘r’ is any one of the general purpose register such as A, B, C, D, E,
H and L
• e.g. SBB C
• A A - C - Cy, after execution All flags are affected

Before Execution After Execution

A 06H A 01H
SBB C
C 04H C 04H
Cy=1 A 06 – 04 - 1
Cy=0
A=01
 SBB M ( A A – M - Cy)
• This instruction is used to subtract content of MEMORY ‘M’
whose address is pointed by HL reg. pair from the contents
Acc along with carry. And result is stored in Acc.
• A A - M -Cy or A A - (HL) - Cy
• E.g HL=6050H, 6050H=04H after execution All flags are affected

Before Execution After Execution

A 0AH A 05
SBB M
H L
60 50 Subtract
H L result
6051 xx H 60 50
6050 04H 6051 xxH
Cy=1 MEMORY Cy=0 6050 04 H
 SBI data( 8 bit)
• This instruction is used to subtract 8 bit data
specified instruction from the contents of Acc
along with carry . And result is stored in Acc.
•A A - data(8 bit) - Cy
• e.g. SBI 08H
•A A - 08H - Cy

Before Execution After Execution

A 0BH SBI 08H A 02H

Cy=1 A 0B-08-1=02 Cy=0

 INR r
• r r +1
• Where ‘r ‘ is any one of the general purpose
register such as A,B,C,D,E,H &L
• E.g INR B
• B B +1
Before Execution After Execution

B FFH INR B B 00
Cy=1
 DCR r
• r r -1
• Where ‘r ‘ is any one of the general purpose
register such as A,B,C,D,E,H &L
• E.g DCR C
• C C-1
Before Execution After Execution

C 05H DCR C C 04H

Z=0
 INX rp
• rp rp +1
• Where ‘rp ‘ is any one of the valid register pair
such as BC,DE & H L
• E.g INX H( HL HL+1), INX B (BC BC+1), INX D
(DE DE+1); N0 flags are affected
• Eg. HL HL+1
Before Execution After Execution
INX H
HL F010 HL F011
 DCX rp ( rp rp-1)
• rp rp -1 DCX D
• DCX D-->DE-2
• Where ‘rp ‘ is any one of the valid register pair
such as BC,DE & H L
• E.g DCX H( HL HL-1), DCX B (BC BC-1), DCX
D (DE DE-1); N0 flags are affected
• Eg. DCX D (DE DE-1)
After Execution
Before Execution
DCX D

DE F010 DE F00F
 Addressing methods/ Modes
• MOV A,B Source is register(operand is in general purpose
register)
• MVI r,Data(8 bit) source(data) is specified in the instruction
itself e.g. MVI B, 06H
• LDA address( 16 bit) source is memory and Address is
specified directly in the instruction e.g LDA 8000H
• MOV A, M source is memory and ,Address is not specified
directly in the instruction but register pair contents the address(
M address is in HL pair ) indirectly pointed by a register pair
• CMA Data is preloaded , most of the time it is in Acc.
• Source of operand is not specified in the instruction
• Defination of addressing Modes :
• Various ways/ formats of specifying the operand/data is known
as addressing methods or addressing Modes
 Addressing modes of 8085
• Addressing mode: of a microprocessor is the
various formats of specifying one operands
(directly, indirectly etc).
• The operand can be data (8 or 16 bit),
address, register
• Every microprocessor has its own set of
instructions.
• Each of these instructions uses one of the
addressing modes
Types of Addressing modes/methods
• The microprocessor 8085 has five addressing
modes
i) Direct addressing( address is given)
ii) Register addressing( source is general register)
iii) Immediate addressing( I- immediate or data is
specified in the instructions)
iv) Register indirect addressing (source is memory
but Register pair contents of memory)
v) Implied /Implicit addressing( data is preloaded)
 Direct addressing method
• In direct addressing, the address appears after
opcode of instruction in program memory
• The address of operand is specified within the
instruction
• The instructions using direct addressing mode are
three byte instructions.
• Byte 1 is op code of instruction, Byte 2 is lower
order address and Byte 3 is high order address
• For e.g. LDA 9FFFH
• i.e. This instruction loads accumulator with
content of memory location 9FFF H.
Register addressing Mode/Method
• In register addressing mode, the source
operands are general purpose registers whose
name is specified within the instruction
• These instructions are single byte instructions
• All actions occur within the CPU
• For e.g. MOV A, B
• This instruction transfers the content of
register B to accumulator without modifying
the content of B
Immediate addressing Mode/Method
• Immediate addressing mode :
• In immediate addressing the data appears
immediately after op code of instruction in
program memory
• In these instructions the actual data is specified
within the instruction
• These operations are specified with either 2 or
3 byte instructions
• For e.g. ADI 05H
• This instruction adds 8 bit data given in the
instruction to the contents of Acc.
Register indirect addressing Mode/Method
• In register indirect addressing the content of
register pair points to the address of the
operand.
• A register pair (H-L pair) is specified for
addressing 16-bit address of memory location
• These are generally 1-byte instruction
• For e.g. ADD M
• This instruction will add the content of
memory location whose address is stored in
HL pair to the content of accumulator.
Implicit/Implied addressing Mode/Method
• In this type of instructions, generally operand is not specified
within the instruction
• It is predetermined
• Generally the operand is accumulator
• Most of the logical group instructions belong to this
addressing mode
• These are single byte instructions
• All actions occur within the CPU
• e.g. CMA, RRC,RAR, RLC,RAL
• CMA this instruction will complement the content of
accumulator.
• Here, the actual operand is not specified in the instruction,
but is predetermined (accumulator)
• The result is stored in accumulator.
 Logical
• ORA r
Group
• ORA M Logical OR operations
• ORI data( 8 bit)
• ANA r
• ANA M Logical AND operations
• ANI data( 8 BIT)
• XRA r
• XRA M Logical XOR operations
• XRI data( 8 bit)
• CMA ---------------> 1’S Complement of Acc
• DAA----------- Decimal Adjust Accumulator
 ORA r (Logical OR Operation
• This instruction logically ORs)the content of Acc. With
register ‘r’ .The result is stored in Accumulator.
• A A V r OR A A OR r, Register addressing, 1 byte instruction

Before Execution After Execution

A 3CH A 7E H
ORA B
B 4AH OR Operation
B 4AH
ACC= 3CH 0 0 1 1 1 1 0 0
B= 4AH 0 1 0 0 1 0 1 0
ACC 7E 0 1 1 1 1 1 1 0
7 E
 ORA M (Logical OR
• Operation
This instruction logically ORs the content)of Acc with memory
contents, whose address is in HL pair. The result is stored in
Accumulator. 1 byte instruction
• A A V M OR A A OR M, Register indirect addressing,
Before Execution After Execution
A 3CH ORA M A 7E H
H L H L
60 50 60 50
6051 xx H 6051 xx H
6050 4EH 6050 4EH
MEMORY MEMORY

ACC= 3CH 0 0 1 1 1 1 0 0
M= 4EH 0 1 0 0 1 1 1 0
ACC 7E 0 1 1 1 1 1 1 0
OR Operation 7 E
 ORI data(8 bit) (Logical OR
• Operation
This instruction logically ORs the content) of Acc. With 8 bit data
specified in the instruction .The result is stored in Accumulator.
• A A V data OR A A OR data, Immediate addressing, 2 byte
instruction

Before Execution After Execution

A 3BH A BB H
ORI 8AH

OR Operation
ACC= 3BH 0 0 1 1 1 0 1 1
Data 8AH 1 0 0 0 1 0 1 0
ACC BB 1 0 1 1 1 0 1 1
B B
 ANA r (Logical AND
Operation
• This instruction logically ) of Acc. With
ANDs the content
register ‘r’ .The result is stored in Accumulator.
• A <-A ^ r OR A A AND r, Register addressing, 1 byte instruction

Before Execution After Execution

A 3DH A 18 H
ANA B
B 5AH AND Operation
B 5AH
ACC= 3DH 0 0 1 1 1 1 0 1
B= 5AH 0 1 0 1 1 0 1 0
ACC 18 0 0 0 1 1 0 0 0
1 8
 ANA M (Logical AND
• Operation
This instruction logically ANDs the content) of Acc with memory
contents, whose address is in HL pair. The result is stored in
Accumulator. 1 byte instruction
• A A V M OR A A AND M, Register indirect addressing,
Before Execution After Execution
A 3CH ANA M A 30 H
H L H L
60 50 60 50
6051 xx H 6051 xx H
6050 F0H 6050 F0H
MEMORY MEMORY

ACC= 3CH 0 0 1 1 1 1 0 0
M= F0H 1 1 1 1 0 0 0 0
ACC 30 0 0 1 1 0 0 0 0
AND Operation 3 0
 ANI data(8 bit) (Logical AND
• Operation
This instruction logically ) Acc. With 8 bit Data
ANDs the content of
specified in the instruction .The result is stored in Accumulator.

^
• A A data OR A A AND data, Immediate addressing, 2 byte
instruction

Before Execution After Execution

A 3BH A 0B H
ANI 0FH

AND Operation
ACC= 3BH 0 0 1 1 1 0 1 1
Data 0FH 0 0 0 0 1 1 1 1
ACC 0B 0 0 0 0 1 0 1 1
0 B
 ANI data(8 bit) (Logical AND
• Operation
This instruction logically ) Acc. With 8 bit Data
ANDs the content of
specified in the instruction .The result is stored in Accumulator.

^
• A A data OR A A AND data, Immediate addressing, 2 byte
instruction

Before Execution After Execution

A 3BH A 00 H
ANI 00H
Use to clear Acc
AND Operation contents
ACC= 3BH 0 0 1 1 1 0 1 1
Data 00H 0 0 0 0 0 0 0 0
ACC 00 0 0 0 0 0 0 0 0
0 0
XRA r (Logical XOR Opeation
) the content of Acc. With
• This instruction logically XORs
register ‘r’ .The result is stored in Accumulator.
• A<-A Vr OR A A XOR r, Register addressing, 1 byte instruction

Before Execution After Execution

A FEH A 34 H
XRA B
B CAH XOR Operation
B CAH
ACC= FEH 1 1 1 1 1 1 1 0
B= CAH 1 1 0 0 1 0 1 0
ACC 34 0 0 1 1 0 1 0 0
3 4
 XRA A (Logical XOR
Operation
• This instruction logically ) of Acc. With
XORs the content
register ‘r’ .The result is stored in Accumulator.
• A<-A VA OR A A XOR A, Register addressing, 1 byte instruction

Before Execution After Execution

A 8AH A 00 H
XRA A
Use to clear Acc
XOR Operation contents
ACC= 8AH 1 0 0 0 1 0 1 0
ACC= 8AH 1 0 0 0 1 0 1 0
ACC 00 0 0 0 0 0 0 0 0
0 0
 XRA M (Logical XOR
• Operation
This instruction logically XORs the content) of Acc with memory
contents, whose address is in HL pair. The result is stored in
Accumulator. 1 byte instruction
• A A V M OR A A XOR M, Register indirect addressing,
Before Execution After Execution
A 3CH XRA M A 41 H
H L H L
60 50 60 50
6051 xx H 6051 xx H
6050 7DH 6050 7DH
MEMORY MEMORY

ACC= 3CH 0 0 1 1 1 1 0 0
M= 7DH 0 1 1 1 1 1 0 1
ACC 41 0 1 0 0 0 0 0 1
XOR Operation 4 1
 XRI data(8 bit) (Logical XOR
• Operation
This instruction logically ) of Acc. With 8 bit
XORs the content
data specified in the instruction .The result is stored in
Accumulator.
• A A V data OR A A XOR data, Immediate addressing, 2 byte
instruction

Before Execution After Execution

A ABH XRI ABH A 00 H

XOR Operation
ACC= ABH 1 0 1 0 1 0 1 1
Data ABH 1 0 1 0 1 0 1 1
ACC 00 0 0 0 0 0 0 0 0
0 0
 CMA (Complement Acc.)
• This instruction complements each bit of Accumulator i.e 1 is
replaced by 0 and 0 is replaced by 1
• A A , Implied addressing method , 1 byte instruction

Before Execution After Execution

A 00H CMA A FF H

Complement Operation

ACC= 00H 0 0 0 0 0 0 0 0
ACC FF 1 1 1 1 1 1 1 1
F F
 CMA (Complement Acc.)
• This instruction complements each bit of Accumulator i.e 1 is
replaced by 0 and 0 is replaced by 1
• A A , Implied addressing method , 1 byte instruction

Before Execution After Execution

A BFH CMA A 40 H

Complement Operation

ACC= BFH 1 0 1 1 1 1 1 1
ACC 40 0 1 0 0 0 0 0 0
4 0
 DIFFERENT TYPES OF
CMP
INSTRUCTIONS

1. CMP R
2. CMP M
3. CPI data( 8 BIT)
 Compare instructions
• CMP r
Operation A – r
Output Cy flag , Z flag
• CMP M
Operation A – M
Output Cy flag , Z flag
• CPI Data( 8 bit)
Operation A – data
Output Cy flag , Z flag
 Working of CMP
instruction
Instruction Operatio Condition Flag Status
n Z= 0 Cy= 0
1) A > r Z= 0 Cy= 1
CMP r A-r 2) A < r Z= 1 Cy= 0
3) A = r Z= 0 Cy= 0
1) A > M Z= 0 Cy= 1
CMP M A - M 2) A < M Z= 1 Cy= 0
3) A = M Z= 0 Cy= 0
1) A > Z= 0 Cy= 1
CPI data A - Data data Z= 1 Cy= 0
(8 bit)
 CMP r [ A- r]
• The contents of the register ‘r’ is compared with the contents
of the accumulator. It will subtract A-r and the result of
subtraction is as follows
• The output of CMP r instruction after A-r is as follows
1. if (A) < r : CY=1 & Z =0
2. if (A) = r : CY=0 & Z = 1
3. if (A) > r : CY=0 & Z =0
4. both Acc. & r contents will remain unchanged. ’r’ is any
one of general purpose register,
Before Execution After Execution
A D3H CMP B A D3HH
B C2H B C2H
Cy=X Z=X Cy=0 Z=0
Since A > B
 CMP M [ A- M]
• The contents of memory ‘M’ whose address is pointed by HL
reg pair is compared with the contents of the accumulator. It
will subtract A-m The output of CMP M instruction is as
follows
1) if (A) < M : CY=1 & Z =0
2) if (A) = M : CY=0 & Z = 1
3) if (A) > M : CY=0 & Z =0
• both Acc. & M contents will remain unchanged
Before Execution After Execution
A 48H CMP M A 48HH
H L
H L
60 50
6051 xx H 60 50
6051 xx H
6050 74H
6050 74H
M
Cy=X Z=X Since A < M Cy=1 Z=0
 CPI data(8-bit) [A – data(8 bit)]
• The second byte being 8-bit data.
• It compares the 8 bit data with the contents of accumulator.
• The output of CMP r instruction is as follows
1. if (A) < data(8 bit) : CY=1 & Z =0
2. if (A) = data(8 bit) : CY=0 & Z = 1
3. if (A) > data(8 bit) : CY=0 & Z =0
• Example: CPI 04H
Before Execution After Execution

A 04H CPI 04H A 04H

Cy=X Z=X CY=0 Z=1

• Instruction- CPI 04H Before execution: A = 04, data=04H
After execution: A = 04H, data= 04H but As A equals to the
data byte, thus Z is set and CY flag is reset.
• CY=0, Z=1
Since A = data
 CPI data(8-bit) [A – data(8 bit)]
• The second byte being 8-bit data.
• It compares the 8 bit data with the contents of accumulator.
1) If A < 8bit data, then CY flag=1 and Zero flag=0.
2) If A > 8-bit data, then CY flag=0 and Zero flag=0.
3) If A= 8 bit data, then CY flag=0 and Zero flag =1.
• Example: CPI 04H
Before Execution After Execution

A 01H CPI 04H A 01H

Cy=X Z=X CY=1 Z=0
• Instruction- CPI 04H Before execution: A = 01, data=04H
After execution: A = 01H, data= 04H but As A < the data
byte, thus Z is reset and CY flag is set.
• CY=1, Z=0 Since A < data
 Rotate Instructions
• Right Shift- shift Acc. Bit by 1 bit position to
the right
• Right shift
a) RRC ( Rotate Acc to right without carry)
b) RAR ( Rotate Acc to right with carry)
• left Shift- shift Acc. Bit by 1 bit position to
the left
a) RLC ( Rotate Acc to left without carry)
b) RAL ( Rotate Acc to left with carry)
Note : Only Acc bits are shifted( instructions
are available with Acc Only
RRC(Rotate Right Acc. without
Carry
• This instruction rotates the contents of accumulator to the right by
one bit.
• It will shift B7 to B6, B6 to B5,............B0 to B7 as well as to carry
flag.
• Only CY flag is modified.
• It is a one byte instruction.
• Implied addressing mode is used. Before execution:

After execution:
Example of RRC
 Example of RRC Instruction
Before
• Execution If Acc.=A5H Cy
Acc
1 0 1 0 0 1 0 1 x

Acc
1 1 0 1 0 0 1 0 1

Cy
D 2
After Execution O/p Acc.=D2H
Example of RRC
RAR(Rotate Right Acc. With
Carry
• This instruction rotates the contents of accumulator to the right by
one bit along with the carry.
• It will shift B7 to B6, B6 to B5,............B0 to CY and CY to B7.
• Only CY flag is modified.
• It is a one byte instruction.
• Implied addressing mode is used.
Before execution:

After execution:
Example of RAR
 Example of RAR Instruction
Before
• Execution If Acc.=2EH, CY=1 Cy
Acc
0 0 1 0 1 1 1 0 1

Acc
1 0 0 1 0 1 1 1 0

Cy
9 7
After Execution O/p Acc.=97H
RLC(Rotate Acc. Left without
Carry
• This instruction rotates the contents of accumulator to the left by
one bit.
• It will shift B0 to B1, B1 to B2,............B7 to B0 as well as to carry
flag.
• Only CY flag is modified.
• It is a one byte instruction.
• Implied addressing mode is used.
Before execution:
• .

After execution:
Example of RLC
 Example of RLC Instruction
• Cy Before Execution If Acc.=6BH
Acc
X 0 1 1 0 1 0 1 1

0 1 1 0 1 0 1 1 0

Cy
D 6 Acc

After Execution O/p Acc.=D6H

RAL (Rotate Acc. Left with
Carry ) rotates the contents of accumulator to the left by
• This instruction
one bit along with the carry.
• It will shift B0 to B1, B1 to B2,............B7 to CY and CY to B0.
• Only CY flag is modified.
• It is a one byte instruction.
• Implied addressing mode is used.
Before execution:

After execution:
Example of RAL
 Multiplication of 04 and 03
HL =0000H, E=04H( Multiplicand),D=00H i.e. DE=0004H C=
03H( Multiplier)
First Addition ( Using DAD D
instruction )
HL =00 00 H Third Addition
+ DE= 00 04H
( using DAD D instruction )
HL= 00 04H
C=C–1 C= 03-01 i.e. C=02 HL = 00 08H
,is C=0 ?Addition ( using DAD D
Second DE= 00 04H
instruction ) HL= 00 0CH
C=C–1 C= 01-01
HL =00 04H i.e. C=00 ,is C==0 ? Yes store
DE= 00 04H produtct
HL= 00 08H
C = C – 1, C= 02-01 i.e. C=01 Thus 04 X 03 = 000C H
,is C=0 ?