Tutorial 4
CSE 112 Computer Organization
ISA description :
Instruction Format Syntax Operations
add R-type add rd, rs1, rs2 rd ← rs1 + rs2
sub R-type sub rd, rs1, rs2 rd ← rs1 − rs2
addi I-type addi rd, rs1, imm rd ← rs1 + imm
beq B-type beq rs1, rs2, label if rs1 = rs2 → PC = label
bne B-type bne rs1, rs2, label if rs1 ≠ rs2 → PC = label
Ques 1. Consider a processor based on a subset of the RISC-V instruction set. The processor
contains 32 general-purpose registers, labeled x0 to x31, where register x0 is hardwired to the
constant value zero. Each instruction occupies 4 bytes in memory, and are stored sequentially in
instruction memory. During normal execution, the Program Counter (PC) advances to the next
instruction by increasing by 4 after each instruction completes. For branch instructions, the PC is
updated to the specified target address when the branch condition evaluates to true; otherwise,
execution proceeds with the next sequential instruction. Initial architectural states are : x1 = 12,
x2 = 8, x3 = 0, x4 = 0, PC = 0x00000000.
Program:
0x00000000: add x3, x1, x2
0x00000004: addi x3, x3, -4
0x00000008: sub x4, x3, x2
0x0000000C: beq x4, x1, TARGET
0x00000010: addi x4, x4, 2
0x00000014: bne x3, x4, TARGET
0x00000018: addi x3, x3, 1
TARGET:
0x0000001C: add x4, x4, x1
(a) Show the contents of registers x3 and x4 after each executed instruction.
(b) For each branch instruction, state whether it is taken or not, and justify your answer.
(c) Show the value of the Program Counter (PC) after each instruction execution.
(d) Write the final values of registers x1, x2, x3, and x4.
Ans 1. Initially
● PC = 0x00000000
● x1 = 12, x2 = 8, x3 = 0, x4 = 0
1) 0x00000000: add x3, x1, x2
● Operation: x3 ← x1 + x2 = 12 + 8 = 20
● Next PC: PC ← PC + 4 = 0x00000004
So now:
● x3 = 20, x4 = 0
● PC = 0x00000004
2) 0x00000004: addi x3, x3, -4
● Operation: x3 ← x3 + (-4) = 20 - 4 = 16
● Next PC: PC ← 0x00000008
So now:
● x3 = 16, x4 = 0
● PC = 0x00000008
3) 0x00000008: sub x4, x3, x2
● Operation: x4 ← x3 - x2 = 16 - 8 = 8
● Next PC: PC ← 0x0000000C
So now:
● x3 = 16, x4 = 8
● PC = 0x0000000C
4) 0x0000000C: beq x4, x1, TARGET
● Compare: x4 == x1
8 == 12 → false
● Branch NOT taken
● Next PC: PC ← PC + 4 = 0x00000010
So now:
● x3 = 16, x4 = 8
● PC = 0x00000010
5) 0x00000010: addi x4, x4, 2
● Operation: x4 ← x4 + 2 = 8 + 2 = 10
● Next PC: PC ← 0x00000014
So now:
● x3 = 16, x4 = 10
● PC = 0x00000014
6) 0x00000014: bne x3, x4, TARGET
● Compare: x3 != x4
16 != 10 → true
● Branch TAKEN
● Next PC: PC ← TARGET = 0x0000001C
So now:
● x3 = 16, x4 = 10
● PC = 0x0000001C
Since branch jumps to 0x1C, instruction at 0x18 is skipped.
7) 0x0000001C: add x4, x4, x1
● Operation: x4 ← x4 + x1 = 10 + 12 = 22
● Next PC: PC ← 0x00000020
(a) Register values after each executed instruction
PC Instruction Operation x3 x4 Next PC
add x3, x1, x2 12 + 8 = 20 20 0 0x04
0x00
0x04 addi x3, x3,-4 20 − 4 = 16 16 0 0x08
0x08 sub x4, x3, x2 16 − 8 = 8 16 8 0x0C
0x0C beq x4, x1, TARGET 8 ≠ 12 → not 16 8 0x10
taken
0x10 addi x4, x4, 2 8 + 2 = 10 16 10 0x14
0x14 bne x3, x4, TARGET 16 ≠ 10 → taken 16 10 0x1C
0x1C add x4, x4, x1 10 + 12 = 22 16 22 0x20
(b) Branch decisions
● beq x4, x1, TARGET: 8 == 12 → Not Taken
● bne x3, x4, TARGET: 16 != 10 → Taken
(c) PC after each executed instruction
0x00 → 0x04 → 0x08 → 0x0C → 0x10 → 0x14 → 0x1C → 0x20
d) Final Register Values:
x1 = 12
x2 = 8
x3 = 16
x4 = 22
Ques 2. A program consists of 8× 108 instructions and is executed on two processors:
Processor A has a CPI of 1.25 and a clock frequency of 2 GHz, while Processor B has a CPI of 2.0
and a clock frequency of 3 GHz.
(a) Compute the execution time of both processors.
(b) Which processor is faster and by how much?
(c) Even though Processor B has a higher clock frequency, explain why it may still be slower.
Ans 2 a) The program executes: 8× 108 instructions
Processor A
● CPI = 1.25
● Clock frequency = 2 GHz
Clock period:
1
TA = 9 = 0.5 × 10-9 s
2×10
Execution Time = (Number of Instructions) × (CPI) × (Clock Period)
Execution time: = 8 × 108 × 1.25 × 0.5×10-9 = 0.50 seconds.
Processor B
● CPI = 2.0
● Clock frequency = 3 GHz
Clock period:
1
TB = 9 = 0.333 × 10-9 s
3×10
Execution time: = 8 × 108 × 2.0× 0.333 × 10-9 ≈ 0.533 seconds
b) Execution time on Processor A = 0.50 s
Execution time on Processor B = 0.533 s
Processor A is faster.
c) Even though Processor B has a higher clock frequency, it requires more cycles per instruction
(higher CPI). Since execution time depends on both CPI and clock period, a faster clock alone
cannot guarantee better performance.
Ques 3: A processor uses base-plus-offset addressing for memory access. The contents of
register R1 and memory are given below:
R1 = 0x6000
Memory[0x6004] = 5, Memory[0x6008] = 10, Memory[0x600C] = 15
The following instructions are executed in order:
lw R2, 4(R1)
lw R3, 8(R1)
add R2, R2, R3
lw R3, 12(R1)
add R2, R2, R3
sw R2, 16(R1)
Determine:
(a) The value stored in register R2 after each arithmetic operation.
(b) The final value written to memory at address 0x6010.
Ans3 : Given: R1 = 0x6000
Memory[0x6004] = 5, Memory[0x6008] = 10, Memory[0x600C] = 15
Instructions:
lw R2, 4(R1)
lw R3, 8(R1)
add R2, R2, R3
lw R3, 12(R1)
add R2, R2, R3
sw R2, 16(R1)
1) lw R2, 4(R1)
Address accessed: 0x6000 + 0x0004 = 0x6004
So: R2←Memory [0x6004] = 5
2) lw R3, 8(R1)
Address accessed: 0x6000 + 0x0008 = 0x6008
So: R3←Memory [0x6008] = 10
3) add R2, R2, R3
R2←R2 + R3 = 5 + 10 = 15
After the first arithmetic operation: R2 = 15
4) lw R3, 12(R1)
Address accessed: 0x6000 + 0x000C = 0x600C
So: R3←Memory [0x600C] = 15
5) add R2, R2, R3
R2←R2 + R3 = 15 + 15 = 30
After the second arithmetic operation: R2 = 30
6) sw R2, 16(R1)
Address written: 0x6000 + 0x0010 = 0x6010
Store the value of R2: Memory [0x6010]←30.
(a) Value of R2 after each arithmetic operation:
● After first add: R2 = 15
● After second add: R2 = 30
(b) Final value written to memory: Memory [0x6010] = 30
Ques 4: A processor uses base-plus-offset addressing and follows little-endian byte ordering.
The contents of register R1 and memory are given below:
R1=0x8000
Address Byte
0×8000 0×34
0×8001 0×12
0×8002 0×00
0×8003 0×00
0×8004 0×01
0×8005 0×00
0×8006 0×00
0×8007 0×00
The following instructions are executed sequentially:
lw R2, 0(R1)
lw R3, 4(R1)
add R4, R2, R3
sw R4, 8(R1)
Determine:
(a) The values loaded into R2 and R3 (in hex)
(b) The value in R4 after addition (in hex)
(c) The four bytes stored at addresses 0x8008 to 0x800B
Ans4 :
1) lw R2, 0(R1)
Address accessed: 0x8000
Bytes at 0x8000 – 0x8003 : 34 12 00 00
Little-endian means: R2 = 0x00001234
2) lw R3, 4(R1)
Address accessed: 0x8004
Bytes at 0x8004- 0x8007 : 01 00 00 00
So : R3 = 0x00000001
3) add R4, R2, R3
R4 = 0x00001234 + 0x00000001 = 0x00001235
4) sw R4, 8(R1)
Store address : 0x8000 + 0x8 = 0x8008
We store : R4 = 0x00001235
Little-endian bytes (LSB first):
Address Byte
0×8008 0×35
0×8009 0×12
0×800A 0×00
0×800B 0×00
a) R2 = 0 x 00001234, R3=0 x 00000001
b) R4 = 0 x 00001235
c) Stored bytes at 0 x 8008 - 0 x 800B : 35 12 00 00