Tutorial 2
CSE 112 Computer Organization
Topic:
We will analyze a subset of R-type instructions available in the RISC-V ISA
Semantic Explanation
add rd, rs1, rs2 Add
Add the content of the rs1 and rs2 and store the result in
rd. rd = rs1 + rs2
sub rd, rs1,rs2 Subtract
Two’s complement subtraction.
rd = rs1 - rs2.
sll rd, rs1, rs2 Shift left logical
rd = rs1 << unsigned(rs2[4:0])
Left shift rs1 by the value in lower 5 bits of rs2.
Note: Appending zeros at required places is called logical shift.
slt rd, rs1, rs2 Set if less than
rd=1. only if signed(rs1) < signed(rs2)
Note: Here we treat the register content of rs1, rs2 as signed integers.
sltu rd, rs1, rs2 Set if less than unsigned
rd=1. Only if unsigned(rs1) < unsigned(rs2)
Note: Here we treat the register content of rs1, rs2 as unsigned integers.
xor rd, rs1, rs2 Bitwise Xor
rd=rs1 ⊕ rs2
srl rd, rs1, rs2 Shift right logical
rd=rs1 >> unsigned(rs2[4:0])
Right shift rs1 by the value in the lower 5 bits of rs2.
Note: Here no sign is preserved.
or rd, rs1, rs2 Bitwise Or
rd=rs1 | rs2
and rd, rs1, rs2 Bitwise And
rd=rs1 & rs2
R-type instruction:
Format:
func7 rs2 rs1 func3 rd opcode
[31:25] [24:20] [19:15] [14:12] [11:7] [6:0]
func7 rs2 rs1 func3 rd opcode Instruction
[31:25] [24:20] [19:15] [14:12] [11:7] [6:0]
0000000 000 0110011 add
0100000 000 0110011 sub
0000000 001 0110011 sll
0000000 010 0110011 slt
0000000 011 0110011 sltu
0000000 100 0110011 xor
0000000 101 0110011 srl
0000000 110 0110011 or
0000000 111 0110011 and
Note: All registers in the above-mentioned ISA are 32-bit. Furthermore, the register “zero” is
hardwired to zero. Any read from this register provides zero; the write to this will remain
unaffected.
Questions:
Q1. What is an ISA?
Q2. The above table shows a subset of R-type Instructions available in the RISC-V ISA. Answer
the questions given below.
a) How many registers are there in the ISA as per the mentioned R-type subset?
b) What is the minimum and maximum signed and unsigned value that can be stored in any
register?
c) How many unique operations are possible in the mentioned R-type subset of RISC-V?
d) What is the size of each instruction in bits?
e) What is the role of func3 and func7 and opcode in each mentioned instruction type?
f) Why do add and sub have the same func3 but different func7?
g) What are the drawbacks and benefits of having more number of addressable registers as
per ISA?
h) Find value of r3 after the execution of every instruction mentioned below:
a) r1=0x0000_0000; r2=0x8000_0000;
i. add r3, r2, zero
ii. add zero, r1, zero
iii. add r3, r2, r1
b) r1=0x8000_0000; r2=0x8000_0000;
i. add r3, r2, r1
c) r1=0x8000_0000; r2=0x8000_0001;
i. sub r3, r2, r1
d) r1=0x0000_0030; r2=0x0000_0040;
i. sub r3, r2, r1
e) r1=0x0002_0701; r2=0x0000_0010;
i. sll r3, r1, r2
f) r1=0x0002_0701; r2=0x0000_000A;
i. sll r3, r1, r2
g) r1=0x8000_0000; r2=0x8000_0001;
i. slt r3, r2, r1
ii. slt r3, r1, r2
h) r1=0x8000_0000; r2=0x8000_0001;
i. sltu r3, r2, r1
ii. sltu r3, r1, r2
i) r1=0x0C0C_0000; r2=0xC0C0_0101;
i. xor r3, r2, r1
j) r1=0x0002_0701; r2=0x0000_000A;
i. srl r3, r1, r2
k) r1=0x0C0C_0000; r2=0xC0C0_0101;
i. or r3, r2, r1
l) r1=0x0C0C_0000; r2=0xC0C0_0101;
i. and r3, r2, r1
Note: The notation “0x0_” represents the alphabets trailing the “x” characters are hexadecimal
and “_” is added just to improve the readability.
Remark: Here is a link to look for the RISC-V ISA with a good explanation RISC-V.
Solutions:
Q1. ISA- The semantics of all the instructions supported by a processor is known as its
instruction set architecture (ISA). This includes the semantics of the instructions themselves,
along with their operands and interfaces with peripheral devices.
Q2. a) As we have only 5-bits to address each register uniquely. So, only 32 registers (general
purpose registers) are available as per the above-mentioned subset of ISA.
b) As each register is of 32 bit so,
Signed 32-bit (two’s complement):
● Max signed = 2^{31} - 1
● Min signed = -2^{31}
Unsigned 32-bit:
● Max unsigned = 2^{32} - 1
● Min unsigned = 0
c) In the mentioned R-type subset of RISC-V, the following operations are present:
add, sub, sll, slt, sltu, xor, srl, or, and.
Thus, the number of unique operations in this subset is: 9. Since each instruction performs a
distinct operation, there are 9 unique operations in the given R-type subset.
d) As per the complete instruction code format given, the size of each instruction is 32-bit.
e) Role of opcode, funct3, funct7 in the mentioned R-type instructions
● Opcode: Identifies the instruction format/type and tells the CPU this instruction belongs
to the R-type register-to-register ALU class (i.e., perform an ALU operation using two
source registers and write to a destination register).
● funct3: Selects the specific operation category inside that opcode type.
Example: It decides whether the operation is an add/sub type, shift type, compare type,
logical OR/AND/XOR type, etc.
● funct7: Acts as an extra selector used when funct3 is not enough to uniquely identify the
operation.
Example: add and sub have the same opcode and funct3, so funct7 is used to
differentiate between them.
f) As add and sub share the same opcode and funct3 because they are grouped under the same
R-type ALU operation class. Since funct3 cannot uniquely differentiate both instructions, funct7
is used as an additional field to distinguish them (0000000 for add and 0100000 for sub).
g) More registers are often beneficial, but not always.
Benefits:
● Fewer loads/stores: More values can stay in registers, reducing memory traffic.
● Better compiler optimization: More freedom for register allocation, fewer spills.
● Potentially fewer instructions: Less shuffling of values between memory and registers.
Drawbacks:
● Larger register file: More area and power, and can increase access delay.
● Timing impact: A bigger register file can become a critical path and reduce max clock.
● Encoding pressure: If instruction size is fixed (like 32-bit), supporting more architectural
registers can require bigger register fields, which would steal bits from other fields or
force a new encoding format.
So, more registers are usually good for performance, but real designs trade performance vs.
area/power/timing/encoding.
h) The values of r3 after the execution of corresponding instructions are:
a) r1=0x0000_0000; r2=0x8000_0000;
i. r3=0x8000_0000;
ii. r3=”Unchanged”. But the instruction executes properly.
iii. r3=0x8000_0000;
b) r1=0x8000_0000; r2=0x8000_0000;
i. r3=0x0000_0000; Arithmetic overflow is ignored.
c) r1=0x8000_0000; r2=0x8000_0001;
i. r3=0x0000_0001; Arithmetic overflow is ignored.
d) r1=0x0000_0030; r2=0x0000_0040;
i. r3=0x0000_0010
e) r1=0x0002_0701; r2=0x0000_0010;
i. r3=0x0701_0000
f) r1=0x0002_0701; r2=0x0000_000A;
i. r3=0x081C_0400
g) r1=0x8000_0000; r2=0x8000_0001;
i. r3=0x0000_0000
ii. r3=0x0000_0001
h) r1=0x8000_0000; r2=0x8000_0001;
i. r3=0x0000_0000
ii. r3=0x0000_0001
i) r1=0x0C0C_0000; r2=0xC0C0_0101;
i. r3=0xCCCC_0101
j) r1=0x0002_0701; r2=0x0000_000A;
i. r3=0x0000_0081
k) r1=0x0C0C_0000; r2=0xC0C0_0101;
i. r3=0xCCCC_0101
l) r1=0x0C0C_0000; r2=0xC0C0_0101;
i. r3=0x0000_0000;