Basic Processing Unit

Dr. Raghunath Dey

School of Computer Engineering

KIIT Deemed to be University, Bhubaneswar, India
Some Fundamental Concepts
• Processor fetches one instruction at a time and perform
the operation specified.
• Instructions are fetched from successive memory
locations until a branch or a jump instruction is
encountered.
• Processor keeps track of the address of the memory
location containing the next instruction to be fetched
using Program Counter (PC).
• It uses Instruction Register (IR) to keep the instruction
to be executed.
Some Fundamental Concepts

To execute an instruction the processor has the following

phases:
– Fetch Phase:
• Fetch the contents of the memory location pointed to by the PC. The
contents of this location are loaded into the IR.
IR ← [[PC]]
• Assuming that the memory is byte addressable, increment the contents
of the PC by 4.
PC ← [PC] + 4
– Execution Phase:
• Carry out the actions specified by the instruction in the IR.
Some Fundamental Concepts

• During execution of an instruction the processor does the

followings:
– Transfer a word of data from one processor register to another
or to the ALU.
– Perform an arithmetic or a logic operation and store the result in
a processor register.
– Fetch the contents of a given memory location and load them
into a processor register.
– Store a word of data from a processor register into a given
memory location.
 Some Fundamental Concepts
• The diagram shows single bus organization of the data
path inside the processor.
• Memory data register (MDR) has two inputs and two
outputs. Data may be loaded into MDR either from the
memory bus or from the internal processor bus.
Similarly the data stored in MDR may be placed on
either bus.
• The input of Memory address register (MAR) is
connected to the internal bus, and its output is
connected to the external bus.
• Three temporary registers Y, Z, TEMP are used by
processor for temporary storage during execution of
some instruction. These are never used for storing data
generated by one instruction for later use by another
instruction.
 Some Fundamental Concepts
• The multiplexer selects either the
output of register Y or constant value 4
to be provided as input A of the ALU.
• The instruction decoder and control
logic unit is responsible for
implementing the actions specified by
the instruction loaded in the IR register.
• The registers, the ALU and the
interconnecting bus are collectively
referred to as the datapath.
Register Transfers

• Instruction execution involves a sequence of steps in

which data are transferred from one register to another.
• For each register two control signals are used.
– Place the contents of register on the BUS.
– Load the data on the bus into register.
 Register Transfers
• The following diagram shows the register transfer.
• The input and output of register Ri are connected
to the bus via switches controlled by the signals
Riin and Riout respectively.
– When Riin = 1, data on the bus are loaded to Ri.
– When Riout = 1, contents of register Ri are placed on
the bus.
– When Riout = 0, BUS can be used for transferring data
from other registers.
• Example: Transfer of data from register R1 to R4
– Make R1out = 1, which places the contents of R1 on the
processor bus.
– Make R4 in = 1, which loads data from the processor
bus into register R4.
Performing an Arithmetic or Logic Operation

• ALU is a combinational circuit that

has no internal storage.
• It performs arithmetic and logic
operations on the two operands
applied to its A and B inputs.
• In the ALU, one of the operands is
the output of the multiplexer MUX
and the other operand is obtained
directly from the BUS.
 Performing an Arithmetic or Logic Operation
Example: Add the contents of R1 to R2 and store it in R3
1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in
• Step 1: Contents of R1 to be transferred over the BUS Y.
• Step 2:
– Multiplexer’s Select signal is set to SelectY, causing the multiplexer
to gate the contents of register Y to input A of the ALU.
– At the same time, the contents of register R2 are gated onto the bus
and hence to input B.
– The control line signal is set to 1 which causes the output of ALU to
be the sum of A and B.
– Sum is loaded in the register Z because its input control signal is
activated.
• Step 3: The contents of register Z are transferred to the register
R3.
Fetching a word from Memory

• To fetch a word of information from memory, the processor has to

specify the address of the memory location and request a Read
operation.
• The information may be an instruction in a program or an operand
specified in the instruction.
• The processor transfers the required address to the MAR. It also
uses the control lines of the memory bus to indicate that a Read
operation is needed.
• When the requested data are received from the memory they are
stored in register MDR from where they can be transferred to
other registers in the processor.
 Fetching a word from Memory
• MDR has four control signals:
– MDR in and MDR out control the connections to the
internal bus.
– MDR inE and MDR outE control the connections to the
external bus.
• The response time of each memory access varies
(cache miss, memory-mapped I/O,…).
• To accommodate this, the processor waits until it
receives an indication that the requested operation
has been completed through the control signal called
Memory-Function-Completed (MFC).
• When this signal is 1, it indicates that the contents of
the specified location have been read and available
in the data lines of the memory BUS.
 Fetching a word from Memory
Example: Move (R1),R2
– The actions needed to execute the instruction are:
• MAR  [R1]
• Start a Read operation on the memory bus
• Wait for the MFC response from the memory
• Load MDR from the memory bus
• R2  [MDR]
– Some these actions can be combined into a single step.
– The memory read operation requires three steps, which can be
described by the signals being activated as follows:
1. R1out, MARin, Read
2. MDRinE, WMFC
3. MDRout R2in
• WMFC is the control signal that causes the processor’s
control directory to wait for the arrival of the MFC signal.
Storing a word in Memory

• To write a word into a memory location the following procedure is

followed:
– The desired address is loaded into MAR.
– The data to be written are loaded into MDR.
– Write command is issued.
• Example: Move R2,(R1)
1. R1out, MARin
2. R2out, MDRin, Write
3. MDRout E, WMFC
– The Write control signal causes the memory bus interface hardware to
issue a Write command on the memory bus.
– The processor remains in step 3 until the memory operation is completed
and an MFC response is received.
Execution Of A Complete Instruction

• Consider the following instruction which adds the contents

of a memory location pointed to by R3 to register R1:
Add (R3), R1 [R1  [[R3]] + R1]
• Execution of the instruction requires the following actions:
– Fetch the instruction (Step 1 to 3)
– Fetch the first operand (the contents of the memory location
pointed to by R3)
– Perform the addition
– Load the result into R1
Execution Of A Complete Instruction

The following sequence of steps

required to perform these operations
for the single-bus architecture:
Step Action
1. PCout, MARin, Read, Select4, Add, Zin
2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. R3out, MARin, Read
5. R1out, Yin, WMFC
6. MDRout, SelectY, Add, Zin
7. Zout, R1in, End
Step 1: PCout, MARin, Read, Select4, Add, Zin

• The instruction fetch operation

is initiated by loading the
contents of PC into MAR and
sending a read request to the
memory.
• The Select signal is set to
Select4, which causes the
multiplexer MUX to select the
constant 4.
• Perform the addition (4 and B)
• Store the result in register Z.
Step 2: Zout, PCin, Yin, WMFC

• The value of register Z is

moved back into the PC.
• Updated content of PC is
copied to Y which is used for
computing the branch target
address if the current
instruction is a branch
instruction.
• Wait for the memory to
respond.
Step 3: MDRout, IRin

• The word fetched from

the memory is loaded
into the IR.
Step 4: R3out, MARin, Read

• The instruction
decoding circuit
interprets the contents
of IR at the beginning
of this step.
• The contents of R3 is
transferred to MAR.
• M e m o r y r e a d
operation is initiated.
Step 5: R1out, Yin, WMFC

• The contents of R1 is
transferred to register Y to
prepare the addition
operation.
• Wait for the memory to
respond.
• When the read operation
is completed, the memory
operand is available in
register MDR.
Step 6: MDRout, SelectY, Add, Zin

• The contents of the MDR

are gated to the bus and
also given to B of the ALU.
• Register Y is selected as
the second input to the
ALU by choosing SelectY.
• Addition operation is
performed.
• Result of addition is
stored in register Z.
Step 7: Zout, R1in, End

• The sum is transferred

to R1.
• The End signal causes
a new instruction fetch
cycle to begin by
returning to step 1.
Branch Instructions

• A branch instruction replaces the contents of PC with branch

target address.
• Branch target address = PC (updated value) + offset X (provided
in the branch instruction).
• Offset X used in a branch instruction is usually the difference
between the branch target address and the address immediately
following the branch instruction.
– Example:
If the branch instruction location is 2000.
Branch target address is 2050.
Then the value of X is 46.
Unconditional Branch Instruction Step Action
1. PCout, MARin, Read, Select4, Add, Zin
2. Zout, PCin, Yin, WMFC
• The table shows a control sequence that
3. MDRout, IRin
implements an unconditional branch
4. Offset-field-of-IRout, Add, Zin
instruction:
5. Zout, PCin, End
• Fetch phase ends when the instruction is
loaded into the IR in Step 3.
• The offset value is extracted from the IR by
the instruction decoding circuit.
• Since the value of the updated PC i s
already available in register Y, the offset X is
gated onto the bus in step 4 and addition is
performed.
• The result, which is branch target address,
is loaded into the PC in step 5.
Conditional Branch Instruction

• In this case we need to check the status of the

condition codes before loading a new value into
the PC.
– Example: For a Branch-on-negative (Branch<0)
instruction step 4 of the above table is replaced with:
Offset-field-of-IRout, Add, Zin, If N = 0 then End
– If N = 0, the processor returns to step 1 after step 4.
– If N = 1, step 5 is performed to load a new value into
the PC.
Example

Q1) Write the sequence of control steps for following

instructions for single bus CPU organization.
• I1: Add 10(R3),R4
• I2: Branch<0,L1
• I3: MUL –(R5),R5
• I4: CALL SUB1 //SUB1 is a subroutine
• I5: RETURN

27
Answer

28
Answer

29
Answer

30
CALL SUB1

31
RETURN

32
Multiple Bus Organization

• In a single bus organization the

control sequences are quite long
because only one data item can be
transferred over the bus in a clock
cycle.
• To reduce the number of steps
needed, CPUs provide multiple
internal paths that enable several
transfers to take place in parallel.
• The figure shows a three-bus
stru c t u r e u s e d t o c o n n e ct t h e
registers and the ALU of a
processor:
Multiple Bus Organization

• All general purpose registers are

combined into a single block called the
register file. It has three ports. Using two
ports data from two different registers can
be loaded on bus A and B. Through the
third port data from the bus C can be
loaded into a third register during the
same clock cycle.
• Buses A and B are used to transfer the
source operands to the A and B inputs of
the ALU.
• The result from the ALU is transferred to
the destination through bus C.
Multiple Bus Organization

• If needed, the ALU may simply

pass one of its two input operands
unmodified to bus C. Such
operation is called as R=A or R=B.
• The incrementer unit is used to
increment PC by 4.
• The source for the constant 4 at
the ALU input multiplier is used to
increment other addresses, such
as memory addresses in
LoadMultiple and StoreMultiple
instructions.
 Multiple Bus Organization
• Consider the following three-operand
instruction:
Add R4,R5,R6
• The control sequences for executing this
Step instructionAction
are: Explanation

 The contents of the PC are

passed through the ALU, using
the R= B control si g n a l , a n d
1. PCout, R=B, MARin, Read, IncPC loaded into the MAR.
 Memory read operation is
initiated.
 PC is incremented by 4.

 Processor waits for the MFC and

2. WMFC loads the data received into
MDR.
 Multiple Bus Organization

Step Action Explanation

 Processor transfers the data
MDRoutB, R=B,
3. from MDR to IR using the
IRin
R=B control signal.
 Contents of register R4 and
R5 is sent to the ALU through
bus A and B respectively.
R4outA, R5outB,
SelecA signal selects the
4. SelectA, Add,
value A. After addition the
R6in, End
result is transferred from the
ALU to the register R6
through bus C.
 Question
Write the control sequence for the following instructions in a multi
Bus CPU Organization. Assume R3 is the destination operand.
• ADD 50(R1), R2, R3

1. PCout, R=B, MARin, Read, IncPC

2. WMFC
3. MDRoutB, R=B, IRin
4. Offset_field_of_IRoutA, SelectA, R1outB, Add, MARin, Read
5. MDRinE, WMFC
6. R2outA, MDRoutB, Select A, Add, R3in, End

38
Generating Control Signals

• To execute instructions, the processor must have

some means of generating control signals needed
in the proper sequence.
• There are two techniques of generating control
signals:
– Hardwired Control
– Microprogrammed Control
Hardwired Control

• In the hardwired organization, the control logic is

implemented with gates, flip flops, decoders and other
digital circuits.
• Advantage:
– A controller that uses this approach can operate at high speed.
• Disadvantages:
– It has little flexibility, and the complexity of the instruction set it
can implement is limited.
– It needs changes in the wiring among the various components if
the design has to be modified or changed.
 Hardwired Control
• Consider the sequence of control
signals shown in the table.

• Each step in this sequence is completed in

one clock period.
• A counter may be used to keep track of
control steps. Each count of this counter
corresponds to one control step.
Hardwired Control

• The required control signals are

determined by the following information:
– Contents of the control step counter
– Contents of the instruction register
– Contents of the condition code flags
– External input signals, such as MFC and
interrupt requests
• The decoder/encoder block is a
combinational circuit that generates the
required control outputs, depending the
state of all its inputs.
 Block Diagram of Hardwired Control

• The detail control hardware

(block diagram) which separates
instruction encoder from decoder.
• The step decoder provides a
separate signal line for each step,
or time slot, in the control
sequence.
• The output of instruction decoder
consists of a separate line for
each machine instruction. For
any instruction loaded in the IR,
one of the output lines INS1
through INSm is set to 1, all other
lines are set to 0.
ADD instruction BR instruction
Add (R3), R1
Step Action

1. PCout, MARin, Read, Select4, Add, Zin

2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. Offset-field-of-IRout, Add, Zin
5. Zout, PCin, End

Step Action

1. PCout, MARin, Read, Select4, Add, Zin

2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. Offset-field-of-IRout, Add, Zin, If N = 0 then End

5. Zout, PCin, End

BRN instruction
 Hardwired Control

• The input signals to the encoder

block are combined to generate the
individual control signals like Y in ,
PCout, Add, End etc.
Example:
1. Generation of Zin control signal where
Zin = T1 + T6 . ADD + T4 . BR + . . .
This signal is asserted during time slot T1 for all instructions,
during T6 for ADD instructions and during T4 for
unconditional branch instructions.
2. Generation of End control signal from the logic function
End = T7 . ADD + T5 . BR + (T5 . N + T4 . �) . BRN + . . .
The End signal starts a new instruction fetch cycle by resetting
the control step counter to its starting value.
Hardwired Control

• RUN control signal:

– When RUN = 1, the counter is incremented by one at the end of every
clock cycle.
– When RUN = 0, the counter stops counting. This is needed whenever
the WMFC signal is issued to cause the processor to wait for the reply
from the memory.
• The control hardware can be viewed as a state machine:
– It changes from one state to another in every clock cycle depending on
the contents of the instruction register, the condition codes and the
external inputs.
– The output of the state machine is control signal.
Circuit Design

Circuit Design
Home Assignment-1:
Write the logic function expression and design cercuit for Zin, End, Add,
MDRout, PCin control signal with reference to above instructions i.e I1 to I3
I1: ADD 50(R1), R2, R3
I2: Branch>0,L1
I3: MUL –(R5),R5

Home Assignment-2
Write the sequence of control steps for following instructions using multibus (3
Bus) CPU organization and design the logic function for WMFC control signal
with reference to above instructions i.e I1 to I3. Draw the circuit diagram.
I1: ADD 50(R1), R2, R3
I2: Branch>0,L1
I3: MUL –(R5),R5

48
A Complete Processor

• The instruction unit fetches instruction

from an instruction cache or from
main memory when the desired
instructions are not in cache.
• Integer unit and Floating-point unit is
separated to deal integer and floating
point data separately.
• There is a data cache unit between
Integer unit / Floating-point unit and
the main memory.
 Microprogrammed Control

• In Microprogrammed Control,
the control signals are
generated by a program similar
to machine language programs.
• Control Word (CW): It is a word
whose individual bits represent
the various control signals.
– The figure shows the CWs
corresponding to the 7 steps of
single bus architecture.
 Microprogrammed Control
• A sequence of CWs
corresponding to the control
sequence of a machine
instruction constitutes the
microroutine for that instruction
and the individual control words
in this microroutine are referred
to as microinstructions.
• The microroutines for all the
instructions in the instruction set
of a computer are stored in a • The control unit can generate the control
special memory called the signals for any instruction by sequentially
control store. reading the control words of the
corresponding microroutine from the control
store.
 Organization of Microprogrammed Control Unit
• The microprogram counter is used to read the
control words sequentially from the control store.
• When a new instruction is loaded into the IR, the
output of “Starting and Branch address generator”
block is loaded into the microprogram counter.
• The microprogram counter is then automatically
incremented by the clock, causing successive
microinstructions to be read from the control store.
• When the control unit is required to check the
status of the condition codes or external inputs to
choose between alternative courses of action, it
uses conditional branch microinstructions.
 Organization of Microprogrammed Control Unit
• To allow implementation of a conditional
branch, inputs to “Starting and Branch
address generator” block consists of the
external inputs, condition codes and the
contents of the instruction register.
• The microprogrammed counter does not
increment in the following situation:
– When a new instruction is loaded into IR
– When a branch micro instruction is
encountered and the branch condition is
satisfied.
– When an End microinstruction is encountered.
 Microinstructions

• A straightforward way to
structure microinstruction is to
assign one bit position to
each control signal required in
the CPU.
• This scheme is called as
horizontal organization.
• Drawback: Assigning
individual bits to each control
signal results in long
microinstructions because the
number of required signals is
usually large.
 Microinstructions

• The length of the micro-

instructions can be reduced
easily, because:
– Most signals are not needed
simultaneously
– Many signals are mutually
exclusive
• Highly encoded schemes that
use compact codes to specify
only a small number of control
functions in each micro-
instruction are referred to as
vertical organization.
Vertical Organization
• Grouping control signals into fields
require a little more hardware,
because decoding circuits must be
used to decode the bit patterns of
each field into individual control
signals.
• In the vertical organization, each
microinstruction is represented in a
compact form.
• It uses fewer bits to encode the
control signals (which makes it
more compact), but as a result,
each control signal is encoded
using multiple bits.
Horizontal Vs Vertical Organization

Horizontal Micro-organization Vertical Micro-organization

1. Minimally encoded scheme in which 1. H i g h l y e n c o d e d s c h e m e s t h a t u s e
many resources can be controlled with compact codes to specify only a small
a single micro-instruction, is called a number of control functions in each micro-
horizontal organization. instruction are referred to as vertical
organization.

2. This scheme is useful when a higher 2. Vertical approach results in considerably

operating speed is desired and when slower operating speeds because more
the machine structure allows parallel micro-instructions are needed to perform
use of resources. the desired control functions.