Subject Name & code:
COMPUTER ORGANIZATION & ARCHITECTURE (KCA-152)
Course :
MASTER OF COMPUTER APPLICATION
Session – 2024–25
Submitted To: Submitted By:
Mr. Saurabh Singh
[Asst. Professor, CA Dept.] Course: M.C.A. 1 st Sem
Roll. No. :
Affiliated To:
DR. A.P.J. ABDUL KALAM TECHNICAL UNIVERSITY, (U.P.)
INDEX
S. PAGE.
DATE PRACTICAL SIGNATURE
NO. NO.
1. To verify truth tables of various basic gates.
Implementing HALF ADDER, FULL ADDER
2.
using basic logic gates.
Implementing HALF SUBTRACTOR, FULL
3.
SUBTRACTOR using basic logic gates.
Implementing Binary -to -Gray, Gray -to -Binary
4.
code conversions.
5. Implementing 3×8 line DECODER.
6. Implementing 8×3 line ENCODER.
7. Implementing 4×1 and 8×1 MULTIPLEXERS.
8. Implementing 1×4 and 1×8 DEMULTIPLEXERS.
To verify excitation tables of various FLIP-
9.
FLOPS.
10. Design of a 4-bit ARITHMETIC LOGIC UNIT.
EXPERIMENT NO. 1.
OBJECTIVE : To verify truth tables of various basic gates.
APPARATUS REQUIRED:
[Link]. Gates / Trainer/ Component IC No. Quantity
1. AND 7408 1
2. OR 7432 1
3. NOT 7404 1
4. NAND 7400 1
5. NOR 7402 1
6. X-OR 7486 1
7. Digital Trainer with bread board - 1
8. Connecting leads - 27
THEORY: Logic gates are idealized or physical devices implementing a Boolean function, which it performs
a logical operation on one or more logical inputs and produce a single output. Depending on the
context, the term may refer to an ideal logic gate, one that has for instance zero rise time and
unlimited fan out or it may refer to a non-ideal physical device.
1. Basic Gates : AND, OR, NOT
2. Universal Gates : NAND, NOR
3. Advanced Gates : XOR
AND gate: The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are
high. A dot (.) is used to show the AND operation i.e. A.B or can be written as AB
Y= A.B
Logic Symbol of AND Gate Truth Table of AND Gate
7408 IC Pin Diagram
OR gate: The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs
are high. A plus (+) is used to show the OR operation.
Y= A+B
Logic Symbol of OR Gate Truth Table of OR Gate
7432 IC Pin Diagram
NOT gate: The NOT gate is an electronic circuit that produces an inverted version of the input at its
output. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT
A. This is also shown as A' or A with a bar over the top, as shown at the outputs.
Y= A'
Logic Symbol of NOT Gate Truth Table of NOT Gate
7404 IC Pin Diagram
NAND gate:This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The
outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a
small circle on the output. The small circle represents inversion.
.
Y= (AB)’
Logic Symbol of NAND Gate Truth Table of NAND Gate
7400 IC Pin Diagram
NOR gate: This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs
of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on
the output. The small circle represents inversion.
Y= A+B
Logic Symbol of NOR Gate Truth Table of NOR Gate
7402 IC Pin Diagram
Ex-OR gate: The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both
of its two inputs are high. An encircled plus sign (⊕) is used to show the Ex-OR operation. Ex-OR
gate is created from AND, NAND and OR gates. The output is high only when both the inputs are
different.
Y= A⊕B
Logic Symbol of NOR Gate Truth Table of NOR Gate
7486 IC Pin Diagram
PROCEDURE:
1. Check the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Provide the input data via the input switches and observe the output on output LEDs
RESULT:
All gates are verified. Observed output matches theoretical concepts.
PRECAUTIONS:
1. All connections should be made neat and tight.
2. Digital lab kits and ICs should be handled with utmost care.
3. While making connections main voltage should be kept switched off.
4. Never touch live and naked wires.
EXPERIMENT NO. 2.
OBJECTIVE : Implementing HALF ADDER, FULL ADDER using basic logic gates.
APPARATUS REQUIRED:
[Link]. Gates / Trainer / Component IC No. Quantity
1. AND 7408 1
2. OR 7432 1
3. NOT 7404 1
4. X-OR 7486 1
5. Digital Trainer with bread board - 1
6. Patch cords - 23
THEORY :
An adder is a digital logic circuit in electronics that is extensively used for the addition of numbers. In
many computers and other types of processors, adders are even used to calculate addresses and related
activities and calculate table indices in the ALU and even utilized in other parts of the processors. These
can be built for many numerical representations like excess-3 or binary coded decimal.
Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and B, is called
a half-adder. Addition will result in two output bits; one of which is the sum bit, S, and the other is the
carry bit, C. The Boolean functions describing the half-adder are: S =A ⊕ B C = A B
Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This carry bit
from its previous stage is called carry-in bit. A combinational logic circuit that adds two data bits, A and
B, and a carry-in bit, Cin , is called a full-adder.
The Boolean functions describing the full-adder are: S = (x ⊕ y) ⊕ Cin C = xy + Cin (x ⊕ y)
i) BASIC GATE
PROCEEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:
The half adder, full adder circuits are design and constructed and verify the truth tables.
PRECAUTIONS:
• All connections should be made neat and tight.
• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.
EXPERIMENT NO. 3.
OBJECTIVE : Implementing HALF SUBTRACTOR, FULL SUBTRACTOR using basic logic gates.
APPARATUS REQUIRED:
[Link]. Gates / Trainer / Component IC No. Quantity
1. AND 7408 1
2. OR 7432 1
3. NOT 7404 1
4. X-OR 7486 1
5. Digital Trainer with bread board - 1
6. Patch cords - 23
THEORY :
The subtractor is one of the types of the combinational arithmetic circuit that generates an output which is
the subtraction of two binary numbers. Through this article on Subtractors, you will learn about half
subtractors, full subtractors with the truth tables, circuit diagram and Boolean expression.
Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A -B ) produces a
difference bit D and a borrow out bit B-out. This operation is called half subtraction and the circuit to
realize it is called a half subtractor. The Boolean functions describing the half Subtractor are: S =A ⊕ B
C = A’ B
Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit value A produces a
difference bit D and a borrow out Br bit. This is called full subtraction. The Boolean functions
describing the full-subtracter are: D = (x ⊕ y) ⊕ Cin Br= A’B + A’(Cin) + B(Cin)
PROCEEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:
The half subtractor, full subtractor circuits are design and constructed and verify the truth tables.
PRECAUTIONS:
• All connections should be made neat and tight.
• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.
EXPERIMENT NO. 4.
OBJECTIVE : Implementing Binary -to -Gray, Gray -to -Binary code conversions.
APPARATUS REQUIRED:
[Link]. Gates / Trainer / Component IC No. Quantity
1. AND 7408 1
2. OR 7432 1
3. NOT 7404 1
4. X-OR 7486 1
5. Digital Trainer with bread board - 1
6. Patch cords - 35
THEORY :
Gray Code: Gray Code is a form of binary that uses a different method of incrementing from one number to
the next. With Gray Code, only one bit changes state from one position to another. This feature allows a
system designer to perform some error checking (i.e., if more than one bit changes, the data must be
incorrect).
Gray Code is the most popular absolute encoder output type because its use prevents certain data errors that
can occur with Natural Binary during state changes. For example, in a highly capacitive circuit (or sluggish
system response), a Natural Binary state change from 0011 to 0100 could cause the counter/PLC to see 0111.
This sort of error is not possible with Gray Code, so the data is more reliable.
LOGIC DIAGRAM : Binary to Gray code Converter.
LOGIC DIAGRAM : Gray code to Binary Converter
K-map for B3
B3 = G3
K-map for B2
B2 = G3 G2
K-map for B1
K-map for B0
TRUTH TABLE:
PROCEDURE :
(i) Connections were given as per circuit diagram.
(ii) Logical inputs were given as per truth table.
(iii) Observe the logical output and verify with the truth tables.
RESULT:
The Binary to gray, Gray to binary, converter Combinational circuits are
constructed and their truth tables have been checked
PRECAUTIONS:
(i) All the ICs should be checked before use the apparatus.
(ii) All LEDs should be checked.
(iii) All connections should be tight.
(iv) Always connect GROUND first and then Vcc.
(v) The circuit should be off before change the connections.
(vi) After completing the experiment switches off the supply to apparatus
EXPERIMENT NO. 5.
OBJECTIVE : Implementing 3×8 line DECODER.
APPARATUS REQUIRED:
[Link]. Gates / Trainer / Component IC No. Quantity
1. 3 I/P AND GATE 7411 1
2. OR 7432 1
3. NOT 7404 1
4. X-OR 7486 1
5. Digital Trainer with bread board With IC 74LS138 1
6. Patch cords - 32
THEORY :
A decoder is a multiple input multiple output logic circuits which converts coded input into coded
output where input and output codes are different. The input code generally has fewer bits than the
output code. Each input code word produces a different output code word i.e. there is one to one
mapping can be expressed in truth table. In the block diagram of decoder circuit the encoded
information is present as n input producing 2n possible outputs.2n output values are from 0 through out
2n – 1.
LOGIC DIAGRAM FOR 3×8 LINE DECODER:
PINOUT OF IC 74138
TRUTH TABLE :
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:
Thus, the design and implementation of decoder and multiplexer using logic gates and study of IC
74138 has done.
PRECAUTIONS:
(i) All the ICs should be checked before use the apparatus.
(ii) All LEDs should be checked.
(iii) All connections should be tight.
(iv) Always connect GROUND first and then Vcc.
(v) The circuit should be off before change the connections.
(vi) After completing the experiment switches off the supply to apparatus.
EXPERIMENT NO. 6.
OBJECTIVE : Implementing 8×3 line ENCODER.
APPARATUS REQUIRED:
[Link]. Gates / Trainer / Component IC No. Quantity
1. AND GATE 7408 1
2. OR 7432 1
3. NOT 7404 1
4. X-OR 7486 1
5. Digital Trainer with bread board With IC 74147 1
6. Patch cords - 32
THEORY :
An encoder is a digital circuit that converts a set of binary inputs into a unique binary code. The binary
code represents the position of the input and is used to identify the specific input that is active. Encoders
are commonly used in digital systems to convert a parallel set of inputs into a serial code.
The basic principle of an encoder is to assign a unique binary code to each possible input. For example, a 2-to-4
line encoder has 2 input lines and 4 output lines and assigns a unique 4-bit binary code to each of the 2^2 = 4
possible input combinations. The output of an encoder is usually active low, meaning that only one output is
active (low) at any given time, and the remaining outputs are inactive (high). The active low output is selected
based on the binary code assigned to the active input.
LOGIC DIAGRAM FOR 8×3 LINE ENCODER:
PINOUT OF IC 74147
TRUTH TABLE :
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:
Thus, the design and implementation of encoder using logic gates and study of IC 74147 has done.
PRECAUTIONS:
(i) All the ICs should be checked before use the apparatus.
(ii) All LEDs should be checked.
(iii) All connections should be tight.
(iv) Always connect GROUND first and then Vcc.
(v) The circuit should be off before change the connections.
(vi) After completing the experiment switches off the supply to apparatus.
EXPERIMENT NO. 7.
OBJECTIVE : Implementing 4×1 MULTIPLEXERS.
APPARATUS REQUIRED:
[Link]. Gates / Trainer / Component IC No. Quantity
1. 3 I/P AND GATE 7411 2
2. OR 7432 1
3. NOT 7404 1
4. X-OR 7486 1
5. Digital Trainer with bread board With IC 74153 1
6. Patch cords - 32
THEORY :
MULTIPLEXER: Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of a
particular input line is controlled by a set of selection lines. Normally there are 2n input line and n
selection lines whose bit combination determine which input is selected
BLOCK DIAGRAM FOR 4×1 MULTIPLEXER:
FUNCTION TABLE:
LOGIC DIAGRAM FOR 4×1 MULTIPLEXER:
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:
Thus the design and implementation of decoder and multiplexer using logic gates and study of IC
74153 has done.
PRECAUTIONS:
(i) All the ICs should be checked before use the apparatus.
(ii) All LEDs should be checked.
(iii) All connections should be tight.
(iv) Always connect GROUND first and then Vcc.
(v) The circuit should be off before change the connections.
(vi) After completing the experiment switches off the supply to apparatus.
EXPERIMENT NO. 8.
OBJECTIVE : Implementing 1×4 and 1×8 DEMULTIPLEXERS.
APPARATUS REQUIRED:
[Link]. Gates / Trainer / Component IC No. Quantity
1. 3 I/P AND GATE 7411 2
2. OR 7432 1
3. NOT 7404 1
4. X-OR 7486 1
5. Digital Trainer with bread board With IC 74138 / 74139 1
6. Patch cords - 32
THEORY :
DEMULTIPLEXER: A demultiplexer (DEMUX) performs the reverse operation of a multiplexer. It
takes input from one line and distributes it to a given number of output lines. It is also known as a data
distributor. A demultiplexer with 2n output lines should have n data-selector lines.
BLOCK DIAGRAM FOR 1×4 DEMULTIPLEXER:
FUNCTION TABLE:
Data Selector Outputs
S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 I
0 1 0 0 1 0
1 0 0 I 0 0
1 1 I 0 0 0
The logical expression can be derived from the truth table.
Y_3=S_1S_0I
Y_2=S_1\overline{S_0}I
Y_1=\overline{S_1}S_0I
Y_0=\overline{S_1}\overline{S_0}I
LOGIC DIAGRAM FOR 1×4 DEMULTIPLEXER:
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:
Thus the design and implementation of demultiplexer using logic gates and study of IC 74138 / 74139
has done.
PRECAUTIONS:
(i) All the ICs should be checked before use the apparatus.
(ii) All LEDs should be checked.
(iii) All connections should be tight.
(iv) Always connect GROUND first and then Vcc.
(v) The circuit should be off before change the connections.
(vi) After completing the experiment switches off the supply to apparatus.
EXPERIMENT NO. 9.
OBJECTIVE : To verify excitation tables of various FLIP-FLOPS.
APPARATUS REQUIRED:
[Link]. Gates / Trainer / Component IC No. Quantity
1. AND GATE 7408 2
2. NOR GATE 7402 2
3. NAND GATE 7400 2
4. NOT GATE 7404 1
5. Digital Trainer with bread board With IC 7410 1
6. Patch cords - 32
THEORY :
In case of sequential circuits, the effect of all previous inputs on the outputs is represented by a state
of the circuit. Thus, the output of the circuit at any time depends upon its current state and the input.
These also determine the next state of the circuit. The relationship that exists among the inputs,
outputs, present states and next states can be specified by either the state table or the state diagram.
State Table: The state table representation of a sequential circuit consists of three sections labelled
present state next state and output. The present state designates the state of flip - flops before the
occurrence of a clock pulse. The next state shows the states of flip -flop s after the clock pulse,
and the output section lists the value of the output variables during the present state.
Flip-Flop: The basic one bit digital memory circuit is known as flip-flop. It can store either 0 or 1.
Flip-flops are classifieds according to the number of inputs.
R-S Flip-Flop: The circuit is similar to SR latch except enable signal is replaced by clock pulse.
Logic Diagram for S-R flip flop
Characteristic table for S-R flip flop
S R Qn Q(n+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 X
D Flip-Flop: The modified clocked SR flip- flop is known as D-flip-flop. From the truth table of SR flip - flop
we see that the output of the SR flip-flop is in unpredictable state when the inputs are same and
high. In many practical applications, these input conditions are not required. These input
conditions can be avoided by making then complement of each other.
Logic Diagram for D flip flop
Characteristic table for D flip flop
J-K Flip-Flop: In a RS flip-flop the input R=S=1 leads to an indeterminate output. The RS flip-flop circuit
may be re-joined if both inputs are 1 than also the outputs are complement of each other.
Logic Diagram for J-K flip flop
Characteristic table for J-K flip flop
T Flip-Flop: it is known as toggle flip-flop. The T flip-flop is modification of the J-K flip - flop . Both the J
K inputs of the J K flip - flop are held at logic 1 and the clock signal continuous to change.
Logic Diagram for T flip flop
Characteristic table for T flip flop
Qn T Qn+1
0 0 0
0 1 1
1 0 1
1 1 0
PROCEDURE:
1. Connections are made as per circuit diagram.
2. Verify truth-tables for various combinations of input.
RESULT:
Study and verified truth-tables of various flip-flops.
PRECAUTIONS:
(i) All the ICs should be checked before use the apparatus.
(ii) All LEDs should be checked.
(iii) All connections should be tight.
(iv) Always connect GROUND first and then Vcc.
(v) The circuit should be off before change the connections.
(vi) After completing the experiment switches off the supply to apparatus.
EXPERIMENT NO. 10.
OBJECTIVE : Design of a 4-bit ARITHMETIC LOGIC UNIT.
APPARATUS REQUIRED:
1. IC 74181
2. Digital trainer
3. Connecting leads
4. Power supply
5. Multi-meter
THEORY :
In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical
operations. The ALU is a fundamental building block of the central processing unit (CPU). ALU
stands for the arithmetic and logical unit and is one of the important units in almost all the calculating
machine these days be it with the hand-held mobile, or computers. All the computational work in the
system is carried out by this unit. The typical ALU sizes are:
4-bit ALU: ALU that processes two 4-bit numbers.
8-bit ALU: ALU that processes two 8-bit numbers.
When the size of 4-bit ALU is to be increased to 8-bit operations two 74181 can be cascaded and
Cn+4 will be used as input to Cn line of next stage.
LOGIC DIAGRAM : Experimental circuit diagram of ALU IC-74181
Pinning Diagram of ALU IC-74181 :
Connection diagram & pin description of ALU IC-74181:
Cascading of ALU IC-74181:
Block Digram of ALU :
Internal Architecture of ALU IC 74181:
Function tables of ALU IC-74181:
PROCEDURE:
As seen in figure-3, the ALU has two 4-bit input lines A3-A0, B3-B0, a 4-bit function select lines S3-
S0, one mode select line ‘M’ that is used to select ALU for either arithmetic or the logical function. It
has four output lines f3-f0, carry-in Cn is used in cascade mode. When the size of 4-bit ALU is to be
increased to 8-bit operations two 74181 can be cascaded and Cn+4 will be used as input to Cn line of
next stage.
1. Connections are made as shown in fig
2. Change the values of the inputs and verify at least 5 functions given in the function table.
RESULT:
The above circuit when connected to power supply gives correct result as per the function table.
PRECAUTIONS:
1. All the IC’s should be checked before use the apparatus.
2. All LED’s should be checked.
3. All connections should be tight.
4. Always connect GROUND first and then Vcc
5. The circuit should be off before change the connections.
6. After completing the experiment switches off the supply to apparatus.