a LC2MOS

16-Bit A/D Converter

AD7701
FEATURES FUNCTIONAL BLOCK DIAGRAM
Monolithic 16-Bit ADC
0.0015% Linearity Error AVDD DVDD AVSS DVSS SC1 SC2

On-Chip Self-Calibration Circuitry 14 15 7 6 4 17

Programmable Low-Pass Filter AD7701

0.1 Hz to 10 Hz Corner Frequency CALIBRATION CALIBRATION
0 V to +2.5 V or 62.5 V Analog Input Range SRAM MICROCONTROLLER 13 CAL

4 kSPS Output Data Rate

Flexible Serial Interface AIN 9 16-BIT A/D CONVERTER
12 BP/UP
Ultralow Power 6-POLE GAUSSIAN
ANALOG LOW-PASS
VREF 10 MODULATOR DIGITAL FILTER
APPLICATIONS 11 SLEEP

Industrial Process Control

Weigh Scales AGND 8
CLOCK 20 SDATA
Portable Instrumentation GENERATOR
SERIAL INTERFACE
LOGIC
19 SCLK
Remote Data Acquisition DGND 5

3 2 1 16 18

CLKIN CLKOUT MODE CS DRDY

GENERAL DESCRIPTION PRODUCT HIGHLIGHTS

The AD7701 is a 16-bit ADC which uses a sigma-delta conver- 1. The AD7701 offers 16-bit resolution coupled with outstand-
sion technique. The analog input is continuously sampled by an ing 0.0015% accuracy.
analog modulator whose mean output duty cycle is proportional 2. No missing codes ensures true, usable, 16-bit dynamic range,
to the input signal. The modulator output is processed by an removing the need for programmable gain and level-setting
on-chip digital filter with a six-pole Gaussian response, which circuitry.
updates the output data register with 16-bit binary words at
word rates up to 4 kHz. The sampling rate, filter corner fre- 3. The effects of temperature drift are eliminated by on-chip
quency and output word rate are set by a master clock input self-calibration, which removes zero and gain error. External
that may be supplied externally, or by a crystal-controlled on- circuits can also be included in the calibration loop to
chip clock oscillator. remove system offsets and gain errors.
The inherent linearity of the ADC is excellent, and endpoint 4. A flexible synchronous/asynchronous interface allows the
accuracy is ensured by self-calibration of zero and full scale AD7701 to interface directly to UARTs or to the serial ports
which may be initiated at any time. The self-calibration scheme of industry-standard microcontrollers.
can also be extended to null system offset and gain errors in the 5. Low operating power consumption and an ultralow power
input channel. standby mode make the AD7701 ideal for loop-powered
The output data is accessed through a flexible serial port, which remote sensing applications, or battery-powered portable
has an asynchronous mode compatible with UARTs and two instruments.
synchronous modes suitable for interfacing to shift registers or
the serial ports of industry-standard microcontrollers.
CMOS construction insures low power dissipation, and a power
down mode reduces the idle power consumption to only 10 µW.

REV. D
Information furnished by Analog Devices is believed to be accurate and © Analog Devices, Inc., 1996
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
 (TA = +258C; AVDD = DVDD = +5 V; AVSS = DVSS = –5 V; VREF = +2.5 V; fCLKIN =
4.096 MHz; Bipolar Mode: MODE = +5 V; AIN Source Resistance = 1k V1 with 1 nF to
AD7701–SPECIFICATIONS AGND at AIN, unless otherwise noted.)

Parameter A, S Versions2 B, T Versions2 Units Test Conditions/Comments

STATIC PERFORMANCE
Resolution 16 16 Bits
Integral Nonlinearity
TMIN to TMAX ± 0.0007 % FSR typ
± 0.003 ± 0.0015 % FSR max
Differential Nonlinearity
TMIN to TMAX ± 0.125 ± 0.125 LSB typ Guaranteed No Missing Codes
± 0.5 ± 0.5 LSB max
Positive Full-Scale Error3 ± 0.13 ± 0.13 LSB typ
± 0.5 ± 0.5 LSB max
Full-Scale Drift4 ± 1.2 (± 2.3 S Version) ± 1.2 (± 2.3 T Version) LSB typ
Unipolar Offset Error3 ± 0.25 ± 0.25 LSB typ
±1 ±1 LSB max
Unipolar Offset Drift4 ± 1.6 (+3/–25 S Version) ± 1.6 (+3/–25 T Version) LSB typ
Bipolar Zero Error3 ± 0.25 ± 0.25 LSB typ
±1 ±1 LSB max
Bipolar Zero Drift4 ± 0.8 (+1.5/–12.5 S Version) ± 0.8 (+1.5/–12.5 T Version) LSB typ
Bipolar Negative Full-Scale Error3 ± 0.5 ± 0.5 LSB typ
±2 ±2 LSB max
Bipolar Negative Full-Scale Drift4 ± 0.6 (± 1.2 S Version) ± 0.6 (± 1.2 T Version) LSB typ
Noise (Referred to Output) 0.1 0.1 LSB rms typ

DYNAMIC PERFORMANCE
Sampling Frequency, fS fCLKIN/256 fCLKIN/256 Hz
Output Update Rate, fOUT fCLKIN/1024 fCLKIN/1024 Hz
Filter Corner Frequency, f –3 dB fCLKIN/409,600 fCLKIN/409,600 Hz
Settling Time to ± 0.0007% FS 507904/fCLKIN 507904/fCLKIN sec For Full-Scale Input Step

SYSTEM CALIBRATION Applies to Unipolar and

Positive Full-Scale Overrange VREF + 0.1 VREF + 0.1 V max Bipolar Ranges. After Cali-
Positive Full-Scale Overrange VREF + 0.1 VREF + 0.1 V max bration, If AIN > VREF, the
Negative Full-Scale Overrange –(VREF + 0.1) –(VREF + 0.1) V max Device Will Output All 1s
Maximum Offset Calibration Range5, 6 If AIN < 0 (Unipolar) or
Unipolar Input Range –(VREF + 0.1) –(VREF + 0.1) V max –VREF (Bipolar), the Device
Bipolar Input Range –0.4 VREF to +0.4 VREF –0.4 VREF to +0.4 VREF V max Will Output All 0s.
Input Span7 0.8 VREF 0.8 VREF V min
2 VREF + 0.2 2 VREF + 0.2 V max

ANALOG INPUT
Unipolar Input Range 0 to +2.5 0 to +2.5 Volts
Bipolar Input Range ± 2.5 ± 2.5 Volts
Input Capacitance 10 10 pF typ
Input Bias Current1 1 1 nA typ

LOGIC INPUTS
All Inputs Except CLKIN
VINL, Input Low Voltage 0.8 0.8 V max
VINH, Input High Voltage 2.0 2.0 V min
CLKIN
VINL, Input Low Voltage 0.8 0.8 V max
VINH, Input High Voltage 3.5 3.5 V min
IIN, Input Current 10 10 µA max

LOGIC OUTPUTS
VOL, Output Low Voltage 0.4 0.4 V max ISINK = 1.6 mA
VOH, Output High Voltage DVDD – 1 DVDD – 1 V min ISOURCE = 100 µA
Floating State Leakage Current ± 10 ± 10 µA max
Floating State Output Capacitance 9 9 pF typ

–2– REV. D
 AD7701
Parameter A, S Versions2 B, T Versions2 Units Test Conditions/Comments

POWER REQUIREMENTS8
Power Supply Voltages
Analog Positive Supply (AVDD) 4.5/5.5 4.5/5.5 V min/V max
Digital Positive Supply (DVDD) 4.5/AVDD 4.5/AVDD V min/V max
Analog Negative Supply (AVSS) –4.5/–5.5 –4.5/–5.5 V min/V max
Digital Negative Supply (DVSS) –4.5/–5.5 –4.5/–5.5 V min/V max
Calibration Memory Retention
Power Supply Voltage 2.0 2.0 V min
DC Power Supply Currents8
Analog Positive Supply (AIDD) 3.2 3.2 mA max Typically 2 mA
Digital Positive Supply (DIDD) 1.5 1.5 mA max Typically 1 mA
Analog Negative Supply (AISS) 3.2 3.2 mA max Typically 2 mA
Digital Negative Supply (DISS) 0.1 0.1 mA max Typically 0.03 mA
Power Supply Rejection9
Positive Supplies 70 70 dB typ
Negative Supplies 75 75 dB typ
Power Dissipation
Normal Operation 40 40 mW max SLEEP = Logic 1,
Typically 25 mW
Standby Operation10 20 (40 S Version) 20 (40 T Version) µW max SLEEP = Logic 0,
Typically 10 µW
NOTES
11
The AIN pin presents a very high impedance dynamic load which varies with clock frequency.
12
Temperature ranges are as follows: A, B Versions; –40°C to +85°C; S, T Versions; –55°C to +125°C.
13
Apply after calibration at the temperature of interest. Full-scale error applies for both unipolar and bipolar input ranges.
14
Total drift over the specified temperature range since calibration at power-up at +25 °C. This is guaranteed by design and/or characterization. Recalibration at any
temperature will remove these errors.
15
In unipolar mode the offset can have a negative value (–VREF) such that the unipolar mode can mimic bipolar mode operation.
16
The specifications for input overrange and for input span apply additional constraints on the offset calibration range.
17
For unipolar mode, input span is the difference between full scale and zero scale. For bipolar mode, input span is the difference between positive and negative
full-scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of ± (VREF +0.1)
18
All digital outputs unloaded. All digital inputs at 5 V CMOS levels.
19
Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter.
10
CLKIN is stopped. All digital inputs are grounded.
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS 1 Industrial Cerdip (A, B Versions) . . . . . . . –40°C to +85°C

(TA = +25°C unless otherwise noted) Extended Cerdip (S, T Versions) . . . . . . –55°C to +125°C
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
DVDD to AVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
DVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V NOTES
1
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
Digital Input Voltage to DGND . . . . –0.3 V to DVDD +0.3 V operation of the device at these or any other conditions above those listed in the
Analog Input operational sections of this specification is not implied. Exposure to absolute
Voltage to AGND . . . . . . . . AVSS – 0.3 V to AVDD + 0.3 V maximum rating conditions for extended periods may affect device reliability.
Input Current to Any Pin Except Supplies2 . . . . . . . . ± 10 mA
2
Transient currents of up to 100 mA will not cause SCR latch-up.
Operating Temperature Range
Commercial Plastic (A, B Versions) . . . . . –40°C to +85°C

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although this device features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

REV. D –3–
AD7701
PIN FUNCTION DESCRIPTION
Pin Mnemonic Description
1 MODE Selects the Serial Interface Mode. If MODE is tied to –5 V, the AD7701 will operate in the asynchronous
communications (ac) mode. The SCLK pin is configured as an input, and data is transmitted in two bytes,
each with one start bit and two stop bits. If MODE is tied to DGND, the synchronous external clocking
(SEC) mode is selected. SCLK is configured as an input, and the output appears without formatting, the
MSB coming first. If MODE is tied to +5 V, the AD7701 operates in the synchronous self-clocking (SSC)
mode. SCLK is configured as an output, with a clock frequency of fCLKlN/4 and 25% duty-cycle.
2 CLKOUT Clock Output to generate an Internal Master Clock by connecting a crystal between CLKOUT and CLKIN.
If an external clock is used, CLKOUT is not connected.
3 CLKIN Clock Input for External Clock.
4, 17 SC1, SC2 System Calibration Pins. The state of these pins, when CAL is taken high, determines the type of calibration
performed.
5 DGND Digital Ground. Ground reference for all digital signals.
6 DVSS Digital Negative Supply, –5 V nominal.
7 AVSS Analog Negative Supply, –5 V nominal.
8 AGND Analog Ground. Ground reference for all analog signals.
9 AIN Analog Input.
10 VREF Voltage Reference Input, +2.5 V nominal. This determines the value of positive full-scale in the unipolar
mode and of both positive and negative full-scale in the bipolar mode.
11 SLEEP Sleep mode pin. When this pin is taken low, the AD7701 goes into a low-power mode with typically 10 µW
power consumption.
12 BP/UP Bipolar/Unipolar Mode Pin. When this pin is low, the AD7701 is configured for a unipolar input range going
from AGND to VREF. When Pin 12 is high, the AD7701 is configured for a bipolar input range, ± VREF.
13 CAL Calibration Mode Pin. When CAL is taken high for more than 4 cycles, the AD7701 is reset and performs a
calibration cycle when CAL is brought low again. The CAL pin can also be used as a strobe to synchronize
the operation of several AD7701s.
14 AVDD Analog Positive Supply, +5 V nominal.
15 DVDD Digital Positive Supply, +5 V nominal.
16 CS Chip Select Input. When CS is brought low, the AD7701 will begin to transmit serial data in a format deter-
mined by the state of the MODE pin.
18 DRDY Data Ready output. DRDY is low when valid data is available in the output register. It goes high after transmission
of a word is completed. It also goes high for four clock cycles when a new data word is being loaded into the out-
put register, to indicate that valid data is not available, irrespective of whether data transmission is complete or not.
19 SCLK Serial Clock Input/Output. The SCLK pin in configured as an input or output, dependent on the type of se-
rial data transmission that has been selected by the MODE pin. When configured as an output in the syn-
chronous self-clocking mode, it has a frequency of fCLKIN/4 and a duty cycle of 25%.
20 SDATA Serial Data Output. The AD7701’s output data is available at this pin as a 16-bit serial word. The transmis-
sion format is determined by the state of the MODE pin.

PIN CONFIGURATIONS ORDERING GUIDE

DIP, Cerdip, SOIC SSOP Temperature Linearity Package
Model Range Error (% FSR) Options*
MODE 1 20 SDATA MODE 1 28 SDATA
CLKOUT 2 19 SCLK CLKOUT 2 27 SCLK
AD7701AN –40°C to +85°C 0.003 N-20
CLKIN 3 18 DRDY CLKIN 3 26 DRDY
17 SC2
AD7701BN –40°C to +85°C 0.0015 N-20
SC1 4 SC1 4 25 SC2

DGND 5
AD7701
16 CS DGND 5 24 CS
AD7701AR –40°C to +85°C 0.003 R-20
TOP VIEW
DVSS 6 (Not to Scale) 15 DVDD NC 6 23 NC AD7701BR –40°C to +85°C 0.0015 R-20
AVSS 7 14 AVDD NC 7
AD7701 22 NC AD7701ARS –40°C to +85°C 0.003 RS-28
TOP VIEW
AGND 8 13 CAL DVSS 8
(Not to Scale)
21 NC
AD7701AQ –40°C to +85°C 0.003 Q-20
AIN 9 12 BP/UP NC 9 20 DVDD
AD7701BQ –40°C to +85°C 0.0015 Q-20
VREF 10 11 SLEEP AVSS 10 19 AVDD
NC 11 18 NC
AD7701SQ –55°C to +125°C 0.003 Q-20
AGND 12 17 CAL AD7701TQ –55°C to +125°C 0.0015 Q-20
AIN 13 16 BP/UP
VREF 14 15 SLEEP
NOTES
*N = Plastic DIP; Q = Cerdip; R = SOIC; RS = SSOP.
NC = NO CONNECT

–4– REV. D
 AD7701
(AVDD = DVDD = +5 V 6 10%; AVSS = DVSS = –5 V 6 10%; AGND = DGND = O V;
TIMING CHARACTERISTICS1, 2 f CLKIN = 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DVDD)

Limit at TMIN, TMAX Limit at TMIN, TMAX

Parameter (A, B Versions) (S, T Versions) Units Conditions/Comments
fCLKIN3, 4 200 200 kHz min Master Clock Frequency: Internal Gate Oscillator
5 5 MHz max Typically 4.096 MHz
200 200 kHz min Master Clock Frequency: Externally Supplied
5 5 MHz max
tr5 50 50 ns max Digital Output Rise Time. Typically 20 ns
tf5 50 50 ns max Digital Output Fall Time. Typically 20 ns
t1 0 0 ns min SC1, SC2 to CAL High Setup Time
t2 50 50 ns min SC1, SC2 Hold Time After CAL Goes High
t3 6 1000 1000 ns min SLEEP High to CLKIN High Setup Time
SSC Mode
t4 7 3/fCLKIN 3/fCLKIN ns max Data Access Time (CS Low to Data Valid)
t5 100 100 ns max SCLK Falling Edge to Data Valid Delay (25 ns typ)
t6 250 250 ns min MSB Data Setup Time. Typically 380 ns
t7 300 300 ns max SCLK High Pulse Width. Typically 240 ns
t8 790 790 ns max SCLK Low Pulse Width. Typically 730 ns
t9 8 l/fCLKIN +200 l/fCLKIN +200 ns max SCLK Rising Edge to Hi-Z Delay (l/fCLKIN + 100 ns typ)
t108, 9 (4/fCLKIN) +200 (4/fCLKIN) +200 ns max CS High to Hi-Z Delay
SEC Mode
fSCLK 5 5 MHz Serial Clock Input Frequency
t11 35 35 ns min SCLK Input High Pulse Width
t12 160 160 ns min SCLK Low Pulse Width
t137, 10 160 160 ns max Data Access Time (CS Low to Data Valid). Typically 80 ns
t1411 150 150 ns max SCLK Falling Edge to Data Valid Delay. Typically 75 ns
t158 250 250 ns max CS High to Hi-Z Delay
t168 200 200 ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns
AC Mode
t17 40 40 ns min CS Setup Time. Typically 20 ns
t18 180 180 ns max Data Delay Time. Typically 90 ns
t19 200 200 ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns
NOTES
11
Sample tested at +25°C to ensure compliance. All input signals are specified with t r = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
12
See Figures 1 to 6.
13
CLKIN Duty Cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7701 is not in SLEEP mode. If no clock is present in this case, the device can
draw higher current than specified and possibly become uncalibrated.
14
The AD7701 is production tested with f CLKIN at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.
15
Specified using 10% and 90% points on waveform of interest.
16
In order to synchronize several AD7701s together using the SLEEP pin, this specification is met.
17
t4 and t13 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
18
t9, t10, t15 and t16 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is
then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is the
true bus relinquish time of the part and as such as independent of external bus loading capacitance.
19
If CS is returned high before all 16 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.
10
If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be as
great as 4 CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high sooner than
4 CLKIN cycles plus 160 ns after CS goes low.
11
SDATA is clocked out on the falling edge of the SCLK input.

REV. D –5–
AD7701
I OL
1.6mA
CAL
TO CLKIN
OUTPUT +2.1V t1 t2
PIN CL t3
100pF
SC1, SC2 SC1,SC2 VALID
I OH SLEEP
200µA

Figure 1. Load Circuit for Access Figure 2a. Calibration Control Timing Figure 2b. SLEEP Mode Timing
Time and Bus Relinquish Time
DRDY

CS
CS
CS
t12
t15 t11
t10
HI-Z SCLK
DATA
HI-Z SDATA
DATA VALID t13 t16
SDATA
VALID t14
HI-Z HI-Z
SDATA DB15 DB14 DB1 DB0

Figure 3. SSC Mode Data Hold Figure 4a. SEC Mode Data Hold Time Figure 4b. SEC Mode Timing Diagram
Time

CLKIN

DRDY
CS

t7 CS
t8 t17
HI-Z
SCLK
SCLK
t4 t9 t18 t19
t6 START
t5 HI-Z HI-Z
SDATA DB8 DB9 DB7 STOP 1 STOP 2
HI-Z HI-Z
SDATA DB15 DB14 DB1 DB0 HIGH BYTE LOW BYTE

Figure 5. SSC Mode Timing Diagram Figure 6. AC Mode Timing Diagram

TERMINOLOGY
LINEARITY ERROR BIPOLAR ZERO ERROR
This is the maximum deviation of any code from a straight line This is the deviation of the midscale transition (0111 . . . 111 to
passing through the endpoints of the transfer function. The 1000 . . . 000) from the ideal (AGND – 0.5 LSB) when
endpoints of the transfer function are Zero-Scale (not to be operating in the bipolar mode. It is expressed in microvolts.
confused with Bipolar Zero), a point 0.5 LSB below the first
code transition (000 . . . 000 to 000 . . . 001) and Full-Scale, a BIPOLAR NEGATIVE FULL-SCALE ERROR
point 1.5 LSB above the last code transition (111 . . . 110 to This is the deviation of the first code transition from the ideal
111 . . . 111). The error is expressed as a percentage of full (–VREF + 0.5 LSB), when operating in the bipolar mode. It is
scale. expressed in microvolts.

DIFFERENTIAL LINEARITY ERROR POSITIVE FULL-SCALE OVERRANGE

This is the difference between any code’s actual width and the Positive Full-Scale Overrange is the amount of overhead avail-
ideal (1 LSB) width. Differential Linearity Error is expressed in able to handle input voltages greater than +VREF ( for example,
LSBs. A differential linearity specification of ± 1 LSB or less noise peaks or excess voltages due to system gain errors in
guarantees monotonicity. system calibration routines) without introducing errors due to
overloading the analog modulator or overflowing the digital
POSITIVE FULL-SCALE ERROR filter. It is expressed in millivolts.
Positive Full-Scale Error is the deviation of the last code
transition (111 . . . 110 to 111 . . . 111) from the ideal (VREF NEGATIVE FULL-SCALE OVERRANGE
–3/2 LSBs). It applies to both positive and negative analog input This is the amount of overhead available to handle voltages
ranges and it is expressed in microvolts. below –VREF without overloading the analog modulator or
overflowing the digital filter. Note that the analog input will
UNIPOLAR OFFSET ERROR accept negative voltage peaks even in the unipolar mode. The
Unipolar Offset Error is the deviation of the first code transition overhead is expressed in millivolts.
from the ideal (AGND + 0.5 LSB) when operating in the uni-
polar mode. It is expressed in microvolts.
–6– REV. D
 AD7701
OFFSET CALIBRATION RANGE The AD7701 can perform self-calibration using the on-chip
In the system calibration modes (SC2 low) the AD7701 calibration microcontroller and SRAM to store calibration
calibrates its offset with respect to the AIN pin. The Offset parameters. A calibration cycle may be initiated at any time
Calibration Range specification defines the range of voltages, using the CAL control input.
expressed as a percentage of VREF that the AD7701 can accept
Other system components may also be included in the
and still calibrate offset accurately.
calibration loop to remove offset and gain errors in the input
channel.
FULL-SCALE CALIBRATION RANGE
This is the range of voltages that the AD7701 can accept in the For battery operation, the AD7701 also offers a standby mode
system calibration mode and still calibrate full-scale correctly. that reduces idle power consumption to typically 10 µW.

INPUT SPAN THEORY OF OPERATION

In system calibration schemes, two voltages applied in sequence The general block diagram of a sigma-delta ADC is shown in
to the AD7701’s analog input define the analog input range. Figure 8. It contains the following elements.
The input span specification defines the minimum and maxi- 1. A sample-hold amplifier.
mum input voltages from zero to full-scale that the AD7701 can
2. A differential amplifier or subtracter.
accept and still calibrate gain accurately. The input span is ex-
pressed as a percentage of VREF. 3. An analog low-pass filter.
4. A 1-bit A/D converter (comparator).
GENERAL DESCRIPTION
The AD7701 is a 16-bit A/D converter with on-chip digital 5. A 1-bit DAC.
filtering, intended for the measurement of wide dynamic range, 6. A digital low-pass filter.
low frequency signals such as those representing chemical, In operation, the analog signal sample is fed to the subtracter,
physical or biological processes. It contains a charge-balancing along with the output of the 1-bit DAC. The filtered difference
(sigma-delta) ADC, calibration microcontroller with on-chip signal is fed to the comparator, whose output samples the
static RAM, a clock oscillator and a serial communications port. difference signal at a frequency many times that of the analog
The analog input signal to the AD7701 is continuously sampled signal sampling frequency (oversampling).
at a rate determined by the frequency of the master clock,
S/H AMP
CLKIN. A charge-balancing A/D converter (Sigma-Delta COMPARATOR
Modulator) converts the sampled signal into a digital pulse train ANALOG
LOW-PASS
whose duty cycle contains the digital information. A six-pole DIGITAL
FILTER
FILTER
Gaussian digital low-pass filter processes the output of the
modulator and updates the 16-bit output register at a 4 kHz
DIGITAL DATA
rate. The output data can be read from the serial port randomly DAC

or periodically at any rate up to 4 kHz.

+5V
ANALOG
Figure 8. General Sigma-Delta ADC
SUPPLY
0.1µF 10µF Oversampling is fundamental to the operation of sigma-delta
ADCs. Using the quantization noise formula for an ADC:
AVDD DVDD
0.1µF SNR = (6.02 × number of bits + 1.76) dB
VOLTAGE 2.5V SLEEP
REFERENCE VREF a 1-bit ADC or comparator yields an SNR of 7.78 dB.
MODE
DATA
DRDY READY The AD7701 samples the input signal at 16 kHz, which spreads
CS
READ the quantization noise from 0 to 8 kHz. Since the specified
RANGE BP/UP (TRANSMIT)
SELECT
SERIAL
analog input bandwidth of the AD7701 is only 0 to 10 Hz, the
SCLK CLOCK noise energy in this bandwidth would be only 1/800 of the total
CALIBRATE CAL SERIAL
SDATA
DATA quantization noise, even if the noise energy was spread evenly
AD7701 throughout the spectrum. It is reduced still further by analog
CLKIN filtering in the modulator loop, which shapes the quantization
ANALOG AIN
INPUT
CLKOUT
noise spectrum to move most of the noise energy to frequencies
SC1
above 10 Hz. The SNR performance in the 0 to 10 Hz range is
SC2
conditioned to the 16-bit level in this fashion.
ANALOG
GROUND AGND
0.1µF
DGND The output of the comparator provides the digital input for the
0.1µF
AVSS DVSS 1-bit DAC, so that the system functions as a negative feedback
loop that tries to minimize the difference signal. The digital data
–5V
ANALOG that represents the analog input voltage is contained in the duty
SUPPLY 0.1µF
10µF cycle of the pulse train appearing at the output of the compara-
tor. It can be retrieved as a parallel binary data word using a
digital filter.

Figure 7. Typical System Connection Diagram

REV. D –7–
AD7701
Sigma-delta ADCs are generally described by the order of the FILTER CHARACTERISTICS
analog low-pass filter. A simple example of a first order sigma- The cutoff frequency of the digital filter is fCLK /409600. At the
delta ADC is shown in Figure 9. This contains only a first-order maximum clock frequency of 4.096 MHz, the cutoff frequency
low-pass filter or integrator. It also illustrates the derivation of of the filter is 10 Hz and the output rate is 4 kHz.
the alternative name for these devices: Charge-Balancing ADCs.
Figure 10 shows the filter frequency response. This is a 6-pole
C Gaussian response that provides 55 dB of 60 Hz rejection for a
CLOCK
10 Hz cutoff frequency. If the clock frequency is halved to give a
R
AIN
5 Hz cutoff, 60 Hz rejection is better than 90 dB. A normalized
s-domain pole-zero plot of the filter is shown in Figure 11.
TO DIGITAL
FILTER
The response of the filter is defined by:
INTEGRATOR
STROBED
COMPARATOR
H(x) = [1+ 0.693x2 + 0.240x4 + 0.0555x6 + 0.00962x8
R + 0.00133x10 + 0.000154x12] –0.5
+VREF
where:
x = f/f3 dB, f3 dB = fCLKIN/409600,
–VREF
and
1-BIT DAC
f is the frequency of interest.
Figure 9. SEC Basic Charge-Balancing ADC 20

The term charge-balancing comes from the fact that this system 0
is a negative feedback loop that tries to keep the net charge on fCLK = 4MHz
–20
the integrator capacitor at zero, by balancing charge injected by
the input voltage with charge injected by the 1-bit DAC. When –40
the analog input is zero, the only contribution to the integrator
GAIN – dBs

–60 fCLK = 2MHz

output comes from the 1-bit DAC. For the net charge on the
integrator capacitor to be zero, the DAC output must spend half –80
its time at +1 V and half its time at –1 V. Assuming ideal
–100
components, the duty cycle of the comparator will be 50%.
–120
When a positive analog input is applied, the output of the 1-bit fCLK = 1MHz
DAC must spend a larger proportion of the time at +1 V, so the –140
duty cycle of the comparator increases. When a negative input
–160
voltage is applied, the duty cycle decreases. 1 10 100
FREQUENCY – Hz
The AD7701 uses a second-order sigma-delta modulator and a
Figure 10. Frequency Response of AD7701 Filter
sophisticated digital filter that provides a rolling average of the
sampled output. After power-up or if there is a step change in jw
the input voltage, there is a settling time that must elapse before j2

valid data is obtained.

j1
DIGITAL FILTERING
S1,2 = –1.4663 + j1.8191
The AD7701’s digital filter behaves like a similar analog filter, s
0 S3,4 = –1.7553 + j1.0005
with a few minor differences. –2 –1
S5,6 = –1.8739 + j0.32272
First, since digital filtering occurs after the A to D conversion
process, it can remove noise injected during the conversion –j1

process. Analog filtering cannot do this.

On the other hand, analog filtering can remove noise super- –j2
imposed on the analog signal before it reaches the ADC. Digital
filtering cannot do this and noise peaks riding on signals near Figure 11. Normalized Pole-Zero Plot of AD7701 Filter
full scale have the potential to saturate the analog modulator Since the AD7701 contains this on-chip, low-pass filtering,
and digital filter, even though the average value of the signal is there is a settling time associated with step function inputs, and
within limits. To alleviate this problem, the AD7701 has over- data will be invalid after a step change until the settling time has
range headroom built into the sigma-delta modulator and digital elapsed. The AD7701 is therefore unsuitable for high speed
filter which allows overrange excursions of 100 mV. If noise multiplexing, where channels are switched and converted se-
signals are larger than this, consideration should be given to quentially at high rates, as switching between channels can
analog input filtering, or to reducing the gain in the input cause a step change in the input. Rather, it is intended for dis-
channel so that a full-scale input (2.5 V) gives only a half-scale tributed converter systems using one ADC per channel.
input to the AD7701 (1.25 V). This will provide an overrange
capability greater than 100% at the expense of reducing the However, slow multiplexing of the AD7701 is possible, provided
dynamic range by 1 bit (50%). that the settling time is allowed to elapse before data for the new
channel is accessed.

–8– REV. D
 AD7701
The output settling of the AD7701 in response to a step input The input sampling frequency, output data rate, filter character-
change is shown in Figure 12. The Gaussian response has fast istics and calibration time are all directly related to the master
settling with no overshoot, and the worst-case settling time to clock frequency fCLKIN by the ratios given in the specification
± 0.0007% (± 0.5 LSB) is 125 ms with a 4.096 MHz master table. Therefore, the first step in system design with the
clock frequency. AD7701 is to select a master clock frequency suitable for the
bandwidth and output data rate required by the application.
ANALOG INPUT RANGES
100
The AD7701 performs conversion relative to an externally
PERCENT OF FINAL VALUE

80
supplied reference voltage, which allows easy interfacing to
ratiometric systems. In addition, either unipolar or bipolar input
60
voltage range may be selected using the BP/UP input. With BP/
UP tied low, the input range is unipolar and the span is 0 to
40 +VREF. With BP/UP tied high, the input range is bipolar and the
span is ± VREF. In the bipolar mode both positive and negative
20 full scale are directly determined by VREF. This offers superior
tracking of positive and negative full scale and better midscale
0 (bipolar zero) stability than bipolar schemes that simply scale
0 40 80 120 160
TIME – ms
and offset the input range.
The digital output coding for the unipolar range is Unipolar
Figure 12. AD7701 Step Response
Binary; for the bipolar range it is Offset Binary. Bit weights for
the unipolar and bipolar modes are shown in Table I. The input
USING THE AD7701
voltages and output codes for unipolar and bipolar ranges, using
SYSTEM DESIGN CONSIDERATIONS
the recommended +2.5 V reference, are shown in Table II.
The AD7701 operates differently from successive approxima-
tion ADCs or other integrating ADCs. Since it samples the sig-
Table I. Bit Weight Table (2.5 V Reference Voltage)
nal continuously, like a tracking ADC, there is no need for a
start convert command. The 16-bit output register is updated at Unipolar Mode Bipolar Mode
a 4 kHz rate, and the output can be read at any time, either syn-
chronously or asynchronously. mV LSBs % FS ppm FS LSBs % FS ppm FS
CLOCKING 10 0.26 0.0004 4 0.13 0.0002 2
The AD7701 requires a master clock input, which may be an 19 0.5 0.0008 8 0.26 0.0004 4
external TTL/CMOS compatible clock signal applied to the 38 1.00 0.0015 15 0.5 0.0008 8
CLKIN pin (CLKOUT not used). Alternatively, a crystal of the 76 2.00 0.0031 31 1.00 0.0015 15
correct frequency can be connected between CLKIN and 153 4.00 0.0061 61 2.00 0.0031 31
CLKOUT, when the clock circuit will function as a crystal-
controlled oscillator.
Table II. Output Coding

Unipolar Mode Bipolar Mode

Input Relative to Input in Volts Input Relative to Input in Volts Output Data
FS and AGND FS and AGND
1111 1111 1111 1111
+VREF – 1.5 LSB +2.499943 +VREF – 1.5 LSB +2.499886
1111 1111 1111 1110
+VREF – 2.5 LSB +2.499905 +VREF – 2.5 LSB +2.499810
1111 1111 1111 1101
+VREF – 3.5 LSB +2.499867 +VREF – 3.5 LSB +2.499733
1111 1111 1111 1100

1000 0000 0000 0001

+VREF/2 + 0.5 LSB +1.250019 AGND + 0.5 LSB +0.000038
1000 0000 0000 0000
+VREF/2 – 0.5 LSB +1.249981 AGND – 0.5 LSB –0.000038
0111 1111 1111 1111
+VREF/2 – 1.5 LSB +1.249943 AGND – 1.5 LSB –0.000114
0111 1111 1111 1110

0000 0000 0000 0011

AGND + 2.5 LSB +0.000095 –VREF + 2.5 LSB –2.499810
0000 0000 0000 0010
AGND + 1.5 LSB +0.000057 –VREF + 1.5 LSB –2.499886
0000 0000 0000 0001
AGND + 0.5 LSB +0.000019 –VREF + 0.5 LSB –2.499962
0000 0000 0000 0000
NOTES
1
VREF = +2.5 V
2
AGND = 0 V
3
Unipolar Mode, 1 LSB = 2.5 V/655536 = 0.000038 V
4
Bipolar Mode, 1 LSB = 5 V/65536 = 0.000076 V
5
Inputs are voltages at code transitions.

REV. D –9–
AD7701
INPUT SIGNAL CONDITIONING An RC filter may be added in front of the AD7701 to reduce
Reference voltages from +1 V to +3 V may be used with the high frequency noise. With an external capacitor added from
AD7701, with little degradation in performance. Input ranges AIN to AGND, the following equation will specify the maximum
that cannot be accommodated by this range of reference voltages allowable source resistance:
may be achieved by input signal conditioning. This may take the
form of gain to accommodate a smaller signal range, or passive 62
RS (Max) =
attenuation to reduce a larger input voltage range.  100 mV × C IN / (C IN + C EXT ) 
f CLKIN × ( C IN + C EXT ) × ln  
Source Resistance  VE 
If passive attenuators are used in front of the AD7701, care
must be taken to ensure that the source impedance is suffi- The practical limit to the maximum value of source resistance is
ciently low. The AD7701 has an analog input with over 1 GΩ thermal (Johnson) noise. A practical resistor may be modeled as
dc input resistance. In parallel with this there as a small dy- an ideal (noiseless) resistor in series with a noise voltage source
namic load which varies with the clock frequency (see Figure or in parallel with a noise current source.
13). Each time the analog input is sampled, a 10 pF capacitor Vn = √4 kTRf Volts
draws a charge packet of maximum 1 pC (10 pF × 100 mV)
in = √4 kTf / R Amperes

R1 AIN
where:
k is Boltzmann’s constant (1.38 × 10–23 J/K)
AD7701
and
R2 CEXT T is temperature in degrees Kelvin (°C + 273).
CIN Active signal conditioning circuits such as op amps generally do
10pF
VOS ≤100mV
not suffer from problems of high source impedance. Their open
loop output resistance is normally only tens of ohms and, in any
AGND
case, most modern general purpose op amps have sufficiently
fast closed loop settling time for this not to be a problem. Offset
Figure 13. Equivalent Input Circuit and Input Attenuator voltage in op amps can be eliminated in a system calibration
routine. With the wide dynamic range and small LSB size of the
from the analog source with a frequency fCLKIN/256. For a AD7701, noise can also be a problem, but the digital filter will
4.096 MHz CLKIN, this yields an average current draw of reject most broadband noise above its cutoff frequency. How-
16 nA. After each sample the AD7701 allows 62 clock periods ever, in certain applications there may be a need for analog
for the input voltage to settle. The equation which defines input filtering.
settling time is:
Antialias Considerations
VO = VIN [1 – e–t/RC] The digital filter of the AD7701 does not provide any rejection
where: at integer multiples of the sampling frequency (nfCLKlN/256,
VO is the final settled value, where n = 1, 2, 3 . . . ).
VIN is the value of the input signal, With a 4.096 MHz master clock there are narrow (± 10 Hz)
R is the value of the input source resistance, bands at 16 kHz, 32 kHz, 48 kHz, etc., where noise passes
C is the 10 pF sample capacitor, unattenuated to the output.
t is equal to 62/fCLKIN. However, due to the AD7701’s high oversampling ratio of 800
From this, the following equation can be developed which gives (16 kHz to 20 Hz) these bands occupy only a small fraction of
the maximum allowable source resistance, RS(MAX), for an error the spectrum, and most broadband noise is filtered. The
of VE: reduction in broadband noise is given by:

62 eOUT = eIN 2 f C / f S = 0.035 eIN

RS (MAX ) =
f CLKIN ×(10 pF ) × l n (100mV /VE )
where:
Provided the source resistance is less than this value, the analog elN and eOUT are rms noise terms referred to the input
input will settle within the desired error band in the requisite 62 fC is the filter –3 dB corner frequency
clock periods. Insufficient settling leads to offset errors. These (fCLKIN/409600)
can be calibrated in system calibration schemes.
and
If a limit of 10 µV (0.25 LSB at 16 bits) is set for the maximum
offset voltage, then the maximum allowable source resistance is fS is the sampling frequency (fCLKIN/256).
160 kΩ from the above equation, assuming that there is no Since the ratio of fS to fCLKIN is fixed, the digital filter reduces
external stray capacitance. broadband white noise by 96.5% independent of the master
clock frequency.

–10– REV. D
 AD7701
VOLTAGE REFERENCE CONNECTIONS GROUNDING AND SUPPLY DECOUPLING
The voltage applied to the VREF pin defines the analog input AGND is the ground reference voltage for the AD7701, and is
range. The specified reference voltage is 2.5 V, but the AD7701 completely independent of DGND. Any noise riding on the
will operate with reference voltages from 1 V to 3 V with little AGND input with respect to the system analog ground will
degradation in performance. cause conversion errors. AGND should therefore be used as the
The reference input presents exactly the same dynamic load as system ground and also as the ground for the analog input and
the analog input, but in the case of the reference input, source the reference voltage.
resistance and long settling time introduce gain errors rather The analog and digital power supplies to the AD7701 are
than offset errors. Fortunately, most precision references have independent and separately pinned out, to minimize coupling
sufficiently low output impedance and wide enough bandwidth between analog and digital sections of the device. The digital
to settle to 10 µV within 62 clock cycles. filter will provide rejections of broadband noise on the power
supplies, except at integer multiples of the sampling frequency.
+5V AVDD
Therefore, the two analog supplies should be decoupled to
AGND using 100 nF ceramic capacitors to provide power
LT1019 supply noise rejections at these frequencies. The two digital
AD7701
supplies should similarly be decoupled to DGND.
VREF
ACCURACY AND AUTOCALIBRATION
Sigma-delta ADCs, like VFCs and other integrating ADCs, do
AGND not contain any source of nonmonotonicity and inherently offer
no-missing-codes performance. The AD7701 achieves excellent
linearity (± 0.0007%) by the use of high quality, on-chip silicon
Figure 14. Typical External Reference Connections
dioxide capacitors, which have a very low capacitance/voltage
The digital filter of the AD7701 removes noise from the coefficient.
reference input, just as it does with noise at the analog input,
The AD7701 offers two self-calibration modes using the on-chip
and the same limitations apply regarding lack of noise rejection
calibration microcontroller and SRAM. Table III is a truth table
at integer multiples of the sampling frequency. If reference noise
for the calibration control inputs SC1 and SC2.
is a problem, some voltage references offer noise reduction
schemes using an external capacitor. Alternatively, a simple RC In the self-calibration mode, zero-scale is calibrated against the
filter may be used, as shown in Figure 15. AGND pin and full scale is calibrated against the VREF pin, to
remove internal errors.
+5V AVDD Note that in the bipolar mode the AD7701 calibrates positive
AD580 full scale and midscale (bipolar zero).
RF AD7701 In the system-calibration mode, the AD7701 calibrates its zero
13kΩ
VREF
and full scale to voltages present on the analog input pin in two
CF
sequential steps. This allows system offsets and/or gain errors to
100pF be nulled out.
AGND
MICRO
AD7701 COMPUTER

Figure 15. Filtered Reference Input SYSTEM SCLK

REF HI
SDATA
The same considerations apply to this filter as to a filter at the ANALOG CAL
AIN MUX SIGNAL
analog input. In this case: CONDITIONING SC1
SYSTEM A0 A1 SC2
REF LO
62
[RF (CF +10 pF )]=
100 mV × CIN (CIN + CF ) 
f CLKIN × ln  
 V FSE 
Figure 16. Typical Connections for System Calibration
where: A typical system calibration scheme is shown in Figure 16. In
fCLKIN is the master clock frequency normal operation the analog signal is fed to the AD7701 via an
analog multiplexer. When the system is to be calibrated, AIN is
and
first switched to the system REF LO via the multiplexer and
VFSE is the maximum desired error in volts. CAL is strobed high, with SC1 and SC2 both high. AIN is then
switched to the system REF HI and CAL is strobed, with SC1
low and SC2 high. In this way, the effect of all error sources

REV. D –11–
AD7701
Table III. Calibration Truth Table

CAL SC1 SC2 CAL TYPE ZERO REFERENCE FS REFERENCE SEQUENCE CALIBRATION TIME
0 0 Self-Cal AGND VREF One Step 3,145,655 Clock Cycles
1 1 System Offset AIN – 1st Step 1,052,599 Clock Cycles
0 1 System Gain – AIN 2nd Step 1,068,813 Clock Cycles
1 0 System Offset AIN VREF One Step 2,117,389 Clock Cycles
NOTE
DRDY remains high throughout the calibration sequence. In the Self-Cal mode, DRDY falls once the AD7701 has settled to the analog input. In all other modes
DRDY falls as the device begins to settle.

between the multiplexer and the AD7701 is removed. Op amps The type of calibration cycle initiated by CAL is determined by
and other signal conditioning circuits may be used in front of the SC1 and SC2 inputs, in accordance with Table III.
the AD7701, without worrying about their absolute gain or The power dissipation and temperature drift of the AD7701 are
offset errors. Note that the absolute value of the reference low and no warm-up time is required before the initial calibra-
supplied to the AD7701 is no longer important, provided it has tion is performed. However, the system reference must have
adequate short-term stability between calibration cycles, as full stabilized before calibration is initiated.
scale is calibrated to the system reference.
If system offset errors are important but system gain errors are POWER SUPPLY SEQUENCING
not, then a one step system calibration may be performed with The positive digital supply (DVDD) must never exceed the
SC1 high and SC2 low. In this case, offset is calibrated against positive analog supply (AVDD) by more than 0.3 V. Power
AIN, which should be connected to system REF LO during supply sequencing is therefore important. If separate analog and
calibration, but full scale is calibrated against the AD7701’s digital supplies are used, care must be taken to ensure that the
VREF input. analog supply is powered up first.
System calibration schemes will yield better accuracy than self- It is also important that power is applied to the AD7701 before
calibration, even if there are no system errors. Using self- signals at VREF, AIN or the logic input pins in order to avoid any
calibration, errors arise due to the mismatch in source impedances possibility of latch-up. If separate supplies are used for the
between the references during calibration (AGND and VREF) AD7701 and the system digital circuitry, then the AD7701
and the analog input during normal operation. In system cali- should be powered up first.
bration, the source impedances inherently remain identical, A typical scheme for powering the AD7701 from a single set of
such that the theoretical limit to system accuracy is calibration ± 5 V rails is shown in the system connection diagram, Figure 7.
resolution. The practical limit is the noise floor of the AD7701. In this circuit AVDD and DVDD are brought along separate
Note that in system calibration, “REF LO” does not necessarily tracks from the same +5 V supply. Thus, there is no possibility
mean the system ground or zero volts. The AD7701 can be of the digital supply coming up before the analog supply.
calibrated to measure between any two voltages that lie within
its calibration range by deliberately making REF LO nonzero. GROUNDING
For example, if REF LO is +0.5 V and REF HI is +2.5 V, the The AD7701 uses the analog ground connection, AGND, as the
unipolar span will be between these limits. measurement reference node. It should be used as the reference
node for both the analog input signal and the reference voltage
CALIBRATION RANGE at the VREF pin.
When designing system calibration schemes, care must be taken The analog and digital power supplies to the AD7701 die are
to ensure that the worst-case system errors do not cause the pinned out separately to minimize coupling between the analog
overrange headroom of the AD7701 to be exceeded. Although and digital sections of the chip. All four supplies should be
the measurement error caused by offset and gain errors can be decoupled separately to their respective grounds as shown in
nulled out, the actual error voltages will still be present at the Figure 7. The on-chip digital filtering of the AD7701 further
analog input and can cause overloading of the analog modulator enhances power supply rejection by attenuating noise injected
or overflow of the digital filter. With a 2.5 V reference, the into the conversion process.
maximum input voltage is (+VREF + 100 mV), and the minimum
input voltage is (–VREF – 100 mV). SINGLE SUPPLY OPERATION
Figure 17 shows a circuit to power the AD7701 from a single
POWER-UP AND CALIBRATION +10 V supply, using an op amp to provide a half supply refer-
A calibration cycle must be carried out after power-up to initial- ence point for AGND and DGND. As the digital I/O pins are
ize the device to a consistent starting condition and correct cali- referenced to this point, level shifting is required for external
bration. The CAL pin must be held high for at least four clock digital communications. If galvanic isolation is required in the
cycles, after which calibration is initiated on the falling edge of system, level shifting and isolation can both be provided by
CAL and takes a maximum of 3,145,655 clock cycles (approxi- opto-isolators.
mately 768 ms, with a 4.096 MHz clock). See Table III.

–12– REV. D
 AD7701
SYNCHRONOUS SELF-CLOCKING MODE (SSC)
0.1µF
The SSC mode (MODE pin high) allows easy interfacing to
serial-parallel conversion circuits in systems with parallel data
0.1µF AVDD DVDD
10kΩ
communication. This mode allows interfacing to 74XX299
REF VREF Universal Shift registers without any additional decoding. The
AD7701 SSC mode can also be used with microprocessors such as the
AD707 DGND 68HC11 and 68HC05, which allow an external device to clock
10V ± 1V
their serial port.
AGND Figure 18 shows the timing diagram for the SSC mode. Data is
10kΩ 0.1µF
AVSS DVSS clocked out by an internally generated serial clock. The AD7701
divides each sampling interval into sixteen distinct periods.
0.1µF
Eight periods of 64 clock pulses are for analog settling and eight
periods of 64 clock pulses are for digital computation. The
status of CS is polled at the beginning of each digital computation
Figure 17. Single Supply Operation
period. If it is low at any of these times then SCLK will become
active and the data word currently in the output register will be
SLEEP MODE
transmitted, MSB first. After the LSB has been transmitted
The low power standby mode is initiated by taking the SLEEP
DRDY goes high and SDATA goes three-state. If CS, having
input low, which shuts down all analog and digital circuits and
been brought low, is taken high again at any time during data
reduces power consumption to 10 µW. The calibration coeffi-
transmission, SDATA and SCLK will go three-state after the
cients are still retained in memory, but as the converter has been
current bit finishes. If CS is subsequently brought low,
quiescent, it is necessary to wait for the filter settling time
transmission will resume with the next bit during the sub-
(507,904 cycles) before accessing the output data.
sequent digital computation period. If transmission has not been
initiated and completed by the time the next data word is
DIGITAL INTERFACE
available, DRDY will go high for four clock cycles then low
The AD7701’s serial communications port allows easy inter-
again as the new word is loaded into the output register.
facing to industry-standard microprocessors. Three different
modes of operations are available, optimized for different types A more detailed diagram of the data transmission in the SSC
of interface. mode is shown in Figure 19. Data bits change on the falling
edge of SCLK and are valid on the rising edge of SCLK.

1024 CLKIN CYCLES

64 CLKIN CYCLES 64 CLKIN CYCLES

INTERNAL
STATUS ANALOG SETTLING DIGITAL COMPUTATION DIGITAL COMPUTATION

72 CLKIN CYCLES

DRDY (O)

CS POLLED
CS (I)

HI-Z HI-Z
SCLK (O)

HI-Z MSB LSB HI-Z

SDATA (O)

Figure 18. Timing Diagram for SSC Data Transmission Mode

REV. D –13–
AD7701
SYNCHRONOUS EXTERNAL CLOCK MODE (SEC) If CS is taken high at any time during data transmission,
The SEC mode (MODE pin grounded) is designed for direct SDATA and SCLK will go three-state immediately. If CS re-
interface to the synchronous serial ports of industry-standard turns low, the AD7701 will continue transmission with the same
microprocessors such as the COPS series, 68HC11 and data bit. If transmission has not been initiated and completed by
68HC05. The SEC mode also allows customized interfaces, the time the next data word becomes available, and if CS is
using I/O port pins, to microprocessors that do not have a direct high, DRDY will return high for four clock cycles, then fall as
fit with the AD7701’s other modes. the new word is loaded into the output register.
As shown in Figure 20, a falling edge on CS enables the serial
data output with the MSB initially valid. Subsequent data bits
change on the falling edge of an externally supplied SCLK.
After the LSB has been transmitted, DRDY goes high and
SDATA goes three-state. If CS is low and the AD7701 is still
transmitting data when a new data word becomes available, the
old data word continues to be transmitted and the new data is
lost.

CLKIN (I)

72 CLKIN
CYCLES
DRDY (O)

CS (I)

HI-Z HI-Z
SDATA (O) DB15 (MSB) DB14 DB2 DB1 DB0 (LSB)

HI-Z HI-Z
SCLK (O)

Figure 19. SSC Mode Showing Data Timing Relative to SCLK

DRDY (O)

CS (I)

SCLK (I)

HI-Z DB15 DB0 HI-Z

SDATA (O) DB14 DB13 DB1
(MSB) (LSB)

Figure 20. Timing Diagram for the SEC Mode

–14– REV. D
 AD7701
ASYNCHRONOUS COMMUNICATIONS (AC) MODE DIGITAL NOISE AND OUTPUT LOADING
The AC mode (MODE pin tied to –5 V) offers a UART- As mentioned earlier, the AD7701 divides its internal timing
compatible interface which allows the AD7701 to transmit data into two distinct phases, analog sampling and settling and digital
asynchronously from remote locations. An external SCLK sets computation. In the SSC mode, data is transmitted only during
the baud rate and data is transmitted in two bytes in UART- the digital computation periods, to minimize the effects of
compatible format. Using the AC mode, the AD7701 can be digital noise on analog performance. In the SEC and AC modes
interfaced direct to microprocessors with UART interfaces, such data transmission is externally controlled, so this automatic
as the 8051 and TMS70X2. safeguard does not exist.
Data transmission is initiated by CS going low. If CS is low on a Whatever mode of operation is used, resistive and capacitive
falling edge of SCLK, the AD7701 begins transmitting an 8-bit loads on digital outputs should be minimized in order to reduce
data byte (DB8–DB15) with one start bit and two stop bits, as crosstalk between analog and digital portions of the circuit. For
in Figure 21. The SDATA output will then go three-state. The this reason connection to low-power CMOS logic such as one of
second byte is transmitted by bringing CS low again and DB0 to the 4000 series or 74C families is recommended.
DB7 are transmitted in the same format as the first byte. It is especially important to minimize the load on SDATA in the
UART baud rates are typically low compared to the AD7701’s AC mode, as transmission in this mode is inherently asynchro-
4 kHz output update rate. If CS is low and data is still being nous. In the SEC mode the AD7701 should be synchronized to
transmitted when a new data word becomes available, the new the digital system clock via CLKIN.
data will be ignored. However, if CS has been taken high
between bytes, when a new data word becomes available, the
AD7701 could update the output register before the second byte
is transmitted. In this case, the UART would receive the first
byte of the new word instead of the second byte of the old word.
When using the AC mode, care must obviously be taken to
ensure that this does not occur.

SCLK (I)

DRDY (O)

CS (I)

HI-Z START STOP STOP START

SDATA (O) DB8 DB9 DB14 DB15 DB0 DB1 DB6 DB7 STOP STOP
BIT BIT BIT BIT BIT BIT

Figure 21. Timing Diagram for Asynchronous Communications Mode

REV. D –15–
AD7701
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

20-Pin Plastic DIP (N-20) 20-Lead SOIC (R-20)

C1432b–2–9/96
20 11
0.280 (7.11) 20 11
PIN 1 0.240 (6.10)
1 10 0.2992 (7.60)
0.2914 (7.40)

1.060 (26.90) 0.325 (8.25) 0.4193 (10.65)

0.925 (23.50) 0.300 (7.62) 0.3937 (10.00)
0.060 (1.52) PIN 1
1 10
0.210 0.015 (0.38) 0.195 (4.95)
(5.33) 0.115 (2.93)
MAX
0.130 0.1043 (2.65)
0.160 (4.06) (3.30) 0.015 (0.381)
0.5118 (13.00) 0.0926 (2.35)
0.115 (2.93) MIN 0.008 (0.204) 0.0291 (0.74)
0.4961 (12.60) x 45 °
0.0098 (0.25)

0.022 (0.558) 0.100 0.070 (1.77) SEATING

0.014 (0.356) (2.54) 0.045 (1.15) PLANE
BSC
8° 0.0500 (1.27)
0.0118 (0.30) 0.0500 0.0192 (0.49) 0° 0.0157 (0.40)
0.0125 (0.32)
0.0040 (0.10) (1.27)
0.0138 (0.35) 0.0091 (0.23)
BSC

20-Pin Cerdip (Q-20) 28-Lead SSOP

(RS-28)
0.005 (0.13) MIN 0.098 (2.49) MAX

0.407 (10.34)
20 11 0.397 (10.08)
0.310 (7.87)
PIN 1
0.220 (5.59)
1 10
28 15

0.212 (5.38)
0.205 (5.21)
0.301 (7.64)
0.311 (7.9)

0.320 (8.13)
1.060 (26.92) MAX 0.290 (7.37)
0.060 (1.52)
0.200 0.015 (0.38)
(5.08)
MAX 1 14
0.150 0.015 (0.38)
0.200 (5.08) (3.81)
0.008 (0.20)
0.125 (3.18) MIN
15 ° 0.078 (1.98) PIN 1 0.07 (1.79)
0.023 (0.58) 0.100 0.070 (1.78) 0° 0.068 (1.73) 0.066 (1.67)
(2.54) SEATING
0.014 (0.36) 0.030 (0.76)
BSC PLANE

8° 0.03 (0.762)
0.008 (0.203) 0.0256 0.015 (0.38)
SEATING 0.009 (0.229)
0° 0.022 (0.558)
(0.65) 0.010 (0.25)
0.002 (0.050) BSC PLANE
0.005 (0.127)

PRINTED IN U.S.A.

–16– REV. D