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Practical 2

The document outlines the implementation of odd and even parity generator circuits for binary error detection. It describes the theory behind parity bits, provides a truth table for a 3-bit even and odd parity generator, and details the procedure for developing and verifying the circuit. The document includes circuit diagrams and emphasizes the importance of parity in ensuring data integrity during transmission.

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malharvala20
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7 views2 pages

Practical 2

The document outlines the implementation of odd and even parity generator circuits for binary error detection. It describes the theory behind parity bits, provides a truth table for a 3-bit even and odd parity generator, and details the procedure for developing and verifying the circuit. The document includes circuit diagrams and emphasizes the importance of parity in ensuring data integrity during transmission.

Uploaded by

malharvala20
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd

Aim : Implement Odd and Even Parity generator Circuit.

Theory :
Binary information transmitted through any communication
medium is subjected to external noise that can change bits from 1 to 0.
Hence binary error detection of error. Through these error can not be
rectified but they can be detected by of observing the frequency of
error. It can be decided if the fault lies in the system or it is just some
external noise.

The most common error detection code used is the parity bit. This is an
extra bit encoded with the information to make the total no of 1’s either
odd or even.

1. A 3-bit even parity generator.


If the information being sent is a 3-bit binary code , then the 3-bit even
parity generator generates a parity bit such that the number of bits in 4-
bit code is even.
The circuit diagram of 3-bit even parity generator and corresponding
truth table is shown in figure.

2. A 3-bit odd parity generator.


An alternate way of parity generation is to use odd parity generator.
Which generates a parity bit such that the number of bits in the bit code
is odd.
The circuit diagram of the 3-bit odd parity generator and corresponding
truth-table is shown in the figure.
Procedure :
[Link] the truth table to generate 3-bit odd/even parity.
[Link] the circuit for generated table.
[Link] the circuit in EWB.
[Link] the result for the truth tables.
Truth Table:

Message Parity
X Y Z Peven Podd
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 0

Circuit Diagram:

Fig: Parity Generator

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