2EC202
FPGA based System Design
Akash Mecwan & Vijay Savani
APEC, IT, NU.
Logic Values
Value Condition in Hardware
Circuit
0 Logic zero, false condition
1 Logic one, true condition
X Unknown logic value
Z High impedance, floating state
Verilog Basics
1/23/2026
2
Logic Strenths
1/23/2026 Ve
3
Gate Level Modeling
Basic Gates
Verilog Basics 5
Truth Table To Follow
Verilog Basics 6
Buffer and Not Gates
Verilog Basics (Input = Output) (Output = ~Input)
7
Bufif/Notif
Verilog Basics 8
Bufif/Notif (Cont…)
Verilog Basics 9
Gate Delays
Rise Delay
Fall Delay
Turnoff Delay
Rise delay → 0 → 1
Fall delay → 1 → 0
Verilog Basics Turn-off delay → output → Z 10
Gate Delays (Cont…)
Verilog Basics 11
Max, Min, Typ Delays
Verilog Basics 12
Delay Use
Verilog Basics 13
Prepare the Verilog Code for 1 – Bit Full Adder using
Gate Level Modelling
module full_adder_s (
input a,b,cin,
output sum,carry
);
wire w1,w2,w3,w4; //Internal connections
W3
xor(w1,a,b);
xor(sum,w1,cin); //Sum output W4
and(w2,a,b);
and(w3,b,cin);
and(w4,cin,a);
or(carry,w2,w3,w4); //carry output
endmodule W1
W2
Verilog Basics 14
Prepare the Verilog Code 4X1 MUX using Gate Level
Modelling
module m41(out, a, b, c, d, s0, s1);
output out;
input a, b, c, d, s0, s1;
wire sobar, s1bar, T1, T2, T3, T4;
not (s0bar, s0), (s1bar, s1);
and (T1, a, s0bar, s1bar), (T2, b, s0bar, s1),(T3, c, s0,
s1bar), (T4, d, s0, s1);
or(out, T1, T2, T3, T4);
endmodule
Verilog Basics 15
Data Flow Modelling
Outline
❖ Continuous Assignment
o The assign statement
o Implicit Continuous Assignment
o Implicit Net Declaration
❖ Gate Level Vs Data Flow Modeling
❖ Delays:
o Regular Assignment delay
o Implicit Continuous Assignment Delay
o Net Declaration Delay
❖ Expressions, Operands and Operators
❖ Parameter
❖ Issues with 4-valued logic
1/23/2026 Verilog Basics 17
Continuous Assignment
❖ Next level up: Dataflow modeling
o Continuous assignment
▪ The assign keyword
module my_and(output out, input in1, in2);
assign out = in1 & in2;
endmodule
1/23/2026 Verilog Basics 18
Rules for assign statement
▪ LHS data type:
o ONLY net (wire),
o scalar or vector net
o concatenations of scalar or vector net
o can not be scalar or vector reg
▪ Are always active [RHS evaluated and assign to LHS]
▪ RHS data type:
▪ register, net or function calls
▪ register can be scalar or vector
▪ Delay values can be specified in terms of time units,
similar to specifying delay for gate
▪ Default value for strength is strong1 and strong0
1/23/2026 Verilog Basics 19
Rules for assign statement
1/23/2026 Verilog Basics 20
Implicit continuous assignment
1/23/2026 Verilog Basics 21
Implicit Net declaration
1/23/2026 Verilog Basics 22
Gate Level vs. Dataflow Modeling
Gate Level Model
module mux4_to_1 (output
out,
input i0, i1, i2, i3, s1, s0);
wire s1n, s0n, y0, y1, y2, y3;
not (s1n, s1);
not (s0n, s0);
and (y0, i0, s1n, s0n); Dataflow Model
module mux4_to_1 (output out,
and (y1, i1, s1n, s0); input i0, i1, i2, i3, s1, s0);
and (y2, i2, s1, s0n);
assign out = (~s1 & ~s0 & i0)|
and (y3, i3, s1, s0); (~s1 & s0 & i1)|
( s1 & ~s0 & i2)|
or (out, y0, y1, y2, y3); ( s1 & s0 & i3);
endmodule endmodule
1/23/2026 Verilog Basics 23
Delays
Delays
❖ Control the time between the change in a
right-hand-side operand and when the
new value is assigned to the left-hand
side
1. Regular Assignment Delay
o Assign a delay value in a continuous assignment
statement & Specified after the keyword assign
2. Implicit Continuous Assignment Delay
o Equivalent to implicit continuous assignment
3. Net Declaration Delay
o A delay is specified along with net declaration
1/23/2026 Verilog Basics 25
Specifying Delays at Dataflow Level
1. Regular Assignment Delay
assign #10 out = in1 & in2;
A pulse of width less than the specified assignment
delay is not propagated to the output.
Delays to Dataflow Level are Inertial Delay
1/23/2026 Verilog Basics 26
Specifying Delays at Dataflow Level
2. Implicit Continuous Assignment Delay
wire #10 out = in1 & in2;
//same as
wire out;
assign #10 out = in1 & in2;
3. Net Declaration Delay
1/23/2026 Verilog Basics 27
Expression
Operands
Operators
Expression, Operands, Operators
Expressions are constructs that
combine operators and operands
to produce a result.
// Examples of expressions. Combines operands and
operators
o a^b
o addr1[20:17] + addr2[20:17]
o in1 | in2
1/23/2026 Verilog Basics 29
Expression, Operands, Operators
It Can be
o constants, integers, real numbers, nets, registers,
times, bit-select (one bit of vector net or a vector
register), part-select (selected bits of the vector net
or register vector), and memories or function calls
(functions are discussed later).
integer count, final_count;
final_count = count + 1; //count is an integer operand
real a, b, c;
c = a - b; //a and b are real operands
reg [15:0] reg1, reg2;
reg [3:0] reg_out;
reg_out = reg1[3:0] ^ reg2[3:0]; //reg1[3:0] and reg2[3:0] are
//part-select register operands
reg ret_value;
ret_value = calculate_parity(A, B);//calculate_parity is a
//function type operand
1/23/2026 Verilog Basics 30
Expression, Operands, Operators
❖ Operators act on the operands to produce desired
results.
❖ Examples:
o d1 && d2 // && is an operator on
operands d1 and d2
o !a[0] // ! is an operator on operand a[0]
o B >> 1 // >> is an operator on operands
B and 1
1/23/2026 Verilog Basics 31
Operators (ABCCE RRRLS)
Operator Category Operators Symbol
Arithmetic * / + - % **
Logical ! && ||
Relational > < <= >=
Equality == != === !===
Bitwise ~ & | ^ ^~ ~^
Reduction (out is one bit) & ~& | ~| ^ ~^ OR ^~
Shift >> << >>> <<<
Concatenation {}
Replication {{}}
Conditional ?:
1/23/2026 Verilog Basics 32
Arithmetic Operators
A = 4'b0011; +5
B = 4'b0100; -4
D = 6; E = 4; F=2;
A*B
D/E
A+B
B-A
• 4-valued logic issue:
13 % 3 x and z values
16 % 4 in1 = 4'b101x;
-7 % 2 in2 = 4'b1010;
7 % -2 sum = in1 + in2;
1/23/2026 Verilog Basics 33
Arithmetic Operators
1/23/2026 Verilog Basics 34
Logical and Relational Operators
❖ Logical Operators:
❖ Evaluate to 1-bit value
❖ ! && ||
❖ Operands: True:1, False:0, x or z => x
❖ Outcome: 0, 1, x
❖ Can take variable or expression as operand
1/23/2026 Verilog Basics 35
What will be the Hardware (RTL)
module test (a,b,c);
input a,b;
output c;
wire d,e;
assign e = a & d;
assign c = b | e;
endmodule
What if, wire d=1’b0;
What if, wire d= 1’b1;
1/23/2026 Verilog Basics 36
Logical and Relational Operators
1/23/2026 Verilog Basics 37
Logical and Relational Operators
❖ Relational Operators: [> < <= >=]
❖ Evaluate to logic 1 - If expression is True
❖ Evaluate to logic 0 - If expression is False
❖ “Unknown or z” value usually treated as x
(operand)
1/23/2026 Verilog Basics 38
Equality Operators
// A = 4, B = 3 // Z = 4'b1xxz, M = 4'b1xxz
// X = 4'b1010, Y = 4'b1101 // N = 4'b1xxx
X == Z -x
A == B - 0
X != Y - 1 Z === M - 1
Z === N - 0
M !== N - 1
1/23/2026 Verilog Basics 39
Bitwise Operators
❖ Bitwise Operators: [~ & | ^ ^~ ~^]
❖ Bit by Bit Operation
❖ If one operand is shorter than other, it will be
extended to zero [to match the length]
❖ Z is treated as X
❖ ~ is unary operator
1/23/2026 Verilog Basics 40
Bitwise Operators
// X = 4'b1010
// Y = 4'b1101
// Z = 4'b10x1
~X
X&Y
X|Y
X^Y
X ^~ Y
X&Z
1/23/2026 Verilog Basics 41
Reduction Operators
❖ Reduction Operators:
❖ and(&), nand(~&), or(|), nor(~|), xor(^),
xnor(~^)
❖ Takes only one operand
❖ Results in one bit output
❖ Works from right to left
1/23/2026 Verilog Basics 42
Reduction Operators
// X = 4'b1010
&X => 1’b0
|X => 1’b1
^X => 1’b0
1/23/2026 Verilog Basics 43
Shift Operators
// X = 4'b1100
Y = X >> 1;
Y = X << 1;
Y = X << 2;
integer a, b, c;
a = 0;
b = -10;
c = a + (b >> 3);
1/23/2026 Verilog Basics 44
Concatenation Operator
❖Provides mechanism to append multiple
operands
❖Unsized operands not allowed
// A = 1'b1, B = 2'b00,
// C = 2'b10, D = 3'b110
Y = {B , C} Y = 4'b0010
Y = {A , B , C , D , 3'b001} Y = 11'b100……01
Y = {A , B[0], C[1]} Y = 3'b101
1/23/2026 Verilog Basics 45
Replication Operator
reg A;
reg [1:0] B, C;
reg [2:0] D;
A = 1'b1; B = 2'b00; C = 2'b10; D = 3'b110;
Y = { 4{A} }
Y = { 4{A} , 2{B} }
Y = { 4{A} , 2{B} , C }
1/23/2026 Verilog Basics 46
Conditional Operator
Port/Const/Vari = Condition ? True_Value : False_Value;
assign addr_bus = drive_enable ? addr_out : 36'bz;
assign out = control ? in1 : in0;
condition ? true_value : false_value;
1/23/2026 Verilog Basics 47
Operators Precedence
❖ Unary: [+ - ! ~]
❖ Mul, Div, Mod: * / %
❖ Add, Sub: + -
❖ Shift: >> <<
❖ Relational: < <= => >
❖ Equality: == != === !==
❖ Reduction
❖ Logical
❖ Conditional
1/23/2026 Verilog Basics 48
Radix Specifiers
1/23/2026 Verilog Basics 49
Examples - MUX
1/23/2026 Verilog Basics 50
Sequential Logic at Dataflow Level
1/23/2026 Verilog Basics 51
Sequential Logic at Dataflow Level
❖ Negative Edge Triggered D-FF
module edge_dff(q, qbar, d, clk, clear);
output q,qbar;
input d, clk, clear;
wire s, sbar, r, rbar,cbar;
assign cbar = ~clear;
assign sbar = ~(rbar & s),
s = ~(sbar & cbar & ~clk),
r = ~(rbar & ~clk & s),
rbar = ~(r & cbar & d);
assign q = ~(s & qbar),
qbar = ~(q & r & cbar);
endmodule
1/23/2026 Verilog Basics 52
Edge-Triggered T-FF
module edge_dff(q, qbar, d, clk, clear);
...
endmodule
module T_FF(q, clk, clear);
output q;
input clk, clear;
edge_dff ff1(q, ,~q, clk, clear);
endmodule
1/23/2026 Verilog Basics 53
Structural Modeling
Structural Modelling
❖ Structural style of modeling in Verilog
describes hardware by explicitly
connecting components (gates or
modules) together, instead of describing
hardware logic itself
E.g.
o 1 bit Full adders using two Half Adder
o 16X1 MUX using 4X1 MUX
1/23/2026 Verilog Basics 55
Structural Modelling (Cont…)
module structural (a,b,c,d,e);// main module
input a,b,c,d; // main module inputs
output e; // main module outputs
wire q,r;
gatelevel m1(a,b,q); // call already available
gatelevel m2(c,d,r); //module with name
gatelevel m3(q,r,e); // gatelevel with two
//inputs and one output
endmodule
1/23/2026 Verilog Basics 56
Structural Modelling (Cont…)
❖ The already available module must have the entire
Verilog code written, available in the same project.
❖ The module that is called can be written using any
style of modelling.
❖ If a separate code is not available to call, it can be
written in the same Verilog code of structural
modelling at the end of the main code.
1/23/2026 Verilog Basics 57
4 Bit Full Adder using 1 Bit Full Adder
❖ Code for 1 bit full adder:
module full_adder_s (
input a,b,cin,
output sum,carry
);
wire w1,w2,w3,w4; //Internal connections
xor(w1,a,b);
xor(sum,w1,cin); //Sum output
and(w2,a,b);
and(w3,b,cin);
and(w4,cin,a);
or(carry,w2,w3,w4); //carry output
endmodule
1/23/2026 Verilog Basics 58
4 Bit Full Adder using 1 Bit Full Adder (Cont…)
❖ One bit full adder module:
a
sum
b 1 Bit
Full Adder carry
cin
1/23/2026 Verilog Basics 59
4 Bit Full Adder using 1 Bit Full Adder (Cont…)
❖ Four bit full adder module:
a(0) – a(3)
sum(0) – sum(3)
b(0) – b(3) 4 Bit
Full Adder cout
cin
module full_adder_4b(sum,cout,a,b,cin);
output [3:0] sum;
output cout;
input [3:0] a,b;
input cin;
1/23/2026 Verilog Basics 60
4 Bit Full Adder using 1 Bit Full Adder (Cont…)
❖ Four bit full adder module:
sum(3)
sum(2)
sum(1) b(3) a(3)
sum(0) b(2) a(2)
b(1) a(1)
b(0) a(0)
cout
full_adder_s f1 (sum[0], cout0, a[0], b[0], cin);
full_adder_s f2 (sum[1], cout1, a[1], b[1], cout0);
full_adder_s f3 (sum[2], cout2, a[2], b[2], cout1);
full_adder_s f4 (sum[3], cout, a[3], b[3], cout2);
1/23/2026 Verilog Basics 61
4 Bit Full Adder using 1 Bit Full Adder (Cont…)
module full_adder_4b(sum,cout,a,b,cin);
output [3:0] sum;
output cout;
input [3:0] a,b;
input cin;
wire cout0,cout1,cout2;
full_adder_s f1 (sum[0], cout0, a[0], b[0], cin);
full_adder_s f2 (sum[1], cout1, a[1], b[1], cout0);
full_adder_s f3 (sum[2], cout2, a[2], b[2], cout1);
full_adder_s f4 (sum[3], cout, a[3], b[3], cout2);
endmodule
1/23/2026 Verilog Basics 62
Port Mapping
module full_adder_s ( module full_adder_4b(sum,cout,a,b,cin);
input a,b,cin, output [3:0] sum;
output sum,carry output cout;
); input [3:0] a,b;
input cin;
❖ Maintain the sequence
full_adder_s f1 (sum[0], cout0, a[0], b[0], cin);
❖ Explicit Port Mapping
full_adder_s (.sum(0)(sum), .cout0(carry), .a(0)(a), .b(0)(b), .cin(cin) );
1/23/2026 Verilog Basics 63
Thank you…!
Verilog Basics 64
1/23/2026