Design and Simulation of a CMOS-Based Pulse-Width Adding DAC for High-Speed
Operation
Review of Related Literature
The progress of modern integrated circuits (ICs) comes from ongoing improvements in three
main areas: dynamic bandwidth (speed), managing complexity through digitalization, and
physical integration with miniaturization. Three primary trends are to be explored, using
recent academic literature focusing on high-speed data converters and analog circuits.
Extending Dynamic Bandwidth and High-Speed Operation
A major limitation for many high-speed applications is the low operating bandwidth of
traditional data conversion methods. For example, a digital-to-analog converter (DAC) that
uses pulse-width adding showed a bandwidth of only 10kHz [1]. To address this issue, the
industry has moved toward high-speed modes for DACs [2] and continuous-time designs for
analog-to-digital converters (ADCs).
Recent research shows successful designs that reach much higher speeds. For applications that
require broad signal capture, a continuous-time 2-2 MASH ΔΣ ADC built in 40nm CMOS
achievedanimpressive50MHzbandwidthanda76.8dB signal-to-noise-and-distortion ratio (SNDR)
[3]. On the DAC side, higher sample rates are also being achieved. For instance, a 12-bit rad-
hard resistor string DAC made for space uses operates at 3MS/s [4]. This ongoing push to
boost bandwidth is essential for supporting next-generation wireless communications and
high-frequency signal processing.
Shifting Complexity to the Digital Domain
Another major trend focuses on simplifying the analog signal chain by moving reconstruction
complexity into the digital domain. This approach primarily addresses the challenge of
relying on a high-precision external analog low-pass filter (LPF) for signal reconstruction.
This component often has non-ideal characteristics and occupies considerable space.
Researchers have shown strong interest in replacing conventional analog blocks with options
that work better with digital systems, leading to the development of digitalized analog
integrated circuits [5].
This digitalization often includes modulation techniques like ΔΣ (delta-sigma) to push
quantization noise out of the signal band. This allows for a much simpler analog LPF. A
notable example is the continuous-time 2-2 MASH ΔΣ ADC, which uses digital calibration
through a Least Mean Squares (LMS) algorithm to align its digital noise cancellation filter
with the analog transfer function [3]. This digital calibration not only simplifies the analog
anti-aliasing filter but also improves overall performance metrics like SNDR. This shows that
transferring complexity to the digital domain can enhance performance and make analog
design easier.
Enhancing Integration and Miniaturization via CMOS Technology
For system integration and miniaturization, research has clearly favored using low-area,
low-power Complementary Metal-Oxide-Semiconductor (CMOS) technologies. This
approach significantly reduces die size and power consumption, which is crucial for portable,
implanted, or space-constrained systems.
The trend toward smaller technology nodes is apparent across different circuit types.
High-speed ADCs are often made using advanced technologies, such as the 40 nm CMOS
node for the 50MHz bandwidth ΔΣ ADC [3]. Even components intended for extreme
environments, like the 3MS/s DAC, are built using standard CMOS technology (0.13μm) by
applying special design techniques that provide radiation hardness [4]. Further pushing
integration limits, a low-power biopotential amplifier for biomedical applications was
developed in a 28nm CMOS technology, resulting in a compact die area of just 2500μm2 [5].
These examples show how complex, high-performance, and specialized analog functions can
successfully move into smaller CMOS nodes to achieve better integration and power
efficiency.
Reference List:
[1] V. Viegas and J. M. D. Pereira, “Digital to analog converter based on pulse-width adding,”
Measurement Sensors, vol. 38, p. 101418, Dec. 2024, doi: 10.1016/[Link].2024.101418.
[2] V. V. Romashov, A. N. Doktorov, K. A. Yakimenko, and N. A. Sochneva, “Application
high-speed digital-to-analog converters for direct digital synthesis of high-frequency radio
signals,” Journal of Physics Conference Series, vol. 1632, no. 1, p. 012023, Sep. 2020, doi:
10.1088/1742-6596/1632/1/012023.
[3] Z. Li, X. Shang, H. Feng, and X. Xing, “A Power-Efficient 50 MHz-BW 76.8 dB
Signal-to-Noise-and-Distortion Ratio Continuous-Time 2-2 MASH Delta-Sigma
Analog-to-Digital Converter with Digital Calibration,” Journal of Low Power Electronics
and Applications, vol. 15, no. 2, p. 20, Apr. 2025, doi: 10.3390/jlpea15020020.
[4] C. Calligaro and U. Gatti, “A CMOS 12-Bit 3MS/s Rad-Hard Digital-to-Analog
Converter Based on a High-Linearity Resistor String Poly-Matrix,” Chips, vol. 3, no. 2, pp.
129–152, May 2024, doi: 10.3390/chips3020006.
[5] Z. Zhu and S. Liu, “Digitalized analog integrated circuits,” Fundamental Research, vol. 4,
no. 6, pp. 1415–1430, Feb. 2023, doi: 10.1016/[Link].2023.01.006.
[6] E. R. R. Koleibi et al., “Design and Implementation of a Low-Power Biopotential
Amplifier in 28 nm CMOS Technology with a Compact Die-Area of 2500 μm2 and an
Ultra-High Input Impedance,” Sensors, vol. 25, no. 7, p. 2320, Apr. 2025, doi:
10.3390/s25072320.