12/01/2026

Computer Organization & Design

Topic # 02

RISC-V Instruction Set Architecture

SE – CIS

Course Teacher : Anita Ali

RV32I Instruction Formats

• 40 core instructions

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Arithmetic/Logical Instructions

Arithmetic/Logical Instructions
Example
Registers

add s0, s1, s2

Instruction Source
mnemonic Destination Registers
Register

# Action : s0  s1 + s2
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Arithmetic/Logical Instructions

1. add s0, s1, s2 # s0  s1 + s2

2. sub s0, s1, s2 # s0  s1 – s2

Register direct
addressing mode
3. and s1, s0, s3 # s1  s0 AND s3

4. or s0, s1, s2 # s0  s1 OR s2

5. addi s0, s1, 9 # s0  s1 + 9 9 is immediate operand

S0, s1 are register-based operands
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RISC-V Assembly
Task
Translate following high-level language statement into RISC-V assembly language and also provide
corresponding machine code.
z = (w + x) – (y - p)

Working
Let's assume following variable-register associations

Variables z w x y p

Registers s2 s3 s4 s5 s6
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Assembly Code

Registers

• There are 32 registers

each of 32 bits.

• Registers are
numbered 0 to 31

• They are given a

special name as well
to indicate a
register’s
conventional
purpose.

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Machine Code

• In order to generate machine code, we must know instruction formats used in

RISC-V

• In this program all instructions are arithmetic instructions

• Most of the arithmetic/logical instructions in RISC-V use R format

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R (Register) Format
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
funct7 rs2 rs1 funct3 rd opcode

• opcode: denotes the operation and format of the instruction. All R-type
instructions have op = 011 0011 = 0x33 = 51)10
• rs1 : identifier of first source register
• rs2 : identifier of second source register
• rd : identifier of destination register
• funct7 : additional opcode field, distinguishes among R-type instructions
• funct3 : additional opcode field, distinguishes among R-type instructions

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RV32I: R-Type Instructions

funct3 funct7
Machine Code Instruction S2-s11 x18-x27
add 0 0 t0-t2, t3-t6 x5-x7, x28-x31
opcode 51 = 0x33 sub 0 32

funct7 rs2 rs1 funct3 rd opcode

Assembly Code 7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

add x5, x19, x20

sub x6, x21, x22

sub x18, x5, x6

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funct3 funct7
Machine Code Instruction S2-s11 x18-x27
add 0 0 t0-t2, t3-t6 x5-x7, x28-x31
opcode 51 = 0x33 sub 0 32

funct7 rs2 rs1 funct3 rd opcode Hex code

Assembly Code 7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

add x5, x19, x20

sub x6, x21, x22

sub x18, x5, x6

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Class Activity
Give MIPS machine code in binary & hex format for following instructions of
program just discussed

sub x6, x21, x22

sub x18, x5, x6

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Data Transfer Instructions

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Word Length
• Number of bits that can be simultaneously accessed from main memory (MM)

• Data is accessed from MM via data bus

• So, word length is same as width of data bus

• For RISC-V word length is 4 bytes (32 bits)

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Load Operation

• Transferring (copying) data from main memory to a processor register is called

load operation.

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Store Operation

• Transferring (copying) data from a processor register to main memory is called

store operation.

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Data Transfer Instructions

1. lw rd , imm (rs1)

2. sw rs2 , imm (rs1)

• It is known as Register – Register Architecture &

• It is also called Load & Store Architecture

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Load Instruction
lw rd , imm (rs1)

# rd  Memory [ rs + imm ]
• This instruction transfers one word (4 bytes) from MM starting at address (rs1 +
imm) into processor register rd
• Register rs1 holds the base (reference) address
• Imm specifies displacement in bytes
• And the required memory address is formed by adding this offset to base address
• Hence, this is called base addressing ( or register-indirect with immediate offset
addressing)
• The register holding base address is known as base register
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Load Instruction

lw x18 , 0 (x19)

x18
x18 20000000 h 3000 h 78 h
x19 3000 h
x19 3000 h 3001 h 56 h x20 4000 h
x20 4000 h 3002 h 34 h Registers
Registers (before) 3003 h 12h (after)
Memory

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Store Instruction

sw rs2 , offset (rs1)

# Memory [rs1 + imm]  rs2

• This instruction transfers one word (4 bytes) from processor register rs2
to main memory starting at address (rs1 + imm)

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Store Instruction
sw x18 , 0 (x19)

3000 h 11 h 3000 h
x18 12345678 h
3001 h 22 h 3001 h
x19 3000 h
3002 h 33 h 3002 h
x20 4000 h
3003 h 44 h 3003 h
Registers
Memory Memory
(before) (after)

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Compilation Example S2-s11 x18-x27

t0-t2, t3-t6 x5-x7, x28-x31

Task : Assuming that variable win is associated with register x18 & puzzle is an
array of words with base address in register x19. Compile the following python
statement into RISC-V assembly language. Also provide corresponding machine
code.

puzzle [3] = puzzle [1] – puzzle [2]

puzzle [8] = win – 2

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Assembly Code S2-s11 x18-x27

t0-t2, t3-t6 x5-x7, x28-x31

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RV32I Instruction Formats

• 40 core instructions

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I (Immediate) Format
12 bits 5 bits 3 bits 5 bits 7 bits
Immediate [11:0] rs1 funct3 rd opcode

• Both lw & addi use I-Format

• opcode: denotes the operation

• rs1 : base register identifier in case of load instructions and first source register

identifier in all other instructions using I format (e.g. addi, andi, ori etc.)

• rd : destination register identifier

• immediate: 12-bit signed offset expressed in bytes (expressed in decimal here)

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RV32I: I-type Instructions

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12 5 3 5 7

Machine Code immediate rs1 funct3 rd opcode

S2-s11 x18-x27
t0-t2, t3-t6 x5-x7, x28-x31

lw x5, 4 (x19) I – type

lw x6, 8 (x19) I – type

sub x7, x5, x6 R – type

sw x7, 12 (x19) S – type

addi x28, x18, -5 I – type

sw x28, 32 (x19) S – type

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S (Store) Format
7 5 5 3 5 7
Immediate[11:5] rs2 rs1 funct3 immediate [4:0] opcode

• sw uses S-Format
• opcode: denotes the operation, opcode =35 for S–type instructions

• rs1 : base register identifier for store instructions

• rs2 : destination register identifier

• immediate: 12-bit signed offset expressed in bytes (expressed in decimal here) – split

into two fields.

• funct3 : distinguishes among various S-type instructions

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RV32I: S-type Instructions

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12 5 3 5 7

Machine Code immediate rs1 funct3 rd opcode

S2-s11 x18-x27
t0-t2, t3-t6 x5-x7, x28-x31

lw x5, 4 (x19) I – type

lw x6, 8 (x19) I – type

sub x7, x5, x6 R – type

sw x7, 12 (x19) S – type

addi x28, x18, -5 I – type

sw x28, 32 (x19) S – type

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Class Activity
Give corresponding machine code in binary & hex format for this program

Assembly Code Machine Code (binary) Machine Code (hex)

lw x5, 4 (x19) I – type

lw x6, 8 (x19) I – type

sub x7, x5, x6 R – type

sw x7, 12 (x19) S – type

addi x28, x18, -5 I – type

sw x28, 32 (x19) S – type

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